1 /*
2 * Copyright 2003 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "drm-uapi/drm_fourcc.h"
27 #include <errno.h>
28 #include <time.h>
29 #include <unistd.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
44
45 #include "utils.h"
46 #include "util/disk_cache.h"
47 #include "util/driconf.h"
48 #include "util/u_memory.h"
49
50 #include "common/gen_defines.h"
51
52 static const driOptionDescription brw_driconf[] = {
53 DRI_CONF_SECTION_PERFORMANCE
54 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
55 * DRI_CONF_BO_REUSE_ALL
56 */
57 DRI_CONF_OPT_E(bo_reuse, 1, 0, 1,
58 "Buffer object reuse",
59 DRI_CONF_ENUM(0, "Disable buffer object reuse")
60 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects"))
61 DRI_CONF_MESA_NO_ERROR(false)
62 DRI_CONF_MESA_GLTHREAD(false)
63 DRI_CONF_SECTION_END
64
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_PRECISE_TRIG(false)
67
68 DRI_CONF_OPT_I(clamp_max_samples, -1, 0, 0,
69 "Clamp the value of GL_MAX_SAMPLES to the "
70 "given integer. If negative, then do not clamp.")
71 DRI_CONF_SECTION_END
72
73 DRI_CONF_SECTION_DEBUG
74 DRI_CONF_ALWAYS_FLUSH_BATCH(false)
75 DRI_CONF_ALWAYS_FLUSH_CACHE(false)
76 DRI_CONF_DISABLE_THROTTLING(false)
77 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN(false)
78 DRI_CONF_FORCE_GLSL_VERSION(0)
79 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS(false)
80 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED(false)
81 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION(false)
82 DRI_CONF_ALLOW_EXTRA_PP_TOKENS(false)
83 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER(false)
84 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION(false)
85 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH(false)
86 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION(false)
87 DRI_CONF_FORCE_COMPAT_PROFILE(false)
88 DRI_CONF_FORCE_GLSL_ABS_SQRT(false)
89 DRI_CONF_FORCE_GL_VENDOR()
90
91 DRI_CONF_OPT_B(shader_precompile, true, "Perform code generation at shader link time.")
92 DRI_CONF_SECTION_END
93
94 DRI_CONF_SECTION_MISCELLANEOUS
95 DRI_CONF_GLSL_ZERO_INIT(false)
96 DRI_CONF_VS_POSITION_ALWAYS_INVARIANT(false)
97 DRI_CONF_ALLOW_RGB10_CONFIGS(false)
98 DRI_CONF_ALLOW_RGB565_CONFIGS(true)
99 DRI_CONF_ALLOW_FP16_CONFIGS(false)
100 DRI_CONF_SECTION_END
101 };
102
103 static char *
brw_driconf_get_xml(UNUSED const char * driver_name)104 brw_driconf_get_xml(UNUSED const char *driver_name)
105 {
106 return driGetOptionsXml(brw_driconf, ARRAY_SIZE(brw_driconf));
107 }
108
109 static const __DRIconfigOptionsExtension brw_config_options = {
110 .base = { __DRI_CONFIG_OPTIONS, 2 },
111 .xml = NULL,
112 .getXml = brw_driconf_get_xml,
113 };
114
115 #include "intel_batchbuffer.h"
116 #include "intel_buffers.h"
117 #include "brw_bufmgr.h"
118 #include "intel_fbo.h"
119 #include "intel_mipmap_tree.h"
120 #include "intel_screen.h"
121 #include "intel_tex.h"
122 #include "intel_image.h"
123
124 #include "brw_context.h"
125
126 #include "drm-uapi/i915_drm.h"
127
128 /**
129 * For debugging purposes, this returns a time in seconds.
130 */
131 double
get_time(void)132 get_time(void)
133 {
134 struct timespec tp;
135
136 clock_gettime(CLOCK_MONOTONIC, &tp);
137
138 return tp.tv_sec + tp.tv_nsec / 1000000000.0;
139 }
140
141 static const __DRItexBufferExtension intelTexBufferExtension = {
142 .base = { __DRI_TEX_BUFFER, 3 },
143
144 .setTexBuffer = intelSetTexBuffer,
145 .setTexBuffer2 = intelSetTexBuffer2,
146 .releaseTexBuffer = intelReleaseTexBuffer,
147 };
148
149 static void
intel_dri2_flush_with_flags(__DRIcontext * cPriv,__DRIdrawable * dPriv,unsigned flags,enum __DRI2throttleReason reason)150 intel_dri2_flush_with_flags(__DRIcontext *cPriv,
151 __DRIdrawable *dPriv,
152 unsigned flags,
153 enum __DRI2throttleReason reason)
154 {
155 struct brw_context *brw = cPriv->driverPrivate;
156
157 if (!brw)
158 return;
159
160 struct gl_context *ctx = &brw->ctx;
161
162 _mesa_glthread_finish(ctx);
163
164 FLUSH_VERTICES(ctx, 0);
165
166 if (flags & __DRI2_FLUSH_DRAWABLE)
167 intel_resolve_for_dri2_flush(brw, dPriv);
168
169 if (reason == __DRI2_THROTTLE_SWAPBUFFER)
170 brw->need_swap_throttle = true;
171 if (reason == __DRI2_THROTTLE_FLUSHFRONT)
172 brw->need_flush_throttle = true;
173
174 intel_batchbuffer_flush(brw);
175 }
176
177 /**
178 * Provides compatibility with loaders that only support the older (version
179 * 1-3) flush interface.
180 *
181 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
182 */
183 static void
intel_dri2_flush(__DRIdrawable * drawable)184 intel_dri2_flush(__DRIdrawable *drawable)
185 {
186 intel_dri2_flush_with_flags(drawable->driContextPriv, drawable,
187 __DRI2_FLUSH_DRAWABLE,
188 __DRI2_THROTTLE_SWAPBUFFER);
189 }
190
191 static const struct __DRI2flushExtensionRec intelFlushExtension = {
192 .base = { __DRI2_FLUSH, 4 },
193
194 .flush = intel_dri2_flush,
195 .invalidate = dri2InvalidateDrawable,
196 .flush_with_flags = intel_dri2_flush_with_flags,
197 };
198
199 static const struct intel_image_format intel_image_formats[] = {
200 { DRM_FORMAT_ABGR16161616F, __DRI_IMAGE_COMPONENTS_RGBA, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F, 8 } } },
202
203 { DRM_FORMAT_XBGR16161616F, __DRI_IMAGE_COMPONENTS_RGB, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F, 8 } } },
205
206 { DRM_FORMAT_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } },
208
209 { DRM_FORMAT_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } },
211
212 { DRM_FORMAT_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010, 4 } } },
214
215 { DRM_FORMAT_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010, 4 } } },
217
218 { DRM_FORMAT_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
220
221 { DRM_FORMAT_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
223
224 { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
226
227 { __DRI_IMAGE_FOURCC_SXRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8, 4 } } },
229
230 { DRM_FORMAT_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } },
232
233 { DRM_FORMAT_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } },
235
236 { DRM_FORMAT_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } },
238
239 { DRM_FORMAT_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } },
241
242 { DRM_FORMAT_R8, __DRI_IMAGE_COMPONENTS_R, 1,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
244
245 { DRM_FORMAT_R16, __DRI_IMAGE_COMPONENTS_R, 1,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } },
247
248 { DRM_FORMAT_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
249 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
250
251 { DRM_FORMAT_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } },
253
254 { DRM_FORMAT_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
256 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
257 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
258
259 { DRM_FORMAT_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
261 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
262 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
263
264 { DRM_FORMAT_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
266 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
267 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
268
269 { DRM_FORMAT_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
270 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
271 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
272 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
273
274 { DRM_FORMAT_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
275 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
276 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
277 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
278
279 { DRM_FORMAT_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
280 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
281 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
282 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
283
284 { DRM_FORMAT_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
285 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
286 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
287 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
288
289 { DRM_FORMAT_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
290 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
291 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
292 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
293
294 { DRM_FORMAT_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
295 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
296 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
297 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
298
299 { DRM_FORMAT_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
300 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
301 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
302 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
303
304 { DRM_FORMAT_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
305 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
306 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
307
308 { DRM_FORMAT_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
309 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
310 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
311
312 { DRM_FORMAT_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
313 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
314 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
315
316 { DRM_FORMAT_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
317 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
318 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
319
320 { DRM_FORMAT_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
321 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
322 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
323
324 { DRM_FORMAT_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1,
325 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
326
327 { DRM_FORMAT_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1,
328 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } },
329
330 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
331 * and treat them as planar buffers in the compositors.
332 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
333 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
334 * clusters and places pairs and places U into the G component and
335 * V into A. This lets the texture sampler interpolate the Y
336 * components correctly when sampling from plane 0, and interpolate
337 * U and V correctly when sampling from plane 1. */
338 { DRM_FORMAT_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
339 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
340 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
341 { DRM_FORMAT_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2,
342 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
343 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }
344 };
345
346 static const struct {
347 uint64_t modifier;
348 unsigned since_gen;
349 } supported_modifiers[] = {
350 { .modifier = DRM_FORMAT_MOD_LINEAR , .since_gen = 1 },
351 { .modifier = I915_FORMAT_MOD_X_TILED , .since_gen = 1 },
352 { .modifier = I915_FORMAT_MOD_Y_TILED , .since_gen = 6 },
353 { .modifier = I915_FORMAT_MOD_Y_TILED_CCS , .since_gen = 9 },
354 };
355
356 static bool
modifier_is_supported(const struct gen_device_info * devinfo,const struct intel_image_format * fmt,int dri_format,uint64_t modifier)357 modifier_is_supported(const struct gen_device_info *devinfo,
358 const struct intel_image_format *fmt, int dri_format,
359 uint64_t modifier)
360 {
361 const struct isl_drm_modifier_info *modinfo =
362 isl_drm_modifier_get_info(modifier);
363 int i;
364
365 /* ISL had better know about the modifier */
366 if (!modinfo)
367 return false;
368
369 if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) {
370 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
371 if (INTEL_DEBUG & DEBUG_NO_RBC)
372 return false;
373
374 /* CCS_E is not supported for planar images */
375 if (fmt && fmt->nplanes > 1)
376 return false;
377
378 if (fmt) {
379 assert(dri_format == 0);
380 dri_format = fmt->planes[0].dri_format;
381 }
382
383 mesa_format format = driImageFormatToGLFormat(dri_format);
384 /* Whether or not we support compression is based on the RGBA non-sRGB
385 * version of the format.
386 */
387 format = _mesa_format_fallback_rgbx_to_rgba(format);
388 format = _mesa_get_srgb_format_linear(format);
389 if (!isl_format_supports_ccs_e(devinfo,
390 brw_isl_format_for_mesa_format(format)))
391 return false;
392 }
393
394 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
395 if (supported_modifiers[i].modifier != modifier)
396 continue;
397
398 return supported_modifiers[i].since_gen <= devinfo->gen;
399 }
400
401 return false;
402 }
403
404 static uint64_t
tiling_to_modifier(uint32_t tiling)405 tiling_to_modifier(uint32_t tiling)
406 {
407 static const uint64_t map[] = {
408 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
409 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
410 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
411 };
412
413 assert(tiling < ARRAY_SIZE(map));
414
415 return map[tiling];
416 }
417
418 static void
intel_image_warn_if_unaligned(__DRIimage * image,const char * func)419 intel_image_warn_if_unaligned(__DRIimage *image, const char *func)
420 {
421 uint32_t tiling, swizzle;
422 brw_bo_get_tiling(image->bo, &tiling, &swizzle);
423
424 if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) {
425 _mesa_warning(NULL, "%s: offset 0x%08x not on tile boundary",
426 func, image->offset);
427 }
428 }
429
430 static const struct intel_image_format *
intel_image_format_lookup(int fourcc)431 intel_image_format_lookup(int fourcc)
432 {
433 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
434 if (intel_image_formats[i].fourcc == fourcc)
435 return &intel_image_formats[i];
436 }
437
438 return NULL;
439 }
440
441 static bool
intel_image_get_fourcc(__DRIimage * image,int * fourcc)442 intel_image_get_fourcc(__DRIimage *image, int *fourcc)
443 {
444 if (image->planar_format) {
445 *fourcc = image->planar_format->fourcc;
446 return true;
447 }
448
449 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
450 if (intel_image_formats[i].planes[0].dri_format == image->dri_format) {
451 *fourcc = intel_image_formats[i].fourcc;
452 return true;
453 }
454 }
455 return false;
456 }
457
458 static __DRIimage *
intel_allocate_image(struct intel_screen * screen,int dri_format,void * loaderPrivate)459 intel_allocate_image(struct intel_screen *screen, int dri_format,
460 void *loaderPrivate)
461 {
462 __DRIimage *image;
463
464 image = calloc(1, sizeof *image);
465 if (image == NULL)
466 return NULL;
467
468 image->screen = screen;
469 image->dri_format = dri_format;
470 image->offset = 0;
471
472 image->format = driImageFormatToGLFormat(dri_format);
473 if (dri_format != __DRI_IMAGE_FORMAT_NONE &&
474 image->format == MESA_FORMAT_NONE) {
475 free(image);
476 return NULL;
477 }
478
479 image->internal_format = _mesa_get_format_base_format(image->format);
480 image->data = loaderPrivate;
481
482 return image;
483 }
484
485 /**
486 * Sets up a DRIImage structure to point to a slice out of a miptree.
487 */
488 static void
intel_setup_image_from_mipmap_tree(struct brw_context * brw,__DRIimage * image,struct intel_mipmap_tree * mt,GLuint level,GLuint zoffset)489 intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
490 struct intel_mipmap_tree *mt, GLuint level,
491 GLuint zoffset)
492 {
493 intel_miptree_make_shareable(brw, mt);
494
495 intel_miptree_check_level_layer(mt, level, zoffset);
496
497 image->width = minify(mt->surf.phys_level0_sa.width,
498 level - mt->first_level);
499 image->height = minify(mt->surf.phys_level0_sa.height,
500 level - mt->first_level);
501 image->pitch = mt->surf.row_pitch_B;
502
503 image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
504 &image->tile_x,
505 &image->tile_y);
506
507 brw_bo_unreference(image->bo);
508 image->bo = mt->bo;
509 brw_bo_reference(mt->bo);
510 }
511
512 static __DRIimage *
intel_create_image_from_name(__DRIscreen * dri_screen,int width,int height,int format,int name,int pitch,void * loaderPrivate)513 intel_create_image_from_name(__DRIscreen *dri_screen,
514 int width, int height, int format,
515 int name, int pitch, void *loaderPrivate)
516 {
517 struct intel_screen *screen = dri_screen->driverPrivate;
518 __DRIimage *image;
519 int cpp;
520
521 image = intel_allocate_image(screen, format, loaderPrivate);
522 if (image == NULL)
523 return NULL;
524
525 if (image->format == MESA_FORMAT_NONE)
526 cpp = 1;
527 else
528 cpp = _mesa_get_format_bytes(image->format);
529
530 image->width = width;
531 image->height = height;
532 image->pitch = pitch * cpp;
533 image->bo = brw_bo_gem_create_from_name(screen->bufmgr, "image",
534 name);
535 if (!image->bo) {
536 free(image);
537 return NULL;
538 }
539 image->modifier = tiling_to_modifier(image->bo->tiling_mode);
540
541 return image;
542 }
543
544 static __DRIimage *
intel_create_image_from_renderbuffer(__DRIcontext * context,int renderbuffer,void * loaderPrivate)545 intel_create_image_from_renderbuffer(__DRIcontext *context,
546 int renderbuffer, void *loaderPrivate)
547 {
548 __DRIimage *image;
549 struct brw_context *brw = context->driverPrivate;
550 struct gl_context *ctx = &brw->ctx;
551 struct gl_renderbuffer *rb;
552 struct intel_renderbuffer *irb;
553
554 rb = _mesa_lookup_renderbuffer(ctx, renderbuffer);
555 if (!rb) {
556 _mesa_error(ctx, GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
557 return NULL;
558 }
559
560 irb = intel_renderbuffer(rb);
561 intel_miptree_make_shareable(brw, irb->mt);
562 image = calloc(1, sizeof *image);
563 if (image == NULL)
564 return NULL;
565
566 image->internal_format = rb->InternalFormat;
567 image->format = rb->Format;
568 image->modifier = tiling_to_modifier(
569 isl_tiling_to_i915_tiling(irb->mt->surf.tiling));
570 image->offset = 0;
571 image->data = loaderPrivate;
572 brw_bo_unreference(image->bo);
573 image->bo = irb->mt->bo;
574 brw_bo_reference(irb->mt->bo);
575 image->width = rb->Width;
576 image->height = rb->Height;
577 image->pitch = irb->mt->surf.row_pitch_B;
578 image->dri_format = driGLFormatToImageFormat(image->format);
579 image->has_depthstencil = irb->mt->stencil_mt? true : false;
580
581 rb->NeedsFinishRenderTexture = true;
582 return image;
583 }
584
585 static __DRIimage *
intel_create_image_from_texture(__DRIcontext * context,int target,unsigned texture,int zoffset,int level,unsigned * error,void * loaderPrivate)586 intel_create_image_from_texture(__DRIcontext *context, int target,
587 unsigned texture, int zoffset,
588 int level,
589 unsigned *error,
590 void *loaderPrivate)
591 {
592 __DRIimage *image;
593 struct brw_context *brw = context->driverPrivate;
594 struct gl_texture_object *obj;
595 struct intel_texture_object *iobj;
596 GLuint face = 0;
597
598 obj = _mesa_lookup_texture(&brw->ctx, texture);
599 if (!obj || obj->Target != target) {
600 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
601 return NULL;
602 }
603
604 if (target == GL_TEXTURE_CUBE_MAP)
605 face = zoffset;
606
607 _mesa_test_texobj_completeness(&brw->ctx, obj);
608 iobj = intel_texture_object(obj);
609 if (!obj->_BaseComplete || (level > 0 && !obj->_MipmapComplete)) {
610 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
611 return NULL;
612 }
613
614 if (level < obj->BaseLevel || level > obj->_MaxLevel) {
615 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
616 return NULL;
617 }
618
619 if (target == GL_TEXTURE_3D && obj->Image[face][level]->Depth < zoffset) {
620 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
621 return NULL;
622 }
623 image = calloc(1, sizeof *image);
624 if (image == NULL) {
625 *error = __DRI_IMAGE_ERROR_BAD_ALLOC;
626 return NULL;
627 }
628
629 image->internal_format = obj->Image[face][level]->InternalFormat;
630 image->format = obj->Image[face][level]->TexFormat;
631 image->modifier = tiling_to_modifier(
632 isl_tiling_to_i915_tiling(iobj->mt->surf.tiling));
633 image->data = loaderPrivate;
634 intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset);
635 image->dri_format = driGLFormatToImageFormat(image->format);
636 image->has_depthstencil = iobj->mt->stencil_mt? true : false;
637 image->planar_format = iobj->planar_format;
638 if (image->dri_format == __DRI_IMAGE_FORMAT_NONE) {
639 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
640 free(image);
641 return NULL;
642 }
643
644 *error = __DRI_IMAGE_ERROR_SUCCESS;
645 return image;
646 }
647
648 static void
intel_destroy_image(__DRIimage * image)649 intel_destroy_image(__DRIimage *image)
650 {
651 brw_bo_unreference(image->bo);
652 free(image);
653 }
654
655 enum modifier_priority {
656 MODIFIER_PRIORITY_INVALID = 0,
657 MODIFIER_PRIORITY_LINEAR,
658 MODIFIER_PRIORITY_X,
659 MODIFIER_PRIORITY_Y,
660 MODIFIER_PRIORITY_Y_CCS,
661 };
662
663 const uint64_t priority_to_modifier[] = {
664 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
665 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
666 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
667 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
668 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
669 };
670
671 static uint64_t
select_best_modifier(struct gen_device_info * devinfo,int dri_format,const uint64_t * modifiers,const unsigned count)672 select_best_modifier(struct gen_device_info *devinfo,
673 int dri_format,
674 const uint64_t *modifiers,
675 const unsigned count)
676 {
677 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
678
679 for (int i = 0; i < count; i++) {
680 if (!modifier_is_supported(devinfo, NULL, dri_format, modifiers[i]))
681 continue;
682
683 switch (modifiers[i]) {
684 case I915_FORMAT_MOD_Y_TILED_CCS:
685 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
686 break;
687 case I915_FORMAT_MOD_Y_TILED:
688 prio = MAX2(prio, MODIFIER_PRIORITY_Y);
689 break;
690 case I915_FORMAT_MOD_X_TILED:
691 prio = MAX2(prio, MODIFIER_PRIORITY_X);
692 break;
693 case DRM_FORMAT_MOD_LINEAR:
694 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
695 break;
696 case DRM_FORMAT_MOD_INVALID:
697 default:
698 break;
699 }
700 }
701
702 return priority_to_modifier[prio];
703 }
704
705 static __DRIimage *
intel_create_image_common(__DRIscreen * dri_screen,int width,int height,int format,unsigned int use,const uint64_t * modifiers,unsigned count,void * loaderPrivate)706 intel_create_image_common(__DRIscreen *dri_screen,
707 int width, int height, int format,
708 unsigned int use,
709 const uint64_t *modifiers,
710 unsigned count,
711 void *loaderPrivate)
712 {
713 __DRIimage *image;
714 struct intel_screen *screen = dri_screen->driverPrivate;
715 uint64_t modifier = DRM_FORMAT_MOD_INVALID;
716 bool ok;
717
718 /* Callers of this may specify a modifier, or a dri usage, but not both. The
719 * newer modifier interface deprecates the older usage flags.
720 */
721 assert(!(use && count));
722
723 if (use & __DRI_IMAGE_USE_CURSOR) {
724 if (width != 64 || height != 64)
725 return NULL;
726 modifier = DRM_FORMAT_MOD_LINEAR;
727 }
728
729 if (use & __DRI_IMAGE_USE_LINEAR)
730 modifier = DRM_FORMAT_MOD_LINEAR;
731
732 if (modifier == DRM_FORMAT_MOD_INVALID) {
733 if (modifiers) {
734 /* User requested specific modifiers */
735 modifier = select_best_modifier(&screen->devinfo, format,
736 modifiers, count);
737 if (modifier == DRM_FORMAT_MOD_INVALID)
738 return NULL;
739 } else {
740 /* Historically, X-tiled was the default, and so lack of modifier means
741 * X-tiled.
742 */
743 modifier = I915_FORMAT_MOD_X_TILED;
744 }
745 }
746
747 image = intel_allocate_image(screen, format, loaderPrivate);
748 if (image == NULL)
749 return NULL;
750
751 const struct isl_drm_modifier_info *mod_info =
752 isl_drm_modifier_get_info(modifier);
753
754 struct isl_surf surf;
755 ok = isl_surf_init(&screen->isl_dev, &surf,
756 .dim = ISL_SURF_DIM_2D,
757 .format = brw_isl_format_for_mesa_format(image->format),
758 .width = width,
759 .height = height,
760 .depth = 1,
761 .levels = 1,
762 .array_len = 1,
763 .samples = 1,
764 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
765 ISL_SURF_USAGE_TEXTURE_BIT |
766 ISL_SURF_USAGE_STORAGE_BIT |
767 ((use & __DRI_IMAGE_USE_SCANOUT) ?
768 ISL_SURF_USAGE_DISPLAY_BIT : 0),
769 .tiling_flags = (1 << mod_info->tiling));
770 assert(ok);
771 if (!ok) {
772 free(image);
773 return NULL;
774 }
775
776 struct isl_surf aux_surf = {0,};
777 if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
778 ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL, 0);
779 if (!ok) {
780 free(image);
781 return NULL;
782 }
783 } else {
784 assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
785 aux_surf.size_B = 0;
786 }
787
788 /* We request that the bufmgr zero the buffer for us for two reasons:
789 *
790 * 1) If a buffer gets re-used from the pool, we don't want to leak random
791 * garbage from our process to some other.
792 *
793 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
794 * a valid state. A CCS value of 0 indicates that the given block is
795 * in the pass-through state which is what we want.
796 */
797 image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
798 surf.size_B + aux_surf.size_B,
799 BRW_MEMZONE_OTHER,
800 isl_tiling_to_i915_tiling(mod_info->tiling),
801 surf.row_pitch_B, BO_ALLOC_ZEROED);
802 if (image->bo == NULL) {
803 free(image);
804 return NULL;
805 }
806 image->width = width;
807 image->height = height;
808 image->pitch = surf.row_pitch_B;
809 image->modifier = modifier;
810
811 if (aux_surf.size_B) {
812 image->aux_offset = surf.size_B;
813 image->aux_pitch = aux_surf.row_pitch_B;
814 image->aux_size = aux_surf.size_B;
815 }
816
817 return image;
818 }
819
820 static __DRIimage *
intel_create_image(__DRIscreen * dri_screen,int width,int height,int format,unsigned int use,void * loaderPrivate)821 intel_create_image(__DRIscreen *dri_screen,
822 int width, int height, int format,
823 unsigned int use,
824 void *loaderPrivate)
825 {
826 return intel_create_image_common(dri_screen, width, height, format, use, NULL, 0,
827 loaderPrivate);
828 }
829
830 static void *
intel_map_image(__DRIcontext * context,__DRIimage * image,int x0,int y0,int width,int height,unsigned int flags,int * stride,void ** map_info)831 intel_map_image(__DRIcontext *context, __DRIimage *image,
832 int x0, int y0, int width, int height,
833 unsigned int flags, int *stride, void **map_info)
834 {
835 struct brw_context *brw = NULL;
836 struct brw_bo *bo = NULL;
837 void *raw_data = NULL;
838 GLuint pix_w = 1;
839 GLuint pix_h = 1;
840 GLint pix_bytes = 1;
841
842 if (!context || !image || !stride || !map_info || *map_info)
843 return NULL;
844
845 if (x0 < 0 || x0 >= image->width || width > image->width - x0)
846 return NULL;
847
848 if (y0 < 0 || y0 >= image->height || height > image->height - y0)
849 return NULL;
850
851 if (flags & MAP_INTERNAL_MASK)
852 return NULL;
853
854 brw = context->driverPrivate;
855 bo = image->bo;
856
857 assert(brw);
858 assert(bo);
859
860 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
861 raw_data = brw_bo_map(brw, bo, flags);
862 if (!raw_data)
863 return NULL;
864
865 _mesa_get_format_block_size(image->format, &pix_w, &pix_h);
866 pix_bytes = _mesa_get_format_bytes(image->format);
867
868 assert(pix_w);
869 assert(pix_h);
870 assert(pix_bytes > 0);
871
872 raw_data += (x0 / pix_w) * pix_bytes + (y0 / pix_h) * image->pitch;
873
874 brw_bo_reference(bo);
875
876 *stride = image->pitch;
877 *map_info = bo;
878
879 return raw_data;
880 }
881
882 static void
intel_unmap_image(UNUSED __DRIcontext * context,UNUSED __DRIimage * image,void * map_info)883 intel_unmap_image(UNUSED __DRIcontext *context, UNUSED __DRIimage *image,
884 void *map_info)
885 {
886 struct brw_bo *bo = map_info;
887
888 brw_bo_unmap(bo);
889 brw_bo_unreference(bo);
890 }
891
892 static __DRIimage *
intel_create_image_with_modifiers(__DRIscreen * dri_screen,int width,int height,int format,const uint64_t * modifiers,const unsigned count,void * loaderPrivate)893 intel_create_image_with_modifiers(__DRIscreen *dri_screen,
894 int width, int height, int format,
895 const uint64_t *modifiers,
896 const unsigned count,
897 void *loaderPrivate)
898 {
899 return intel_create_image_common(dri_screen, width, height, format, 0,
900 modifiers, count, loaderPrivate);
901 }
902
903 static GLboolean
intel_query_image(__DRIimage * image,int attrib,int * value)904 intel_query_image(__DRIimage *image, int attrib, int *value)
905 {
906 switch (attrib) {
907 case __DRI_IMAGE_ATTRIB_STRIDE:
908 *value = image->pitch;
909 return true;
910 case __DRI_IMAGE_ATTRIB_HANDLE: {
911 __DRIscreen *dri_screen = image->screen->driScrnPriv;
912 uint32_t handle;
913 if (brw_bo_export_gem_handle_for_device(image->bo,
914 dri_screen->fd,
915 &handle))
916 return false;
917 *value = handle;
918 return true;
919 }
920 case __DRI_IMAGE_ATTRIB_NAME:
921 return !brw_bo_flink(image->bo, (uint32_t *) value);
922 case __DRI_IMAGE_ATTRIB_FORMAT:
923 *value = image->dri_format;
924 return true;
925 case __DRI_IMAGE_ATTRIB_WIDTH:
926 *value = image->width;
927 return true;
928 case __DRI_IMAGE_ATTRIB_HEIGHT:
929 *value = image->height;
930 return true;
931 case __DRI_IMAGE_ATTRIB_COMPONENTS:
932 if (image->planar_format == NULL)
933 return false;
934 *value = image->planar_format->components;
935 return true;
936 case __DRI_IMAGE_ATTRIB_FD:
937 return !brw_bo_gem_export_to_prime(image->bo, value);
938 case __DRI_IMAGE_ATTRIB_FOURCC:
939 return intel_image_get_fourcc(image, value);
940 case __DRI_IMAGE_ATTRIB_NUM_PLANES:
941 if (isl_drm_modifier_has_aux(image->modifier)) {
942 assert(!image->planar_format || image->planar_format->nplanes == 1);
943 *value = 2;
944 } else if (image->planar_format) {
945 *value = image->planar_format->nplanes;
946 } else {
947 *value = 1;
948 }
949 return true;
950 case __DRI_IMAGE_ATTRIB_OFFSET:
951 *value = image->offset;
952 return true;
953 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER:
954 *value = (image->modifier & 0xffffffff);
955 return true;
956 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER:
957 *value = ((image->modifier >> 32) & 0xffffffff);
958 return true;
959
960 default:
961 return false;
962 }
963 }
964
965 static GLboolean
intel_query_format_modifier_attribs(__DRIscreen * dri_screen,uint32_t fourcc,uint64_t modifier,int attrib,uint64_t * value)966 intel_query_format_modifier_attribs(__DRIscreen *dri_screen,
967 uint32_t fourcc, uint64_t modifier,
968 int attrib, uint64_t *value)
969 {
970 struct intel_screen *screen = dri_screen->driverPrivate;
971 const struct intel_image_format *f = intel_image_format_lookup(fourcc);
972
973 if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
974 return false;
975
976 switch (attrib) {
977 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT:
978 *value = isl_drm_modifier_has_aux(modifier) ? 2 : f->nplanes;
979 return true;
980
981 default:
982 return false;
983 }
984 }
985
986 static __DRIimage *
intel_dup_image(__DRIimage * orig_image,void * loaderPrivate)987 intel_dup_image(__DRIimage *orig_image, void *loaderPrivate)
988 {
989 __DRIimage *image;
990
991 image = calloc(1, sizeof *image);
992 if (image == NULL)
993 return NULL;
994
995 brw_bo_reference(orig_image->bo);
996 image->screen = orig_image->screen;
997 image->bo = orig_image->bo;
998 image->internal_format = orig_image->internal_format;
999 image->planar_format = orig_image->planar_format;
1000 image->dri_format = orig_image->dri_format;
1001 image->format = orig_image->format;
1002 image->modifier = orig_image->modifier;
1003 image->offset = orig_image->offset;
1004 image->width = orig_image->width;
1005 image->height = orig_image->height;
1006 image->pitch = orig_image->pitch;
1007 image->tile_x = orig_image->tile_x;
1008 image->tile_y = orig_image->tile_y;
1009 image->has_depthstencil = orig_image->has_depthstencil;
1010 image->data = loaderPrivate;
1011 image->aux_offset = orig_image->aux_offset;
1012 image->aux_pitch = orig_image->aux_pitch;
1013
1014 memcpy(image->strides, orig_image->strides, sizeof(image->strides));
1015 memcpy(image->offsets, orig_image->offsets, sizeof(image->offsets));
1016
1017 return image;
1018 }
1019
1020 static GLboolean
intel_validate_usage(__DRIimage * image,unsigned int use)1021 intel_validate_usage(__DRIimage *image, unsigned int use)
1022 {
1023 if (use & __DRI_IMAGE_USE_CURSOR) {
1024 if (image->width != 64 || image->height != 64)
1025 return GL_FALSE;
1026 }
1027
1028 return GL_TRUE;
1029 }
1030
1031 static __DRIimage *
intel_create_image_from_names(__DRIscreen * dri_screen,int width,int height,int fourcc,int * names,int num_names,int * strides,int * offsets,void * loaderPrivate)1032 intel_create_image_from_names(__DRIscreen *dri_screen,
1033 int width, int height, int fourcc,
1034 int *names, int num_names,
1035 int *strides, int *offsets,
1036 void *loaderPrivate)
1037 {
1038 const struct intel_image_format *f = NULL;
1039 __DRIimage *image;
1040 int i, index;
1041
1042 if (dri_screen == NULL || names == NULL || num_names != 1)
1043 return NULL;
1044
1045 f = intel_image_format_lookup(fourcc);
1046 if (f == NULL)
1047 return NULL;
1048
1049 image = intel_create_image_from_name(dri_screen, width, height,
1050 __DRI_IMAGE_FORMAT_NONE,
1051 names[0], strides[0],
1052 loaderPrivate);
1053
1054 if (image == NULL)
1055 return NULL;
1056
1057 image->planar_format = f;
1058 for (i = 0; i < f->nplanes; i++) {
1059 index = f->planes[i].buffer_index;
1060 image->offsets[index] = offsets[index];
1061 image->strides[index] = strides[index];
1062 }
1063
1064 return image;
1065 }
1066
1067 static __DRIimage *
intel_create_image_from_fds_common(__DRIscreen * dri_screen,int width,int height,int fourcc,uint64_t modifier,int * fds,int num_fds,int * strides,int * offsets,void * loaderPrivate)1068 intel_create_image_from_fds_common(__DRIscreen *dri_screen,
1069 int width, int height, int fourcc,
1070 uint64_t modifier, int *fds, int num_fds,
1071 int *strides, int *offsets,
1072 void *loaderPrivate)
1073 {
1074 struct intel_screen *screen = dri_screen->driverPrivate;
1075 const struct intel_image_format *f;
1076 __DRIimage *image;
1077 int i, index;
1078 bool ok;
1079
1080 if (fds == NULL || num_fds < 1)
1081 return NULL;
1082
1083 f = intel_image_format_lookup(fourcc);
1084 if (f == NULL)
1085 return NULL;
1086
1087 if (modifier != DRM_FORMAT_MOD_INVALID &&
1088 !modifier_is_supported(&screen->devinfo, f, 0, modifier))
1089 return NULL;
1090
1091 if (f->nplanes == 1)
1092 image = intel_allocate_image(screen, f->planes[0].dri_format,
1093 loaderPrivate);
1094 else
1095 image = intel_allocate_image(screen, __DRI_IMAGE_FORMAT_NONE,
1096 loaderPrivate);
1097
1098 if (image == NULL)
1099 return NULL;
1100
1101 image->width = width;
1102 image->height = height;
1103 image->pitch = strides[0];
1104
1105 image->planar_format = f;
1106
1107 if (modifier != DRM_FORMAT_MOD_INVALID) {
1108 const struct isl_drm_modifier_info *mod_info =
1109 isl_drm_modifier_get_info(modifier);
1110 uint32_t tiling = isl_tiling_to_i915_tiling(mod_info->tiling);
1111 image->bo = brw_bo_gem_create_from_prime_tiled(screen->bufmgr, fds[0],
1112 tiling, strides[0]);
1113 } else {
1114 image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0]);
1115 }
1116
1117 if (image->bo == NULL) {
1118 free(image);
1119 return NULL;
1120 }
1121
1122 /* We only support all planes from the same bo.
1123 * brw_bo_gem_create_from_prime() should return the same pointer for all
1124 * fds received here */
1125 for (i = 1; i < num_fds; i++) {
1126 struct brw_bo *aux = brw_bo_gem_create_from_prime(screen->bufmgr, fds[i]);
1127 brw_bo_unreference(aux);
1128 if (aux != image->bo) {
1129 brw_bo_unreference(image->bo);
1130 free(image);
1131 return NULL;
1132 }
1133 }
1134
1135 if (modifier != DRM_FORMAT_MOD_INVALID)
1136 image->modifier = modifier;
1137 else
1138 image->modifier = tiling_to_modifier(image->bo->tiling_mode);
1139
1140 const struct isl_drm_modifier_info *mod_info =
1141 isl_drm_modifier_get_info(image->modifier);
1142
1143 int size = 0;
1144 struct isl_surf surf;
1145 for (i = 0; i < f->nplanes; i++) {
1146 index = f->planes[i].buffer_index;
1147 image->offsets[index] = offsets[index];
1148 image->strides[index] = strides[index];
1149
1150 mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
1151 /* The images we will create are actually based on the RGBA non-sRGB
1152 * version of the format.
1153 */
1154 format = _mesa_format_fallback_rgbx_to_rgba(format);
1155 format = _mesa_get_srgb_format_linear(format);
1156
1157 ok = isl_surf_init(&screen->isl_dev, &surf,
1158 .dim = ISL_SURF_DIM_2D,
1159 .format = brw_isl_format_for_mesa_format(format),
1160 .width = image->width >> f->planes[i].width_shift,
1161 .height = image->height >> f->planes[i].height_shift,
1162 .depth = 1,
1163 .levels = 1,
1164 .array_len = 1,
1165 .samples = 1,
1166 .row_pitch_B = strides[index],
1167 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
1168 ISL_SURF_USAGE_TEXTURE_BIT |
1169 ISL_SURF_USAGE_STORAGE_BIT,
1170 .tiling_flags = (1 << mod_info->tiling));
1171 if (!ok) {
1172 brw_bo_unreference(image->bo);
1173 free(image);
1174 return NULL;
1175 }
1176
1177 const int end = offsets[index] + surf.size_B;
1178 if (size < end)
1179 size = end;
1180 }
1181
1182 if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
1183 /* Even though we initialize surf in the loop above, we know that
1184 * anything with CCS_E will have exactly one plane so surf is properly
1185 * initialized when we get here.
1186 */
1187 assert(f->nplanes == 1);
1188
1189 image->aux_offset = offsets[1];
1190 image->aux_pitch = strides[1];
1191
1192 /* Scanout hardware requires that the CCS be placed after the main
1193 * surface in memory. We consider any CCS that is placed any earlier in
1194 * memory to be invalid and reject it.
1195 *
1196 * At some point in the future, this restriction may be relaxed if the
1197 * hardware becomes less strict but we may need a new modifier for that.
1198 */
1199 assert(size > 0);
1200 if (image->aux_offset < size) {
1201 brw_bo_unreference(image->bo);
1202 free(image);
1203 return NULL;
1204 }
1205
1206 struct isl_surf aux_surf = {0,};
1207 ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL,
1208 image->aux_pitch);
1209 if (!ok) {
1210 brw_bo_unreference(image->bo);
1211 free(image);
1212 return NULL;
1213 }
1214
1215 image->aux_size = aux_surf.size_B;
1216
1217 const int end = image->aux_offset + aux_surf.size_B;
1218 if (size < end)
1219 size = end;
1220 } else {
1221 assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
1222 }
1223
1224 /* Check that the requested image actually fits within the BO. 'size'
1225 * is already relative to the offsets, so we don't need to add that. */
1226 if (image->bo->size == 0) {
1227 image->bo->size = size;
1228 } else if (size > image->bo->size) {
1229 brw_bo_unreference(image->bo);
1230 free(image);
1231 return NULL;
1232 }
1233
1234 if (f->nplanes == 1) {
1235 image->offset = image->offsets[0];
1236 intel_image_warn_if_unaligned(image, __func__);
1237 }
1238
1239 return image;
1240 }
1241
1242 static __DRIimage *
intel_create_image_from_fds(__DRIscreen * dri_screen,int width,int height,int fourcc,int * fds,int num_fds,int * strides,int * offsets,void * loaderPrivate)1243 intel_create_image_from_fds(__DRIscreen *dri_screen,
1244 int width, int height, int fourcc,
1245 int *fds, int num_fds, int *strides, int *offsets,
1246 void *loaderPrivate)
1247 {
1248 return intel_create_image_from_fds_common(dri_screen, width, height, fourcc,
1249 DRM_FORMAT_MOD_INVALID,
1250 fds, num_fds, strides, offsets,
1251 loaderPrivate);
1252 }
1253
1254 static __DRIimage *
intel_create_image_from_dma_bufs2(__DRIscreen * dri_screen,int width,int height,int fourcc,uint64_t modifier,int * fds,int num_fds,int * strides,int * offsets,enum __DRIYUVColorSpace yuv_color_space,enum __DRISampleRange sample_range,enum __DRIChromaSiting horizontal_siting,enum __DRIChromaSiting vertical_siting,unsigned * error,void * loaderPrivate)1255 intel_create_image_from_dma_bufs2(__DRIscreen *dri_screen,
1256 int width, int height,
1257 int fourcc, uint64_t modifier,
1258 int *fds, int num_fds,
1259 int *strides, int *offsets,
1260 enum __DRIYUVColorSpace yuv_color_space,
1261 enum __DRISampleRange sample_range,
1262 enum __DRIChromaSiting horizontal_siting,
1263 enum __DRIChromaSiting vertical_siting,
1264 unsigned *error,
1265 void *loaderPrivate)
1266 {
1267 __DRIimage *image;
1268 const struct intel_image_format *f = intel_image_format_lookup(fourcc);
1269
1270 if (!f) {
1271 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
1272 return NULL;
1273 }
1274
1275 image = intel_create_image_from_fds_common(dri_screen, width, height,
1276 fourcc, modifier,
1277 fds, num_fds, strides, offsets,
1278 loaderPrivate);
1279
1280 /*
1281 * Invalid parameters and any inconsistencies between are assumed to be
1282 * checked by the caller. Therefore besides unsupported formats one can fail
1283 * only in allocation.
1284 */
1285 if (!image) {
1286 *error = __DRI_IMAGE_ERROR_BAD_ALLOC;
1287 return NULL;
1288 }
1289
1290 image->yuv_color_space = yuv_color_space;
1291 image->sample_range = sample_range;
1292 image->horizontal_siting = horizontal_siting;
1293 image->vertical_siting = vertical_siting;
1294 image->imported_dmabuf = true;
1295
1296 *error = __DRI_IMAGE_ERROR_SUCCESS;
1297 return image;
1298 }
1299
1300 static __DRIimage *
intel_create_image_from_dma_bufs(__DRIscreen * dri_screen,int width,int height,int fourcc,int * fds,int num_fds,int * strides,int * offsets,enum __DRIYUVColorSpace yuv_color_space,enum __DRISampleRange sample_range,enum __DRIChromaSiting horizontal_siting,enum __DRIChromaSiting vertical_siting,unsigned * error,void * loaderPrivate)1301 intel_create_image_from_dma_bufs(__DRIscreen *dri_screen,
1302 int width, int height, int fourcc,
1303 int *fds, int num_fds,
1304 int *strides, int *offsets,
1305 enum __DRIYUVColorSpace yuv_color_space,
1306 enum __DRISampleRange sample_range,
1307 enum __DRIChromaSiting horizontal_siting,
1308 enum __DRIChromaSiting vertical_siting,
1309 unsigned *error,
1310 void *loaderPrivate)
1311 {
1312 return intel_create_image_from_dma_bufs2(dri_screen, width, height,
1313 fourcc, DRM_FORMAT_MOD_INVALID,
1314 fds, num_fds, strides, offsets,
1315 yuv_color_space,
1316 sample_range,
1317 horizontal_siting,
1318 vertical_siting,
1319 error,
1320 loaderPrivate);
1321 }
1322
1323 static bool
intel_image_format_is_supported(const struct gen_device_info * devinfo,const struct intel_image_format * fmt)1324 intel_image_format_is_supported(const struct gen_device_info *devinfo,
1325 const struct intel_image_format *fmt)
1326 {
1327 /* Currently, all formats with an intel_image_format are available on all
1328 * platforms so there's really nothing to check there.
1329 */
1330
1331 #ifndef NDEBUG
1332 if (fmt->nplanes == 1) {
1333 mesa_format format = driImageFormatToGLFormat(fmt->planes[0].dri_format);
1334 /* The images we will create are actually based on the RGBA non-sRGB
1335 * version of the format.
1336 */
1337 format = _mesa_format_fallback_rgbx_to_rgba(format);
1338 format = _mesa_get_srgb_format_linear(format);
1339 enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
1340 assert(isl_format_supports_rendering(devinfo, isl_format));
1341 }
1342 #endif
1343
1344 return true;
1345 }
1346
1347 static GLboolean
intel_query_dma_buf_formats(__DRIscreen * _screen,int max,int * formats,int * count)1348 intel_query_dma_buf_formats(__DRIscreen *_screen, int max,
1349 int *formats, int *count)
1350 {
1351 struct intel_screen *screen = _screen->driverPrivate;
1352 int num_formats = 0, i;
1353
1354 for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
1355 /* These formats are valid DRI formats but do not exist in drm_fourcc.h
1356 * in the Linux kernel. We don't want to accidentally advertise them
1357 * them through the EGL layer.
1358 */
1359 if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 ||
1360 intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888 ||
1361 intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SXRGB8888)
1362 continue;
1363
1364 if (!intel_image_format_is_supported(&screen->devinfo,
1365 &intel_image_formats[i]))
1366 continue;
1367
1368 num_formats++;
1369 if (max == 0)
1370 continue;
1371
1372 formats[num_formats - 1] = intel_image_formats[i].fourcc;
1373 if (num_formats >= max)
1374 break;
1375 }
1376
1377 *count = num_formats;
1378 return true;
1379 }
1380
1381 static GLboolean
intel_query_dma_buf_modifiers(__DRIscreen * _screen,int fourcc,int max,uint64_t * modifiers,unsigned int * external_only,int * count)1382 intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max,
1383 uint64_t *modifiers,
1384 unsigned int *external_only,
1385 int *count)
1386 {
1387 struct intel_screen *screen = _screen->driverPrivate;
1388 const struct intel_image_format *f;
1389 int num_mods = 0, i;
1390
1391 f = intel_image_format_lookup(fourcc);
1392 if (f == NULL)
1393 return false;
1394
1395 if (!intel_image_format_is_supported(&screen->devinfo, f))
1396 return false;
1397
1398 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
1399 uint64_t modifier = supported_modifiers[i].modifier;
1400 if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
1401 continue;
1402
1403 num_mods++;
1404 if (max == 0)
1405 continue;
1406
1407 modifiers[num_mods - 1] = modifier;
1408 if (num_mods >= max)
1409 break;
1410 }
1411
1412 if (external_only != NULL) {
1413 for (i = 0; i < num_mods && i < max; i++) {
1414 if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
1415 f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
1416 f->components == __DRI_IMAGE_COMPONENTS_AYUV ||
1417 f->components == __DRI_IMAGE_COMPONENTS_XYUV ||
1418 f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV ||
1419 f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) {
1420 external_only[i] = GL_TRUE;
1421 }
1422 else {
1423 external_only[i] = GL_FALSE;
1424 }
1425 }
1426 }
1427
1428 *count = num_mods;
1429 return true;
1430 }
1431
1432 static __DRIimage *
intel_from_planar(__DRIimage * parent,int plane,void * loaderPrivate)1433 intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
1434 {
1435 int width, height, offset, stride, size, dri_format;
1436 __DRIimage *image;
1437
1438 if (parent == NULL)
1439 return NULL;
1440
1441 width = parent->width;
1442 height = parent->height;
1443
1444 const struct intel_image_format *f = parent->planar_format;
1445
1446 if (f && plane < f->nplanes) {
1447 /* Use the planar format definition. */
1448 width >>= f->planes[plane].width_shift;
1449 height >>= f->planes[plane].height_shift;
1450 dri_format = f->planes[plane].dri_format;
1451 int index = f->planes[plane].buffer_index;
1452 offset = parent->offsets[index];
1453 stride = parent->strides[index];
1454 size = height * stride;
1455 } else if (plane == 0) {
1456 /* The only plane of a non-planar image: copy the parent definition
1457 * directly. */
1458 dri_format = parent->dri_format;
1459 offset = parent->offset;
1460 stride = parent->pitch;
1461 size = height * stride;
1462 } else if (plane == 1 && parent->modifier != DRM_FORMAT_MOD_INVALID &&
1463 isl_drm_modifier_has_aux(parent->modifier)) {
1464 /* Auxiliary plane */
1465 dri_format = parent->dri_format;
1466 offset = parent->aux_offset;
1467 stride = parent->aux_pitch;
1468 size = parent->aux_size;
1469 } else {
1470 return NULL;
1471 }
1472
1473 if (offset + size > parent->bo->size) {
1474 _mesa_warning(NULL, "intel_from_planar: subimage out of bounds");
1475 return NULL;
1476 }
1477
1478 image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
1479 if (image == NULL)
1480 return NULL;
1481
1482 image->bo = parent->bo;
1483 brw_bo_reference(parent->bo);
1484 image->modifier = parent->modifier;
1485
1486 image->width = width;
1487 image->height = height;
1488 image->pitch = stride;
1489 image->offset = offset;
1490
1491 intel_image_warn_if_unaligned(image, __func__);
1492
1493 return image;
1494 }
1495
1496 static const __DRIimageExtension intelImageExtension = {
1497 .base = { __DRI_IMAGE, 16 },
1498
1499 .createImageFromName = intel_create_image_from_name,
1500 .createImageFromRenderbuffer = intel_create_image_from_renderbuffer,
1501 .destroyImage = intel_destroy_image,
1502 .createImage = intel_create_image,
1503 .queryImage = intel_query_image,
1504 .dupImage = intel_dup_image,
1505 .validateUsage = intel_validate_usage,
1506 .createImageFromNames = intel_create_image_from_names,
1507 .fromPlanar = intel_from_planar,
1508 .createImageFromTexture = intel_create_image_from_texture,
1509 .createImageFromFds = intel_create_image_from_fds,
1510 .createImageFromDmaBufs = intel_create_image_from_dma_bufs,
1511 .blitImage = NULL,
1512 .getCapabilities = NULL,
1513 .mapImage = intel_map_image,
1514 .unmapImage = intel_unmap_image,
1515 .createImageWithModifiers = intel_create_image_with_modifiers,
1516 .createImageFromDmaBufs2 = intel_create_image_from_dma_bufs2,
1517 .queryDmaBufFormats = intel_query_dma_buf_formats,
1518 .queryDmaBufModifiers = intel_query_dma_buf_modifiers,
1519 .queryDmaBufFormatModifierAttribs = intel_query_format_modifier_attribs,
1520 };
1521
1522 static int
brw_query_renderer_integer(__DRIscreen * dri_screen,int param,unsigned int * value)1523 brw_query_renderer_integer(__DRIscreen *dri_screen,
1524 int param, unsigned int *value)
1525 {
1526 const struct intel_screen *const screen =
1527 (struct intel_screen *) dri_screen->driverPrivate;
1528
1529 switch (param) {
1530 case __DRI2_RENDERER_VENDOR_ID:
1531 value[0] = 0x8086;
1532 return 0;
1533 case __DRI2_RENDERER_DEVICE_ID:
1534 value[0] = screen->deviceID;
1535 return 0;
1536 case __DRI2_RENDERER_ACCELERATED:
1537 value[0] = 1;
1538 return 0;
1539 case __DRI2_RENDERER_VIDEO_MEMORY: {
1540 /* Once a batch uses more than 75% of the maximum mappable size, we
1541 * assume that there's some fragmentation, and we start doing extra
1542 * flushing, etc. That's the big cliff apps will care about.
1543 */
1544 const unsigned gpu_mappable_megabytes =
1545 screen->aperture_threshold / (1024 * 1024);
1546
1547 const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
1548 const long system_page_size = sysconf(_SC_PAGE_SIZE);
1549
1550 if (system_memory_pages <= 0 || system_page_size <= 0)
1551 return -1;
1552
1553 const uint64_t system_memory_bytes = (uint64_t) system_memory_pages
1554 * (uint64_t) system_page_size;
1555
1556 const unsigned system_memory_megabytes =
1557 (unsigned) (system_memory_bytes / (1024 * 1024));
1558
1559 value[0] = MIN2(system_memory_megabytes, gpu_mappable_megabytes);
1560 return 0;
1561 }
1562 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE:
1563 value[0] = 1;
1564 return 0;
1565 case __DRI2_RENDERER_HAS_TEXTURE_3D:
1566 value[0] = 1;
1567 return 0;
1568 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
1569 value[0] = 0;
1570 if (brw_hw_context_set_priority(screen->bufmgr,
1571 0, GEN_CONTEXT_HIGH_PRIORITY) == 0)
1572 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH;
1573 if (brw_hw_context_set_priority(screen->bufmgr,
1574 0, GEN_CONTEXT_LOW_PRIORITY) == 0)
1575 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW;
1576 /* reset to default last, just in case */
1577 if (brw_hw_context_set_priority(screen->bufmgr,
1578 0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0)
1579 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM;
1580 return 0;
1581 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB:
1582 value[0] = 1;
1583 return 0;
1584 default:
1585 return driQueryRendererIntegerCommon(dri_screen, param, value);
1586 }
1587
1588 return -1;
1589 }
1590
1591 static int
brw_query_renderer_string(__DRIscreen * dri_screen,int param,const char ** value)1592 brw_query_renderer_string(__DRIscreen *dri_screen,
1593 int param, const char **value)
1594 {
1595 const struct intel_screen *screen =
1596 (struct intel_screen *) dri_screen->driverPrivate;
1597
1598 switch (param) {
1599 case __DRI2_RENDERER_VENDOR_ID:
1600 value[0] = brw_vendor_string;
1601 return 0;
1602 case __DRI2_RENDERER_DEVICE_ID:
1603 value[0] = brw_get_renderer_string(screen);
1604 return 0;
1605 default:
1606 break;
1607 }
1608
1609 return -1;
1610 }
1611
1612 static void
brw_set_cache_funcs(__DRIscreen * dri_screen,__DRIblobCacheSet set,__DRIblobCacheGet get)1613 brw_set_cache_funcs(__DRIscreen *dri_screen,
1614 __DRIblobCacheSet set, __DRIblobCacheGet get)
1615 {
1616 const struct intel_screen *const screen =
1617 (struct intel_screen *) dri_screen->driverPrivate;
1618
1619 if (!screen->disk_cache)
1620 return;
1621
1622 disk_cache_set_callbacks(screen->disk_cache, set, get);
1623 }
1624
1625 static const __DRI2rendererQueryExtension intelRendererQueryExtension = {
1626 .base = { __DRI2_RENDERER_QUERY, 1 },
1627
1628 .queryInteger = brw_query_renderer_integer,
1629 .queryString = brw_query_renderer_string
1630 };
1631
1632 static const __DRIrobustnessExtension dri2Robustness = {
1633 .base = { __DRI2_ROBUSTNESS, 1 }
1634 };
1635
1636 static const __DRI2blobExtension intelBlobExtension = {
1637 .base = { __DRI2_BLOB, 1 },
1638 .set_cache_funcs = brw_set_cache_funcs
1639 };
1640
1641 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension = {
1642 .base = { __DRI_MUTABLE_RENDER_BUFFER_DRIVER, 1 },
1643 };
1644
1645 static const __DRIextension *screenExtensions[] = {
1646 &intelTexBufferExtension.base,
1647 &intelFenceExtension.base,
1648 &intelFlushExtension.base,
1649 &intelImageExtension.base,
1650 &intelRendererQueryExtension.base,
1651 &intelMutableRenderBufferExtension.base,
1652 &dri2ConfigQueryExtension.base,
1653 &dri2NoErrorExtension.base,
1654 &intelBlobExtension.base,
1655 NULL
1656 };
1657
1658 static const __DRIextension *intelRobustScreenExtensions[] = {
1659 &intelTexBufferExtension.base,
1660 &intelFenceExtension.base,
1661 &intelFlushExtension.base,
1662 &intelImageExtension.base,
1663 &intelRendererQueryExtension.base,
1664 &intelMutableRenderBufferExtension.base,
1665 &dri2ConfigQueryExtension.base,
1666 &dri2Robustness.base,
1667 &dri2NoErrorExtension.base,
1668 &intelBlobExtension.base,
1669 NULL
1670 };
1671
1672 static int
intel_get_param(struct intel_screen * screen,int param,int * value)1673 intel_get_param(struct intel_screen *screen, int param, int *value)
1674 {
1675 int ret = 0;
1676 struct drm_i915_getparam gp;
1677
1678 memset(&gp, 0, sizeof(gp));
1679 gp.param = param;
1680 gp.value = value;
1681
1682 if (drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) {
1683 ret = -errno;
1684 if (ret != -EINVAL)
1685 _mesa_warning(NULL, "drm_i915_getparam: %d", ret);
1686 }
1687
1688 return ret;
1689 }
1690
1691 static bool
intel_get_boolean(struct intel_screen * screen,int param)1692 intel_get_boolean(struct intel_screen *screen, int param)
1693 {
1694 int value = 0;
1695 return (intel_get_param(screen, param, &value) == 0) && value;
1696 }
1697
1698 static int
intel_get_integer(struct intel_screen * screen,int param)1699 intel_get_integer(struct intel_screen *screen, int param)
1700 {
1701 int value = -1;
1702
1703 if (intel_get_param(screen, param, &value) == 0)
1704 return value;
1705
1706 return -1;
1707 }
1708
1709 static void
intelDestroyScreen(__DRIscreen * sPriv)1710 intelDestroyScreen(__DRIscreen * sPriv)
1711 {
1712 struct intel_screen *screen = sPriv->driverPrivate;
1713
1714 brw_bufmgr_unref(screen->bufmgr);
1715 driDestroyOptionInfo(&screen->optionCache);
1716
1717 disk_cache_destroy(screen->disk_cache);
1718
1719 ralloc_free(screen);
1720 sPriv->driverPrivate = NULL;
1721 }
1722
1723
1724 /**
1725 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1726 *
1727 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1728 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1729 * this does not allocate GPU memory.
1730 */
1731 static GLboolean
intelCreateBuffer(__DRIscreen * dri_screen,__DRIdrawable * driDrawPriv,const struct gl_config * mesaVis,GLboolean isPixmap)1732 intelCreateBuffer(__DRIscreen *dri_screen,
1733 __DRIdrawable * driDrawPriv,
1734 const struct gl_config * mesaVis, GLboolean isPixmap)
1735 {
1736 struct intel_renderbuffer *rb;
1737 struct intel_screen *screen = (struct intel_screen *)
1738 dri_screen->driverPrivate;
1739 mesa_format rgbFormat;
1740 unsigned num_samples =
1741 intel_quantize_num_samples(screen, mesaVis->samples);
1742
1743 if (isPixmap)
1744 return false;
1745
1746 struct gl_framebuffer *fb = CALLOC_STRUCT(gl_framebuffer);
1747 if (!fb)
1748 return false;
1749
1750 _mesa_initialize_window_framebuffer(fb, mesaVis);
1751
1752 if (screen->winsys_msaa_samples_override != -1) {
1753 num_samples = screen->winsys_msaa_samples_override;
1754 fb->Visual.samples = num_samples;
1755 }
1756
1757 if (mesaVis->redBits == 16 && mesaVis->alphaBits > 0 && mesaVis->floatMode) {
1758 rgbFormat = MESA_FORMAT_RGBA_FLOAT16;
1759 } else if (mesaVis->redBits == 16 && mesaVis->floatMode) {
1760 rgbFormat = MESA_FORMAT_RGBX_FLOAT16;
1761 } else if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) {
1762 rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1763 : MESA_FORMAT_R10G10B10A2_UNORM;
1764 } else if (mesaVis->redBits == 10) {
1765 rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1766 : MESA_FORMAT_R10G10B10X2_UNORM;
1767 } else if (mesaVis->redBits == 5) {
1768 rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1769 : MESA_FORMAT_B5G6R5_UNORM;
1770 } else if (mesaVis->alphaBits == 0) {
1771 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_SRGB
1772 : MESA_FORMAT_B8G8R8X8_SRGB;
1773 fb->Visual.sRGBCapable = true;
1774 } else if (mesaVis->sRGBCapable) {
1775 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1776 : MESA_FORMAT_B8G8R8A8_SRGB;
1777 fb->Visual.sRGBCapable = true;
1778 } else {
1779 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1780 : MESA_FORMAT_B8G8R8A8_SRGB;
1781 fb->Visual.sRGBCapable = true;
1782 }
1783
1784 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1785 bool srgb_cap_set = mesaVis->redBits >= 8 && mesaVis->sRGBCapable;
1786
1787 /* setup the hardware-based renderbuffers */
1788 rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples);
1789 _mesa_attach_and_own_rb(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
1790 rb->need_srgb = srgb_cap_set;
1791
1792 if (mesaVis->doubleBufferMode) {
1793 rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples);
1794 _mesa_attach_and_own_rb(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
1795 rb->need_srgb = srgb_cap_set;
1796 }
1797
1798 /*
1799 * Assert here that the gl_config has an expected depth/stencil bit
1800 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1801 * which constructs the advertised configs.)
1802 */
1803 if (mesaVis->depthBits == 24) {
1804 assert(mesaVis->stencilBits == 8);
1805
1806 if (screen->devinfo.has_hiz_and_separate_stencil) {
1807 rb = intel_create_private_renderbuffer(screen,
1808 MESA_FORMAT_Z24_UNORM_X8_UINT,
1809 num_samples);
1810 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1811 rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_S_UINT8,
1812 num_samples);
1813 _mesa_attach_and_own_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
1814 } else {
1815 /*
1816 * Use combined depth/stencil. Note that the renderbuffer is
1817 * attached to two attachment points.
1818 */
1819 rb = intel_create_private_renderbuffer(screen,
1820 MESA_FORMAT_Z24_UNORM_S8_UINT,
1821 num_samples);
1822 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1823 _mesa_attach_and_reference_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
1824 }
1825 }
1826 else if (mesaVis->depthBits == 16) {
1827 assert(mesaVis->stencilBits == 0);
1828 rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_Z_UNORM16,
1829 num_samples);
1830 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1831 }
1832 else {
1833 assert(mesaVis->depthBits == 0);
1834 assert(mesaVis->stencilBits == 0);
1835 }
1836
1837 /* now add any/all software-based renderbuffers we may need */
1838 _swrast_add_soft_renderbuffers(fb,
1839 false, /* never sw color */
1840 false, /* never sw depth */
1841 false, /* never sw stencil */
1842 mesaVis->accumRedBits > 0,
1843 false, /* never sw alpha */
1844 false /* never sw aux */ );
1845 driDrawPriv->driverPrivate = fb;
1846
1847 return true;
1848 }
1849
1850 static void
intelDestroyBuffer(__DRIdrawable * driDrawPriv)1851 intelDestroyBuffer(__DRIdrawable * driDrawPriv)
1852 {
1853 struct gl_framebuffer *fb = driDrawPriv->driverPrivate;
1854
1855 _mesa_reference_framebuffer(&fb, NULL);
1856 }
1857
1858 static void
intel_cs_timestamp_frequency(struct intel_screen * screen)1859 intel_cs_timestamp_frequency(struct intel_screen *screen)
1860 {
1861 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1862 * gen10, PCI-id is enough to figure it out.
1863 */
1864 assert(screen->devinfo.gen >= 10);
1865
1866 int ret, freq;
1867
1868 ret = intel_get_param(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
1869 &freq);
1870 if (ret < 0) {
1871 _mesa_warning(NULL,
1872 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1873 return;
1874 }
1875
1876 screen->devinfo.timestamp_frequency = freq;
1877 }
1878
1879 static void
intel_detect_sseu(struct intel_screen * screen)1880 intel_detect_sseu(struct intel_screen *screen)
1881 {
1882 assert(screen->devinfo.gen >= 8);
1883 int ret;
1884
1885 screen->subslice_total = -1;
1886 screen->eu_total = -1;
1887
1888 ret = intel_get_param(screen, I915_PARAM_SUBSLICE_TOTAL,
1889 &screen->subslice_total);
1890 if (ret < 0 && ret != -EINVAL)
1891 goto err_out;
1892
1893 ret = intel_get_param(screen,
1894 I915_PARAM_EU_TOTAL, &screen->eu_total);
1895 if (ret < 0 && ret != -EINVAL)
1896 goto err_out;
1897
1898 /* Without this information, we cannot get the right Braswell brandstrings,
1899 * and we have to use conservative numbers for GPGPU on many platforms, but
1900 * otherwise, things will just work.
1901 */
1902 if (screen->subslice_total < 1 || screen->eu_total < 1)
1903 _mesa_warning(NULL,
1904 "Kernel 4.1 required to properly query GPU properties.\n");
1905
1906 return;
1907
1908 err_out:
1909 screen->subslice_total = -1;
1910 screen->eu_total = -1;
1911 _mesa_warning(NULL, "Failed to query GPU properties (%s).\n", strerror(-ret));
1912 }
1913
1914 static bool
intel_init_bufmgr(struct intel_screen * screen)1915 intel_init_bufmgr(struct intel_screen *screen)
1916 {
1917 __DRIscreen *dri_screen = screen->driScrnPriv;
1918
1919 if (getenv("INTEL_NO_HW") != NULL)
1920 screen->no_hw = true;
1921
1922 bool bo_reuse = false;
1923 int bo_reuse_mode = driQueryOptioni(&screen->optionCache, "bo_reuse");
1924 switch (bo_reuse_mode) {
1925 case DRI_CONF_BO_REUSE_DISABLED:
1926 break;
1927 case DRI_CONF_BO_REUSE_ALL:
1928 bo_reuse = true;
1929 break;
1930 }
1931
1932 screen->bufmgr = brw_bufmgr_get_for_fd(&screen->devinfo, dri_screen->fd, bo_reuse);
1933 if (screen->bufmgr == NULL) {
1934 fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
1935 __func__, __LINE__);
1936 return false;
1937 }
1938 screen->fd = brw_bufmgr_get_fd(screen->bufmgr);
1939
1940 if (!intel_get_boolean(screen, I915_PARAM_HAS_EXEC_NO_RELOC)) {
1941 fprintf(stderr, "[%s: %u] Kernel 3.9 required.\n", __func__, __LINE__);
1942 return false;
1943 }
1944
1945 return true;
1946 }
1947
1948 static bool
intel_detect_swizzling(struct intel_screen * screen)1949 intel_detect_swizzling(struct intel_screen *screen)
1950 {
1951 /* Broadwell PRM says:
1952 *
1953 * "Before Gen8, there was a historical configuration control field to
1954 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1955 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1956 * DISP_ARB_CTL[14:13].
1957 *
1958 * For Gen8 and subsequent generations, the swizzle fields are all
1959 * reserved, and the CPU's memory controller performs all address
1960 * swizzling modifications."
1961 */
1962 if (screen->devinfo.gen >= 8)
1963 return false;
1964
1965 uint32_t tiling = I915_TILING_X;
1966 uint32_t swizzle_mode = 0;
1967 struct brw_bo *buffer =
1968 brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768,
1969 BRW_MEMZONE_OTHER, tiling, 512, 0);
1970 if (buffer == NULL)
1971 return false;
1972
1973 brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
1974 brw_bo_unreference(buffer);
1975
1976 return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
1977 }
1978
1979 static int
intel_detect_timestamp(struct intel_screen * screen)1980 intel_detect_timestamp(struct intel_screen *screen)
1981 {
1982 uint64_t dummy = 0, last = 0;
1983 int upper, lower, loops;
1984
1985 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1986 * TIMESTAMP register being shifted and the low 32bits always zero.
1987 *
1988 * More recent kernels offer an interface to read the full 36bits
1989 * everywhere.
1990 */
1991 if (brw_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0)
1992 return 3;
1993
1994 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1995 * upper 32bits for a rapidly changing timestamp.
1996 */
1997 if (brw_reg_read(screen->bufmgr, TIMESTAMP, &last))
1998 return 0;
1999
2000 upper = lower = 0;
2001 for (loops = 0; loops < 10; loops++) {
2002 /* The TIMESTAMP should change every 80ns, so several round trips
2003 * through the kernel should be enough to advance it.
2004 */
2005 if (brw_reg_read(screen->bufmgr, TIMESTAMP, &dummy))
2006 return 0;
2007
2008 upper += (dummy >> 32) != (last >> 32);
2009 if (upper > 1) /* beware 32bit counter overflow */
2010 return 2; /* upper dword holds the low 32bits of the timestamp */
2011
2012 lower += (dummy & 0xffffffff) != (last & 0xffffffff);
2013 if (lower > 1)
2014 return 1; /* timestamp is unshifted */
2015
2016 last = dummy;
2017 }
2018
2019 /* No advancement? No timestamp! */
2020 return 0;
2021 }
2022
2023 /**
2024 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
2025 *
2026 * Some combinations of hardware and kernel versions allow this feature,
2027 * while others don't. Instead of trying to enumerate every case, just
2028 * try and write a register and see if works.
2029 */
2030 static bool
intel_detect_pipelined_register(struct intel_screen * screen,int reg,uint32_t expected_value,bool reset)2031 intel_detect_pipelined_register(struct intel_screen *screen,
2032 int reg, uint32_t expected_value, bool reset)
2033 {
2034 if (screen->no_hw)
2035 return false;
2036
2037 struct brw_bo *results, *bo;
2038 uint32_t *batch;
2039 uint32_t offset = 0;
2040 void *map;
2041 bool success = false;
2042
2043 /* Create a zero'ed temporary buffer for reading our results */
2044 results = brw_bo_alloc(screen->bufmgr, "registers", 4096, BRW_MEMZONE_OTHER);
2045 if (results == NULL)
2046 goto err;
2047
2048 bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, BRW_MEMZONE_OTHER);
2049 if (bo == NULL)
2050 goto err_results;
2051
2052 map = brw_bo_map(NULL, bo, MAP_WRITE);
2053 if (!map)
2054 goto err_batch;
2055
2056 batch = map;
2057
2058 /* Write the register. */
2059 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2);
2060 *batch++ = reg;
2061 *batch++ = expected_value;
2062
2063 /* Save the register's value back to the buffer. */
2064 *batch++ = MI_STORE_REGISTER_MEM | (3 - 2);
2065 *batch++ = reg;
2066 struct drm_i915_gem_relocation_entry reloc = {
2067 .offset = (char *) batch - (char *) map,
2068 .delta = offset * sizeof(uint32_t),
2069 .target_handle = results->gem_handle,
2070 .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
2071 .write_domain = I915_GEM_DOMAIN_INSTRUCTION,
2072 };
2073 *batch++ = reloc.presumed_offset + reloc.delta;
2074
2075 /* And afterwards clear the register */
2076 if (reset) {
2077 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2);
2078 *batch++ = reg;
2079 *batch++ = 0;
2080 }
2081
2082 *batch++ = MI_BATCH_BUFFER_END;
2083
2084 struct drm_i915_gem_exec_object2 exec_objects[2] = {
2085 {
2086 .handle = results->gem_handle,
2087 },
2088 {
2089 .handle = bo->gem_handle,
2090 .relocation_count = 1,
2091 .relocs_ptr = (uintptr_t) &reloc,
2092 }
2093 };
2094
2095 struct drm_i915_gem_execbuffer2 execbuf = {
2096 .buffers_ptr = (uintptr_t) exec_objects,
2097 .buffer_count = 2,
2098 .batch_len = ALIGN((char *) batch - (char *) map, 8),
2099 .flags = I915_EXEC_RENDER,
2100 };
2101
2102 /* Don't bother with error checking - if the execbuf fails, the
2103 * value won't be written and we'll just report that there's no access.
2104 */
2105 drmIoctl(screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
2106
2107 /* Check whether the value got written. */
2108 void *results_map = brw_bo_map(NULL, results, MAP_READ);
2109 if (results_map) {
2110 success = *((uint32_t *)results_map + offset) == expected_value;
2111 brw_bo_unmap(results);
2112 }
2113
2114 err_batch:
2115 brw_bo_unreference(bo);
2116 err_results:
2117 brw_bo_unreference(results);
2118 err:
2119 return success;
2120 }
2121
2122 static bool
intel_detect_pipelined_so(struct intel_screen * screen)2123 intel_detect_pipelined_so(struct intel_screen *screen)
2124 {
2125 const struct gen_device_info *devinfo = &screen->devinfo;
2126
2127 /* Supposedly, Broadwell just works. */
2128 if (devinfo->gen >= 8)
2129 return true;
2130
2131 if (devinfo->gen <= 6)
2132 return false;
2133
2134 /* See the big explanation about command parser versions below */
2135 if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2))
2136 return true;
2137
2138 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2139 * statistics registers), and we already reset it to zero before using it.
2140 */
2141 return intel_detect_pipelined_register(screen,
2142 GEN7_SO_WRITE_OFFSET(0),
2143 0x1337d0d0,
2144 false);
2145 }
2146
2147 /**
2148 * Return array of MSAA modes supported by the hardware. The array is
2149 * zero-terminated and sorted in decreasing order.
2150 */
2151 const int*
intel_supported_msaa_modes(const struct intel_screen * screen)2152 intel_supported_msaa_modes(const struct intel_screen *screen)
2153 {
2154 static const int gen9_modes[] = {16, 8, 4, 2, 0, -1};
2155 static const int gen8_modes[] = {8, 4, 2, 0, -1};
2156 static const int gen7_modes[] = {8, 4, 0, -1};
2157 static const int gen6_modes[] = {4, 0, -1};
2158 static const int gen4_modes[] = {0, -1};
2159
2160 if (screen->devinfo.gen >= 9) {
2161 return gen9_modes;
2162 } else if (screen->devinfo.gen >= 8) {
2163 return gen8_modes;
2164 } else if (screen->devinfo.gen >= 7) {
2165 return gen7_modes;
2166 } else if (screen->devinfo.gen == 6) {
2167 return gen6_modes;
2168 } else {
2169 return gen4_modes;
2170 }
2171 }
2172
2173 static unsigned
intel_loader_get_cap(const __DRIscreen * dri_screen,enum dri_loader_cap cap)2174 intel_loader_get_cap(const __DRIscreen *dri_screen, enum dri_loader_cap cap)
2175 {
2176 if (dri_screen->dri2.loader && dri_screen->dri2.loader->base.version >= 4 &&
2177 dri_screen->dri2.loader->getCapability)
2178 return dri_screen->dri2.loader->getCapability(dri_screen->loaderPrivate, cap);
2179
2180 if (dri_screen->image.loader && dri_screen->image.loader->base.version >= 2 &&
2181 dri_screen->image.loader->getCapability)
2182 return dri_screen->image.loader->getCapability(dri_screen->loaderPrivate, cap);
2183
2184 return 0;
2185 }
2186
2187 static bool
intel_allowed_format(__DRIscreen * dri_screen,mesa_format format)2188 intel_allowed_format(__DRIscreen *dri_screen, mesa_format format)
2189 {
2190 struct intel_screen *screen = dri_screen->driverPrivate;
2191
2192 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2193 bool allow_rgba_ordering = intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING);
2194 if (!allow_rgba_ordering &&
2195 (format == MESA_FORMAT_R8G8B8A8_UNORM ||
2196 format == MESA_FORMAT_R8G8B8X8_UNORM ||
2197 format == MESA_FORMAT_R8G8B8A8_SRGB))
2198 return false;
2199
2200 /* Shall we expose 10 bpc formats? */
2201 bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache,
2202 "allow_rgb10_configs");
2203 if (!allow_rgb10_configs &&
2204 (format == MESA_FORMAT_B10G10R10A2_UNORM ||
2205 format == MESA_FORMAT_B10G10R10X2_UNORM))
2206 return false;
2207
2208 /* Shall we expose 565 formats? */
2209 bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache,
2210 "allow_rgb565_configs");
2211 if (!allow_rgb565_configs && format == MESA_FORMAT_B5G6R5_UNORM)
2212 return false;
2213
2214 /* Shall we expose fp16 formats? */
2215 bool allow_fp16_configs = driQueryOptionb(&screen->optionCache,
2216 "allow_fp16_configs");
2217 allow_fp16_configs &= intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_FP16);
2218 if (!allow_fp16_configs &&
2219 (format == MESA_FORMAT_RGBA_FLOAT16 ||
2220 format == MESA_FORMAT_RGBX_FLOAT16))
2221 return false;
2222
2223 return true;
2224 }
2225
2226 static __DRIconfig**
intel_screen_make_configs(__DRIscreen * dri_screen)2227 intel_screen_make_configs(__DRIscreen *dri_screen)
2228 {
2229 static const mesa_format formats[] = {
2230 MESA_FORMAT_B5G6R5_UNORM,
2231 MESA_FORMAT_B8G8R8A8_UNORM,
2232 MESA_FORMAT_B8G8R8X8_UNORM,
2233
2234 MESA_FORMAT_B8G8R8A8_SRGB,
2235 MESA_FORMAT_B8G8R8X8_SRGB,
2236
2237 /* For 10 bpc, 30 bit depth framebuffers. */
2238 MESA_FORMAT_B10G10R10A2_UNORM,
2239 MESA_FORMAT_B10G10R10X2_UNORM,
2240
2241 MESA_FORMAT_RGBA_FLOAT16,
2242 MESA_FORMAT_RGBX_FLOAT16,
2243
2244 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2245 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2246 * server may disagree on which format the GLXFBConfig represents,
2247 * resulting in swapped color channels.
2248 *
2249 * The problem, as of 2017-05-30:
2250 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2251 * order and chooses the first __DRIconfig with the expected channel
2252 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2253 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2254 *
2255 * EGL does not suffer from this problem. It correctly compares the
2256 * channel masks when matching EGLConfig to __DRIconfig.
2257 */
2258
2259 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2260 MESA_FORMAT_R8G8B8A8_UNORM,
2261
2262 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2263 MESA_FORMAT_R8G8B8X8_UNORM,
2264
2265 MESA_FORMAT_R8G8B8A8_SRGB,
2266 };
2267
2268 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2269 static const GLenum back_buffer_modes[] = {
2270 __DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE
2271 };
2272
2273 static const uint8_t singlesample_samples[1] = {0};
2274
2275 struct intel_screen *screen = dri_screen->driverPrivate;
2276 const struct gen_device_info *devinfo = &screen->devinfo;
2277 uint8_t depth_bits[4], stencil_bits[4];
2278 __DRIconfig **configs = NULL;
2279
2280 unsigned num_formats = ARRAY_SIZE(formats);
2281
2282 /* Generate singlesample configs, each without accumulation buffer
2283 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2284 */
2285 for (unsigned i = 0; i < num_formats; i++) {
2286 __DRIconfig **new_configs;
2287 int num_depth_stencil_bits = 1;
2288
2289 if (!intel_allowed_format(dri_screen, formats[i]))
2290 continue;
2291
2292 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2293 * buffer that has a different number of bits per pixel than the color
2294 * buffer, gen >= 6 supports this.
2295 */
2296 depth_bits[0] = 0;
2297 stencil_bits[0] = 0;
2298
2299 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
2300 if (devinfo->gen >= 8) {
2301 depth_bits[num_depth_stencil_bits] = 16;
2302 stencil_bits[num_depth_stencil_bits] = 0;
2303 num_depth_stencil_bits++;
2304 }
2305 if (devinfo->gen >= 6) {
2306 depth_bits[num_depth_stencil_bits] = 24;
2307 stencil_bits[num_depth_stencil_bits] = 8;
2308 num_depth_stencil_bits++;
2309 }
2310 } else {
2311 depth_bits[num_depth_stencil_bits] = 24;
2312 stencil_bits[num_depth_stencil_bits] = 8;
2313 num_depth_stencil_bits++;
2314 }
2315
2316 new_configs = driCreateConfigs(formats[i],
2317 depth_bits,
2318 stencil_bits,
2319 num_depth_stencil_bits,
2320 back_buffer_modes, 2,
2321 singlesample_samples, 1,
2322 false, false,
2323 /*mutable_render_buffer*/ true);
2324 configs = driConcatConfigs(configs, new_configs);
2325 }
2326
2327 /* Generate the minimum possible set of configs that include an
2328 * accumulation buffer.
2329 */
2330 for (unsigned i = 0; i < num_formats; i++) {
2331 __DRIconfig **new_configs;
2332
2333 if (!intel_allowed_format(dri_screen, formats[i]))
2334 continue;
2335
2336 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
2337 if (devinfo->gen >= 8) {
2338 depth_bits[0] = 16;
2339 stencil_bits[0] = 0;
2340 } else if (devinfo->gen >= 6) {
2341 depth_bits[0] = 24;
2342 stencil_bits[0] = 8;
2343 } else {
2344 depth_bits[0] = 0;
2345 stencil_bits[0] = 0;
2346 }
2347 } else {
2348 depth_bits[0] = 24;
2349 stencil_bits[0] = 8;
2350 }
2351
2352 new_configs = driCreateConfigs(formats[i],
2353 depth_bits, stencil_bits, 1,
2354 back_buffer_modes, 1,
2355 singlesample_samples, 1,
2356 true, false, false);
2357 configs = driConcatConfigs(configs, new_configs);
2358 }
2359
2360 /* Generate multisample configs.
2361 *
2362 * This loop breaks early, and hence is a no-op, on gen < 6.
2363 *
2364 * Multisample configs must follow the singlesample configs in order to
2365 * work around an X server bug present in 1.12. The X server chooses to
2366 * associate the first listed RGBA888-Z24S8 config, regardless of its
2367 * sample count, with the 32-bit depth visual used for compositing.
2368 *
2369 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2370 * supported. Singlebuffer configs are not supported because no one wants
2371 * them.
2372 */
2373 for (unsigned i = 0; i < num_formats; i++) {
2374 if (devinfo->gen < 6)
2375 break;
2376
2377 if (!intel_allowed_format(dri_screen, formats[i]))
2378 continue;
2379
2380 __DRIconfig **new_configs;
2381 const int num_depth_stencil_bits = 2;
2382 int num_msaa_modes = 0;
2383 const uint8_t *multisample_samples = NULL;
2384
2385 depth_bits[0] = 0;
2386 stencil_bits[0] = 0;
2387
2388 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM && devinfo->gen >= 8) {
2389 depth_bits[1] = 16;
2390 stencil_bits[1] = 0;
2391 } else {
2392 depth_bits[1] = 24;
2393 stencil_bits[1] = 8;
2394 }
2395
2396 if (devinfo->gen >= 9) {
2397 static const uint8_t multisample_samples_gen9[] = {2, 4, 8, 16};
2398 multisample_samples = multisample_samples_gen9;
2399 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen9);
2400 } else if (devinfo->gen == 8) {
2401 static const uint8_t multisample_samples_gen8[] = {2, 4, 8};
2402 multisample_samples = multisample_samples_gen8;
2403 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen8);
2404 } else if (devinfo->gen == 7) {
2405 static const uint8_t multisample_samples_gen7[] = {4, 8};
2406 multisample_samples = multisample_samples_gen7;
2407 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen7);
2408 } else if (devinfo->gen == 6) {
2409 static const uint8_t multisample_samples_gen6[] = {4};
2410 multisample_samples = multisample_samples_gen6;
2411 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen6);
2412 }
2413
2414 new_configs = driCreateConfigs(formats[i],
2415 depth_bits,
2416 stencil_bits,
2417 num_depth_stencil_bits,
2418 back_buffer_modes, 1,
2419 multisample_samples,
2420 num_msaa_modes,
2421 false, false, false);
2422 configs = driConcatConfigs(configs, new_configs);
2423 }
2424
2425 if (configs == NULL) {
2426 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
2427 __LINE__);
2428 return NULL;
2429 }
2430
2431 return configs;
2432 }
2433
2434 static void
set_max_gl_versions(struct intel_screen * screen)2435 set_max_gl_versions(struct intel_screen *screen)
2436 {
2437 __DRIscreen *dri_screen = screen->driScrnPriv;
2438 const bool has_astc = screen->devinfo.gen >= 9;
2439
2440 switch (screen->devinfo.gen) {
2441 case 11:
2442 case 10:
2443 case 9:
2444 case 8:
2445 dri_screen->max_gl_core_version = 46;
2446 dri_screen->max_gl_compat_version = 30;
2447 dri_screen->max_gl_es1_version = 11;
2448 dri_screen->max_gl_es2_version = has_astc ? 32 : 31;
2449 break;
2450 case 7:
2451 dri_screen->max_gl_core_version = 33;
2452 if (can_do_pipelined_register_writes(screen)) {
2453 dri_screen->max_gl_core_version = 42;
2454 if (screen->devinfo.is_haswell && can_do_compute_dispatch(screen))
2455 dri_screen->max_gl_core_version = 43;
2456 if (screen->devinfo.is_haswell && can_do_mi_math_and_lrr(screen))
2457 dri_screen->max_gl_core_version = 45;
2458 }
2459 dri_screen->max_gl_compat_version = 30;
2460 dri_screen->max_gl_es1_version = 11;
2461 dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30;
2462 break;
2463 case 6:
2464 dri_screen->max_gl_core_version = 33;
2465 dri_screen->max_gl_compat_version = 30;
2466 dri_screen->max_gl_es1_version = 11;
2467 dri_screen->max_gl_es2_version = 30;
2468 break;
2469 case 5:
2470 case 4:
2471 dri_screen->max_gl_core_version = 0;
2472 dri_screen->max_gl_compat_version = 21;
2473 dri_screen->max_gl_es1_version = 11;
2474 dri_screen->max_gl_es2_version = 20;
2475 break;
2476 default:
2477 unreachable("unrecognized intel_screen::gen");
2478 }
2479 }
2480
2481 static void
shader_debug_log_mesa(void * data,const char * fmt,...)2482 shader_debug_log_mesa(void *data, const char *fmt, ...)
2483 {
2484 struct brw_context *brw = (struct brw_context *)data;
2485 va_list args;
2486
2487 va_start(args, fmt);
2488 GLuint msg_id = 0;
2489 _mesa_gl_vdebugf(&brw->ctx, &msg_id,
2490 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2491 MESA_DEBUG_TYPE_OTHER,
2492 MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
2493 va_end(args);
2494 }
2495
2496 static void
shader_perf_log_mesa(void * data,const char * fmt,...)2497 shader_perf_log_mesa(void *data, const char *fmt, ...)
2498 {
2499 struct brw_context *brw = (struct brw_context *)data;
2500
2501 va_list args;
2502 va_start(args, fmt);
2503
2504 if (INTEL_DEBUG & DEBUG_PERF) {
2505 va_list args_copy;
2506 va_copy(args_copy, args);
2507 vfprintf(stderr, fmt, args_copy);
2508 va_end(args_copy);
2509 }
2510
2511 if (brw->perf_debug) {
2512 GLuint msg_id = 0;
2513 _mesa_gl_vdebugf(&brw->ctx, &msg_id,
2514 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2515 MESA_DEBUG_TYPE_PERFORMANCE,
2516 MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
2517 }
2518 va_end(args);
2519 }
2520
2521 /**
2522 * This is the driver specific part of the createNewScreen entry point.
2523 * Called when using DRI2.
2524 *
2525 * \return the struct gl_config supported by this driver
2526 */
2527 static const
intelInitScreen2(__DRIscreen * dri_screen)2528 __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
2529 {
2530 struct intel_screen *screen;
2531
2532 if (dri_screen->image.loader) {
2533 } else if (dri_screen->dri2.loader->base.version <= 2 ||
2534 dri_screen->dri2.loader->getBuffersWithFormat == NULL) {
2535 fprintf(stderr,
2536 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2537 "support required\n");
2538 return NULL;
2539 }
2540
2541 /* Allocate the private area */
2542 screen = rzalloc(NULL, struct intel_screen);
2543 if (!screen) {
2544 fprintf(stderr, "\nERROR! Allocating private area failed\n");
2545 return NULL;
2546 }
2547 /* parse information in __driConfigOptions */
2548 driOptionCache options;
2549 memset(&options, 0, sizeof(options));
2550
2551 driParseOptionInfo(&options, brw_driconf, ARRAY_SIZE(brw_driconf));
2552 driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum,
2553 "i965", NULL, NULL, 0, NULL, 0);
2554 driDestroyOptionCache(&options);
2555
2556 screen->driScrnPriv = dri_screen;
2557 dri_screen->driverPrivate = (void *) screen;
2558
2559 if (!gen_get_device_info_from_fd(dri_screen->fd, &screen->devinfo))
2560 return NULL;
2561
2562 const struct gen_device_info *devinfo = &screen->devinfo;
2563 screen->deviceID = devinfo->chipset_id;
2564 screen->no_hw = devinfo->no_hw;
2565
2566 if (devinfo->gen >= 12) {
2567 fprintf(stderr, "gen12 and newer are not supported on i965\n");
2568 return NULL;
2569 }
2570
2571 if (!intel_init_bufmgr(screen))
2572 return NULL;
2573
2574 brw_process_intel_debug_variable();
2575
2576 if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
2577 fprintf(stderr,
2578 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2579 intel_debug &= ~DEBUG_SHADER_TIME;
2580 }
2581
2582 if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) {
2583 /* Theorectically unlimited! At least for individual objects...
2584 *
2585 * Currently the entire (global) address space for all GTT maps is
2586 * limited to 64bits. That is all objects on the system that are
2587 * setup for GTT mmapping must fit within 64bits. An attempt to use
2588 * one that exceeds the limit with fail in brw_bo_map_gtt().
2589 *
2590 * Long before we hit that limit, we will be practically limited by
2591 * that any single object must fit in physical memory (RAM). The upper
2592 * limit on the CPU's address space is currently 48bits (Skylake), of
2593 * which only 39bits can be physical memory. (The GPU itself also has
2594 * a 48bit addressable virtual space.) We can fit over 32 million
2595 * objects of the current maximum allocable size before running out
2596 * of mmap space.
2597 */
2598 screen->max_gtt_map_object_size = UINT64_MAX;
2599 } else {
2600 /* Estimate the size of the mappable aperture into the GTT. There's an
2601 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2602 * It turns out it's basically always 256MB, though some ancient hardware
2603 * was smaller.
2604 */
2605 uint32_t gtt_size = 256 * 1024 * 1024;
2606
2607 /* We don't want to map two objects such that a memcpy between them would
2608 * just fault one mapping in and then the other over and over forever. So
2609 * we would need to divide the GTT size by 2. Additionally, some GTT is
2610 * taken up by things like the framebuffer and the ringbuffer and such, so
2611 * be more conservative.
2612 */
2613 screen->max_gtt_map_object_size = gtt_size / 4;
2614 }
2615
2616 screen->aperture_threshold = devinfo->aperture_bytes * 3 / 4;
2617
2618 screen->hw_has_swizzling = intel_detect_swizzling(screen);
2619 screen->hw_has_timestamp = intel_detect_timestamp(screen);
2620
2621 isl_device_init(&screen->isl_dev, &screen->devinfo,
2622 screen->hw_has_swizzling);
2623
2624 if (devinfo->gen >= 10)
2625 intel_cs_timestamp_frequency(screen);
2626
2627 /* GENs prior to 8 do not support EU/Subslice info */
2628 if (devinfo->gen >= 8) {
2629 intel_detect_sseu(screen);
2630 } else if (devinfo->gen == 7) {
2631 screen->subslice_total = 1 << (devinfo->gt - 1);
2632 }
2633
2634 /* Gen7-7.5 kernel requirements / command parser saga:
2635 *
2636 * - pre-v3.16:
2637 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2638 *
2639 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2640 * all batches secure, allowing them to use any feature with no checking.
2641 * This is effectively equivalent to a command parser version of
2642 * \infinity - everything is possible.
2643 *
2644 * The command parser does not exist, and querying the version will
2645 * return -EINVAL.
2646 *
2647 * - v3.16:
2648 * The kernel enables the command parser by default, for systems with
2649 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2650 * hardware checker is still enabled, so Haswell and Baytrail cannot
2651 * do anything.
2652 *
2653 * Ivybridge goes from "everything is possible" to "only what the
2654 * command parser allows" (if the user boots with i915.cmd_parser=0,
2655 * then everything is possible again). We can only safely use features
2656 * allowed by the supported command parser version.
2657 *
2658 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2659 * implemented by the kernel, even if it's turned off. So, checking
2660 * for version > 0 does not mean that you can write registers. We have
2661 * to try it and see. The version does, however, indicate the age of
2662 * the kernel.
2663 *
2664 * Instead of matching the hardware checker's behavior of converting
2665 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2666 * -EINVAL, making it dangerous to try and use privileged features.
2667 *
2668 * Effective command parser versions:
2669 * - Haswell: 0 (reporting 1, writes don't work)
2670 * - Baytrail: 0 (reporting 1, writes don't work)
2671 * - Ivybridge: 1 (enabled) or infinite (disabled)
2672 *
2673 * - v3.17:
2674 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2675 * effectively version 1 (enabled) or infinite (disabled).
2676 *
2677 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2678 * Command parser v2 supports predicate writes.
2679 *
2680 * - Haswell: 0 (reporting 1, writes don't work)
2681 * - Baytrail: 2 (enabled) or infinite (disabled)
2682 * - Ivybridge: 2 (enabled) or infinite (disabled)
2683 *
2684 * So version >= 2 is enough to know that Ivybridge and Baytrail
2685 * will work. Haswell still can't do anything.
2686 *
2687 * - v4.0: Version 3 happened. Largely not relevant.
2688 *
2689 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2690 * L3 config registers are properly saved and restored as part
2691 * of the hardware context. We can approximately detect this point
2692 * in time by checking if I915_PARAM_REVISION is recognized - it
2693 * landed in a later commit, but in the same release cycle.
2694 *
2695 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2696 * Command parser finally gains secure batch promotion. On Haswell,
2697 * the hardware checker gets disabled, which finally allows it to do
2698 * privileged commands.
2699 *
2700 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2701 * - Haswell: 3 (enabled) or 0 (disabled)
2702 * - Baytrail: 3 (enabled) or infinite (disabled)
2703 * - Ivybridge: 3 (enabled) or infinite (disabled)
2704 *
2705 * Unfortunately, detecting this point in time is tricky, because
2706 * no version bump happened when this important change occurred.
2707 * On Haswell, if we can write any register, then the kernel is at
2708 * least this new, and we can start trusting the version number.
2709 *
2710 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2711 * Command parser reaches version 4, allowing access to Haswell
2712 * atomic scratch and chicken3 registers. If version >= 4, we know
2713 * the kernel is new enough to support privileged features on all
2714 * hardware. However, the user might have disabled it...and the
2715 * kernel will still report version 4. So we still have to guess
2716 * and check.
2717 *
2718 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2719 * Command parser v5 whitelists indirect compute shader dispatch
2720 * registers, needed for OpenGL 4.3 and later.
2721 *
2722 * - v4.8:
2723 * Command parser v7 lets us use MI_MATH on Haswell.
2724 *
2725 * Additionally, the kernel begins reporting version 0 when
2726 * the command parser is disabled, allowing us to skip the
2727 * guess-and-check step on Haswell. Unfortunately, this also
2728 * means that we can no longer use it as an indicator of the
2729 * age of the kernel.
2730 */
2731 if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION,
2732 &screen->cmd_parser_version) < 0) {
2733 /* Command parser does not exist - getparam is unrecognized */
2734 screen->cmd_parser_version = 0;
2735 }
2736
2737 /* Kernel 4.13 retuired for exec object capture */
2738 if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_CAPTURE)) {
2739 screen->kernel_features |= KERNEL_ALLOWS_EXEC_CAPTURE;
2740 }
2741
2742 if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_BATCH_FIRST)) {
2743 screen->kernel_features |= KERNEL_ALLOWS_EXEC_BATCH_FIRST;
2744 }
2745
2746 if (!intel_detect_pipelined_so(screen)) {
2747 /* We can't do anything, so the effective version is 0. */
2748 screen->cmd_parser_version = 0;
2749 } else {
2750 screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
2751 }
2752
2753 if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2)
2754 screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
2755
2756 /* Haswell requires command parser version 4 in order to have L3
2757 * atomic scratch1 and chicken3 bits
2758 */
2759 if (devinfo->is_haswell && screen->cmd_parser_version >= 4) {
2760 screen->kernel_features |=
2761 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3;
2762 }
2763
2764 /* Haswell requires command parser version 6 in order to write to the
2765 * MI_MATH GPR registers, and version 7 in order to use
2766 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2767 */
2768 if (devinfo->gen >= 8 ||
2769 (devinfo->is_haswell && screen->cmd_parser_version >= 7)) {
2770 screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
2771 }
2772
2773 /* Gen7 needs at least command parser version 5 to support compute */
2774 if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5)
2775 screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
2776
2777 if (intel_get_boolean(screen, I915_PARAM_HAS_CONTEXT_ISOLATION))
2778 screen->kernel_features |= KERNEL_ALLOWS_CONTEXT_ISOLATION;
2779
2780 const char *force_msaa = getenv("INTEL_FORCE_MSAA");
2781 if (force_msaa) {
2782 screen->winsys_msaa_samples_override =
2783 intel_quantize_num_samples(screen, atoi(force_msaa));
2784 printf("Forcing winsys sample count to %d\n",
2785 screen->winsys_msaa_samples_override);
2786 } else {
2787 screen->winsys_msaa_samples_override = -1;
2788 }
2789
2790 set_max_gl_versions(screen);
2791
2792 /* Notification of GPU resets requires hardware contexts and a kernel new
2793 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2794 * supported, calling it with a context of 0 will either generate EPERM or
2795 * no error. If the ioctl is not supported, it always generate EINVAL.
2796 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2797 * extension to the loader.
2798 *
2799 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2800 */
2801 if (devinfo->gen >= 6) {
2802 struct drm_i915_reset_stats stats;
2803 memset(&stats, 0, sizeof(stats));
2804
2805 const int ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats);
2806
2807 screen->has_context_reset_notification =
2808 (ret != -1 || errno != EINVAL);
2809 }
2810
2811 dri_screen->extensions = !screen->has_context_reset_notification
2812 ? screenExtensions : intelRobustScreenExtensions;
2813
2814 screen->compiler = brw_compiler_create(screen, devinfo);
2815 screen->compiler->shader_debug_log = shader_debug_log_mesa;
2816 screen->compiler->shader_perf_log = shader_perf_log_mesa;
2817
2818 /* Changing the meaning of constant buffer pointers from a dynamic state
2819 * offset to an absolute address is only safe if the kernel isolates other
2820 * contexts from our changes.
2821 */
2822 screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8 ||
2823 !(screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION);
2824
2825 screen->compiler->glsl_compiler_options[MESA_SHADER_VERTEX].PositionAlwaysInvariant = driQueryOptionb(&screen->optionCache, "vs_position_always_invariant");
2826
2827 screen->compiler->supports_pull_constants = true;
2828 screen->compiler->compact_params = true;
2829 screen->compiler->lower_variable_group_size = true;
2830
2831 screen->has_exec_fence =
2832 intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);
2833
2834 intel_screen_init_surface_formats(screen);
2835
2836 if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
2837 unsigned int caps = intel_get_integer(screen, I915_PARAM_HAS_SCHEDULER);
2838 if (caps) {
2839 fprintf(stderr, "Kernel scheduler detected: %08x\n", caps);
2840 if (caps & I915_SCHEDULER_CAP_PRIORITY)
2841 fprintf(stderr, " - User priority sorting enabled\n");
2842 if (caps & I915_SCHEDULER_CAP_PREEMPTION)
2843 fprintf(stderr, " - Preemption enabled\n");
2844 }
2845 }
2846
2847 brw_disk_cache_init(screen);
2848
2849 return (const __DRIconfig**) intel_screen_make_configs(dri_screen);
2850 }
2851
2852 struct intel_buffer {
2853 __DRIbuffer base;
2854 struct brw_bo *bo;
2855 };
2856
2857 static __DRIbuffer *
intelAllocateBuffer(__DRIscreen * dri_screen,unsigned attachment,unsigned format,int width,int height)2858 intelAllocateBuffer(__DRIscreen *dri_screen,
2859 unsigned attachment, unsigned format,
2860 int width, int height)
2861 {
2862 struct intel_buffer *intelBuffer;
2863 struct intel_screen *screen = dri_screen->driverPrivate;
2864
2865 assert(attachment == __DRI_BUFFER_FRONT_LEFT ||
2866 attachment == __DRI_BUFFER_BACK_LEFT);
2867
2868 intelBuffer = calloc(1, sizeof *intelBuffer);
2869 if (intelBuffer == NULL)
2870 return NULL;
2871
2872 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2873 * supports Y tiled and compressed buffers, but there is no way to plumb that
2874 * through to here. */
2875 uint32_t pitch;
2876 int cpp = format / 8;
2877 intelBuffer->bo = brw_bo_alloc_tiled_2d(screen->bufmgr,
2878 "intelAllocateBuffer",
2879 width,
2880 height,
2881 cpp,
2882 BRW_MEMZONE_OTHER,
2883 I915_TILING_X, &pitch,
2884 BO_ALLOC_BUSY);
2885
2886 if (intelBuffer->bo == NULL) {
2887 free(intelBuffer);
2888 return NULL;
2889 }
2890
2891 brw_bo_flink(intelBuffer->bo, &intelBuffer->base.name);
2892
2893 intelBuffer->base.attachment = attachment;
2894 intelBuffer->base.cpp = cpp;
2895 intelBuffer->base.pitch = pitch;
2896
2897 return &intelBuffer->base;
2898 }
2899
2900 static void
intelReleaseBuffer(UNUSED __DRIscreen * dri_screen,__DRIbuffer * buffer)2901 intelReleaseBuffer(UNUSED __DRIscreen *dri_screen, __DRIbuffer *buffer)
2902 {
2903 struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer;
2904
2905 brw_bo_unreference(intelBuffer->bo);
2906 free(intelBuffer);
2907 }
2908
2909 static const struct __DriverAPIRec brw_driver_api = {
2910 .InitScreen = intelInitScreen2,
2911 .DestroyScreen = intelDestroyScreen,
2912 .CreateContext = brwCreateContext,
2913 .DestroyContext = intelDestroyContext,
2914 .CreateBuffer = intelCreateBuffer,
2915 .DestroyBuffer = intelDestroyBuffer,
2916 .MakeCurrent = intelMakeCurrent,
2917 .UnbindContext = intelUnbindContext,
2918 .AllocateBuffer = intelAllocateBuffer,
2919 .ReleaseBuffer = intelReleaseBuffer
2920 };
2921
2922 static const struct __DRIDriverVtableExtensionRec brw_vtable = {
2923 .base = { __DRI_DRIVER_VTABLE, 1 },
2924 .vtable = &brw_driver_api,
2925 };
2926
2927 static const __DRIextension *brw_driver_extensions[] = {
2928 &driCoreExtension.base,
2929 &driImageDriverExtension.base,
2930 &driDRI2Extension.base,
2931 &brw_vtable.base,
2932 &brw_config_options.base,
2933 NULL
2934 };
2935
__driDriverGetExtensions_i965(void)2936 PUBLIC const __DRIextension **__driDriverGetExtensions_i965(void)
2937 {
2938 globalDriverAPI = &brw_driver_api;
2939
2940 return brw_driver_extensions;
2941 }
2942