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1 //===-- ArchSpec.cpp ------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "lldb/Utility/ArchSpec.h"
10 
11 #include "lldb/Utility/Log.h"
12 #include "lldb/Utility/StringList.h"
13 #include "lldb/lldb-defines.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/BinaryFormat/COFF.h"
16 #include "llvm/BinaryFormat/ELF.h"
17 #include "llvm/BinaryFormat/MachO.h"
18 #include "llvm/Support/Compiler.h"
19 
20 using namespace lldb;
21 using namespace lldb_private;
22 
23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
24                         bool try_inverse, bool enforce_exact_match);
25 
26 namespace lldb_private {
27 
28 struct CoreDefinition {
29   ByteOrder default_byte_order;
30   uint32_t addr_byte_size;
31   uint32_t min_opcode_byte_size;
32   uint32_t max_opcode_byte_size;
33   llvm::Triple::ArchType machine;
34   ArchSpec::Core core;
35   const char *const name;
36 };
37 
38 } // namespace lldb_private
39 
40 // This core information can be looked using the ArchSpec::Core as the index
41 static const CoreDefinition g_core_definitions[] = {
42     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
43      "arm"},
44     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
45      "armv4"},
46     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
47      "armv4t"},
48     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
49      "armv5"},
50     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
51      "armv5e"},
52     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
53      "armv5t"},
54     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
55      "armv6"},
56     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
57      "armv6m"},
58     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
59      "armv7"},
60     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
61      "armv7l"},
62     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
63      "armv7f"},
64     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
65      "armv7s"},
66     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
67      "armv7k"},
68     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
69      "armv7m"},
70     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
71      "armv7em"},
72     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
73      "xscale"},
74     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
75      "thumb"},
76     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
77      "thumbv4t"},
78     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
79      "thumbv5"},
80     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
81      "thumbv5e"},
82     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
83      "thumbv6"},
84     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
85      "thumbv6m"},
86     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
87      "thumbv7"},
88     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
89      "thumbv7f"},
90     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
91      "thumbv7s"},
92     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
93      "thumbv7k"},
94     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
95      "thumbv7m"},
96     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
97      "thumbv7em"},
98     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
99      ArchSpec::eCore_arm_arm64, "arm64"},
100     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
101      ArchSpec::eCore_arm_armv8, "armv8"},
102     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm,
103      ArchSpec::eCore_arm_armv8l, "armv8l"},
104     {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
105      ArchSpec::eCore_arm_arm64_32, "arm64_32"},
106     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
107      ArchSpec::eCore_arm_aarch64, "aarch64"},
108 
109     // mips32, mips32r2, mips32r3, mips32r5, mips32r6
110     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
111      "mips"},
112     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
113      "mipsr2"},
114     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
115      "mipsr3"},
116     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
117      "mipsr5"},
118     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
119      "mipsr6"},
120     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
121      "mipsel"},
122     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
123      ArchSpec::eCore_mips32r2el, "mipsr2el"},
124     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
125      ArchSpec::eCore_mips32r3el, "mipsr3el"},
126     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
127      ArchSpec::eCore_mips32r5el, "mipsr5el"},
128     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
129      ArchSpec::eCore_mips32r6el, "mipsr6el"},
130 
131     // mips64, mips64r2, mips64r3, mips64r5, mips64r6
132     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
133      "mips64"},
134     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
135      "mips64r2"},
136     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
137      "mips64r3"},
138     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
139      "mips64r5"},
140     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
141      "mips64r6"},
142     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
143      ArchSpec::eCore_mips64el, "mips64el"},
144     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
145      ArchSpec::eCore_mips64r2el, "mips64r2el"},
146     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
147      ArchSpec::eCore_mips64r3el, "mips64r3el"},
148     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
149      ArchSpec::eCore_mips64r5el, "mips64r5el"},
150     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
151      ArchSpec::eCore_mips64r6el, "mips64r6el"},
152 
153     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
154      "powerpc"},
155     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
156      "ppc601"},
157     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
158      "ppc602"},
159     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
160      "ppc603"},
161     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
162      "ppc603e"},
163     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
164      "ppc603ev"},
165     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
166      "ppc604"},
167     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
168      "ppc604e"},
169     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
170      "ppc620"},
171     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
172      "ppc750"},
173     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
174      "ppc7400"},
175     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
176      "ppc7450"},
177     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
178      "ppc970"},
179 
180     {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
181      ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
182     {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
183      "powerpc64"},
184     {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
185      ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
186 
187     {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
188      ArchSpec::eCore_s390x_generic, "s390x"},
189 
190     {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
191      ArchSpec::eCore_sparc_generic, "sparc"},
192     {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
193      ArchSpec::eCore_sparc9_generic, "sparcv9"},
194 
195     {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
196      "i386"},
197     {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
198      "i486"},
199     {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
200      ArchSpec::eCore_x86_32_i486sx, "i486sx"},
201     {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
202      "i686"},
203 
204     {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
205      ArchSpec::eCore_x86_64_x86_64, "x86_64"},
206     {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
207      ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
208     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
209      ArchSpec::eCore_hexagon_generic, "hexagon"},
210     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
211      ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
212     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
213      ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
214 
215     {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
216      ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
217     {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
218      ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
219     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
220 
221     {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
222 
223     {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
224      "wasm32"},
225 };
226 
227 // Ensure that we have an entry in the g_core_definitions for each core. If you
228 // comment out an entry above, you will need to comment out the corresponding
229 // ArchSpec::Core enumeration.
230 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
231                   ArchSpec::kNumCores,
232               "make sure we have one core definition for each core");
233 
234 struct ArchDefinitionEntry {
235   ArchSpec::Core core;
236   uint32_t cpu;
237   uint32_t sub;
238   uint32_t cpu_mask;
239   uint32_t sub_mask;
240 };
241 
242 struct ArchDefinition {
243   ArchitectureType type;
244   size_t num_entries;
245   const ArchDefinitionEntry *entries;
246   const char *name;
247 };
248 
ListSupportedArchNames(StringList & list)249 void ArchSpec::ListSupportedArchNames(StringList &list) {
250   for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
251     list.AppendString(g_core_definitions[i].name);
252 }
253 
AutoComplete(CompletionRequest & request)254 void ArchSpec::AutoComplete(CompletionRequest &request) {
255   for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
256     request.TryCompleteCurrentArg(g_core_definitions[i].name);
257 }
258 
259 #define CPU_ANY (UINT32_MAX)
260 
261 //===----------------------------------------------------------------------===//
262 // A table that gets searched linearly for matches. This table is used to
263 // convert cpu type and subtypes to architecture names, and to convert
264 // architecture names to cpu types and subtypes. The ordering is important and
265 // allows the precedence to be set when the table is built.
266 #define SUBTYPE_MASK 0x00FFFFFFu
267 
268 // clang-format off
269 static const ArchDefinitionEntry g_macho_arch_entries[] = {
270     {ArchSpec::eCore_arm_generic,     llvm::MachO::CPU_TYPE_ARM,        CPU_ANY,                                UINT32_MAX, UINT32_MAX},
271     {ArchSpec::eCore_arm_generic,     llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_ALL,       UINT32_MAX, SUBTYPE_MASK},
272     {ArchSpec::eCore_arm_armv4,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V4T,       UINT32_MAX, SUBTYPE_MASK},
273     {ArchSpec::eCore_arm_armv4t,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V4T,       UINT32_MAX, SUBTYPE_MASK},
274     {ArchSpec::eCore_arm_armv6,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V6,        UINT32_MAX, SUBTYPE_MASK},
275     {ArchSpec::eCore_arm_armv6m,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V6M,       UINT32_MAX, SUBTYPE_MASK},
276     {ArchSpec::eCore_arm_armv5,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ,     UINT32_MAX, SUBTYPE_MASK},
277     {ArchSpec::eCore_arm_armv5e,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ,     UINT32_MAX, SUBTYPE_MASK},
278     {ArchSpec::eCore_arm_armv5t,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ,     UINT32_MAX, SUBTYPE_MASK},
279     {ArchSpec::eCore_arm_xscale,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_XSCALE,    UINT32_MAX, SUBTYPE_MASK},
280     {ArchSpec::eCore_arm_armv7,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7,        UINT32_MAX, SUBTYPE_MASK},
281     {ArchSpec::eCore_arm_armv7f,      llvm::MachO::CPU_TYPE_ARM,        10,                                     UINT32_MAX, SUBTYPE_MASK},
282     {ArchSpec::eCore_arm_armv7s,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7S,       UINT32_MAX, SUBTYPE_MASK},
283     {ArchSpec::eCore_arm_armv7k,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7K,       UINT32_MAX, SUBTYPE_MASK},
284     {ArchSpec::eCore_arm_armv7m,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7M,       UINT32_MAX, SUBTYPE_MASK},
285     {ArchSpec::eCore_arm_armv7em,     llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7EM,      UINT32_MAX, SUBTYPE_MASK},
286     // FIXME: This should be arm64e once the triple exists.
287     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      llvm::MachO::CPU_SUBTYPE_ARM64E,        UINT32_MAX, SUBTYPE_MASK},
288     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      llvm::MachO::CPU_SUBTYPE_ARM64_V8,      UINT32_MAX, SUBTYPE_MASK},
289     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      llvm::MachO::CPU_SUBTYPE_ARM64_ALL,     UINT32_MAX, SUBTYPE_MASK},
290     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      13,                                     UINT32_MAX, SUBTYPE_MASK},
291     {ArchSpec::eCore_arm_arm64_32,    llvm::MachO::CPU_TYPE_ARM64_32,   0,                                      UINT32_MAX, SUBTYPE_MASK},
292     {ArchSpec::eCore_arm_arm64_32,    llvm::MachO::CPU_TYPE_ARM64_32,   1,                                      UINT32_MAX, SUBTYPE_MASK},
293     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      CPU_ANY,                                UINT32_MAX, SUBTYPE_MASK},
294     {ArchSpec::eCore_thumb,           llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_ALL,       UINT32_MAX, SUBTYPE_MASK},
295     {ArchSpec::eCore_thumbv4t,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V4T,       UINT32_MAX, SUBTYPE_MASK},
296     {ArchSpec::eCore_thumbv5,         llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5,        UINT32_MAX, SUBTYPE_MASK},
297     {ArchSpec::eCore_thumbv5e,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5,        UINT32_MAX, SUBTYPE_MASK},
298     {ArchSpec::eCore_thumbv6,         llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V6,        UINT32_MAX, SUBTYPE_MASK},
299     {ArchSpec::eCore_thumbv6m,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V6M,       UINT32_MAX, SUBTYPE_MASK},
300     {ArchSpec::eCore_thumbv7,         llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7,        UINT32_MAX, SUBTYPE_MASK},
301     {ArchSpec::eCore_thumbv7f,        llvm::MachO::CPU_TYPE_ARM,        10,                                     UINT32_MAX, SUBTYPE_MASK},
302     {ArchSpec::eCore_thumbv7s,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7S,       UINT32_MAX, SUBTYPE_MASK},
303     {ArchSpec::eCore_thumbv7k,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7K,       UINT32_MAX, SUBTYPE_MASK},
304     {ArchSpec::eCore_thumbv7m,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7M,       UINT32_MAX, SUBTYPE_MASK},
305     {ArchSpec::eCore_thumbv7em,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7EM,      UINT32_MAX, SUBTYPE_MASK},
306     {ArchSpec::eCore_ppc_generic,     llvm::MachO::CPU_TYPE_POWERPC,    CPU_ANY,                                UINT32_MAX, UINT32_MAX},
307     {ArchSpec::eCore_ppc_generic,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_ALL,   UINT32_MAX, SUBTYPE_MASK},
308     {ArchSpec::eCore_ppc_ppc601,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_601,   UINT32_MAX, SUBTYPE_MASK},
309     {ArchSpec::eCore_ppc_ppc602,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_602,   UINT32_MAX, SUBTYPE_MASK},
310     {ArchSpec::eCore_ppc_ppc603,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_603,   UINT32_MAX, SUBTYPE_MASK},
311     {ArchSpec::eCore_ppc_ppc603e,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_603e,  UINT32_MAX, SUBTYPE_MASK},
312     {ArchSpec::eCore_ppc_ppc603ev,    llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
313     {ArchSpec::eCore_ppc_ppc604,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_604,   UINT32_MAX, SUBTYPE_MASK},
314     {ArchSpec::eCore_ppc_ppc604e,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_604e,  UINT32_MAX, SUBTYPE_MASK},
315     {ArchSpec::eCore_ppc_ppc620,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_620,   UINT32_MAX, SUBTYPE_MASK},
316     {ArchSpec::eCore_ppc_ppc750,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_750,   UINT32_MAX, SUBTYPE_MASK},
317     {ArchSpec::eCore_ppc_ppc7400,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_7400,  UINT32_MAX, SUBTYPE_MASK},
318     {ArchSpec::eCore_ppc_ppc7450,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_7450,  UINT32_MAX, SUBTYPE_MASK},
319     {ArchSpec::eCore_ppc_ppc970,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_970,   UINT32_MAX, SUBTYPE_MASK},
320     {ArchSpec::eCore_ppc64_generic,   llvm::MachO::CPU_TYPE_POWERPC64,  llvm::MachO::CPU_SUBTYPE_POWERPC_ALL,   UINT32_MAX, SUBTYPE_MASK},
321     {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64,  CPU_ANY,                                UINT32_MAX, SUBTYPE_MASK},
322     {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64,  100,                                    UINT32_MAX, SUBTYPE_MASK},
323     {ArchSpec::eCore_x86_32_i386,     llvm::MachO::CPU_TYPE_I386,       llvm::MachO::CPU_SUBTYPE_I386_ALL,      UINT32_MAX, SUBTYPE_MASK},
324     {ArchSpec::eCore_x86_32_i486,     llvm::MachO::CPU_TYPE_I386,       llvm::MachO::CPU_SUBTYPE_486,           UINT32_MAX, SUBTYPE_MASK},
325     {ArchSpec::eCore_x86_32_i486sx,   llvm::MachO::CPU_TYPE_I386,       llvm::MachO::CPU_SUBTYPE_486SX,         UINT32_MAX, SUBTYPE_MASK},
326     {ArchSpec::eCore_x86_32_i386,     llvm::MachO::CPU_TYPE_I386,       CPU_ANY,                                UINT32_MAX, UINT32_MAX},
327     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_64_ALL,    UINT32_MAX, SUBTYPE_MASK},
328     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_ARCH1,     UINT32_MAX, SUBTYPE_MASK},
329     {ArchSpec::eCore_x86_64_x86_64h,  llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_64_H,      UINT32_MAX, SUBTYPE_MASK},
330     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     CPU_ANY, UINT32_MAX, UINT32_MAX},
331     // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
332     {ArchSpec::eCore_uknownMach32,    0,                                0,                                      0xFF000000u, 0x00000000u},
333     {ArchSpec::eCore_uknownMach64,    llvm::MachO::CPU_ARCH_ABI64,      0,                                      0xFF000000u, 0x00000000u}};
334 // clang-format on
335 
336 static const ArchDefinition g_macho_arch_def = {
337     eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries),
338     g_macho_arch_entries, "mach-o"};
339 
340 //===----------------------------------------------------------------------===//
341 // A table that gets searched linearly for matches. This table is used to
342 // convert cpu type and subtypes to architecture names, and to convert
343 // architecture names to cpu types and subtypes. The ordering is important and
344 // allows the precedence to be set when the table is built.
345 static const ArchDefinitionEntry g_elf_arch_entries[] = {
346     {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
347      0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
348     {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
349      0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
350     {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
351      0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
352     {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
353      0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
354     {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
355      0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
356     {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
357      0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
358     {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
359      0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
360     {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
361      0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
362     {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
363      0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
364     {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
365      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
366     {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
367      0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
368     {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
369      0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
370     {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
371      ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
372     {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
373      ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
374     {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
375      ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
376     {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
377      ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
378     {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
379      ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
380     {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
381      0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
382     {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
383      ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
384     {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
385      ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
386     {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
387      ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
388     {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
389      ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
390     {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
391      ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
392     {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
393      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
394     {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
395      0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
396     {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
397      0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR
398 };
399 
400 static const ArchDefinition g_elf_arch_def = {
401     eArchTypeELF,
402     llvm::array_lengthof(g_elf_arch_entries),
403     g_elf_arch_entries,
404     "elf",
405 };
406 
407 static const ArchDefinitionEntry g_coff_arch_entries[] = {
408     {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
409      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
410     {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
411      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
412     {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
413      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
414     {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
415      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
416     {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
417      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
418     {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
419      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
420     {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
421      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
422     {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
423      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
424 };
425 
426 static const ArchDefinition g_coff_arch_def = {
427     eArchTypeCOFF,
428     llvm::array_lengthof(g_coff_arch_entries),
429     g_coff_arch_entries,
430     "pe-coff",
431 };
432 
433 //===----------------------------------------------------------------------===//
434 // Table of all ArchDefinitions
435 static const ArchDefinition *g_arch_definitions[] = {
436     &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def};
437 
438 static const size_t k_num_arch_definitions =
439     llvm::array_lengthof(g_arch_definitions);
440 
441 //===----------------------------------------------------------------------===//
442 // Static helper functions.
443 
444 // Get the architecture definition for a given object type.
FindArchDefinition(ArchitectureType arch_type)445 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) {
446   for (unsigned int i = 0; i < k_num_arch_definitions; ++i) {
447     const ArchDefinition *def = g_arch_definitions[i];
448     if (def->type == arch_type)
449       return def;
450   }
451   return nullptr;
452 }
453 
454 // Get an architecture definition by name.
FindCoreDefinition(llvm::StringRef name)455 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
456   for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) {
457     if (name.equals_lower(g_core_definitions[i].name))
458       return &g_core_definitions[i];
459   }
460   return nullptr;
461 }
462 
FindCoreDefinition(ArchSpec::Core core)463 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) {
464   if (core < llvm::array_lengthof(g_core_definitions))
465     return &g_core_definitions[core];
466   return nullptr;
467 }
468 
469 // Get a definition entry by cpu type and subtype.
470 static const ArchDefinitionEntry *
FindArchDefinitionEntry(const ArchDefinition * def,uint32_t cpu,uint32_t sub)471 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) {
472   if (def == nullptr)
473     return nullptr;
474 
475   const ArchDefinitionEntry *entries = def->entries;
476   for (size_t i = 0; i < def->num_entries; ++i) {
477     if (entries[i].cpu == (cpu & entries[i].cpu_mask))
478       if (entries[i].sub == (sub & entries[i].sub_mask))
479         return &entries[i];
480   }
481   return nullptr;
482 }
483 
484 static const ArchDefinitionEntry *
FindArchDefinitionEntry(const ArchDefinition * def,ArchSpec::Core core)485 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) {
486   if (def == nullptr)
487     return nullptr;
488 
489   const ArchDefinitionEntry *entries = def->entries;
490   for (size_t i = 0; i < def->num_entries; ++i) {
491     if (entries[i].core == core)
492       return &entries[i];
493   }
494   return nullptr;
495 }
496 
497 //===----------------------------------------------------------------------===//
498 // Constructors and destructors.
499 
ArchSpec()500 ArchSpec::ArchSpec() {}
501 
ArchSpec(const char * triple_cstr)502 ArchSpec::ArchSpec(const char *triple_cstr) {
503   if (triple_cstr)
504     SetTriple(triple_cstr);
505 }
506 
ArchSpec(llvm::StringRef triple_str)507 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
508 
ArchSpec(const llvm::Triple & triple)509 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
510 
ArchSpec(ArchitectureType arch_type,uint32_t cpu,uint32_t subtype)511 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
512   SetArchitecture(arch_type, cpu, subtype);
513 }
514 
515 ArchSpec::~ArchSpec() = default;
516 
Clear()517 void ArchSpec::Clear() {
518   m_triple = llvm::Triple();
519   m_core = kCore_invalid;
520   m_byte_order = eByteOrderInvalid;
521   m_distribution_id.Clear();
522   m_flags = 0;
523 }
524 
525 //===----------------------------------------------------------------------===//
526 // Predicates.
527 
GetArchitectureName() const528 const char *ArchSpec::GetArchitectureName() const {
529   const CoreDefinition *core_def = FindCoreDefinition(m_core);
530   if (core_def)
531     return core_def->name;
532   return "unknown";
533 }
534 
IsMIPS() const535 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
536 
GetTargetABI() const537 std::string ArchSpec::GetTargetABI() const {
538 
539   std::string abi;
540 
541   if (IsMIPS()) {
542     switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
543     case ArchSpec::eMIPSABI_N64:
544       abi = "n64";
545       return abi;
546     case ArchSpec::eMIPSABI_N32:
547       abi = "n32";
548       return abi;
549     case ArchSpec::eMIPSABI_O32:
550       abi = "o32";
551       return abi;
552     default:
553       return abi;
554     }
555   }
556   return abi;
557 }
558 
SetFlags(const std::string & elf_abi)559 void ArchSpec::SetFlags(const std::string &elf_abi) {
560 
561   uint32_t flag = GetFlags();
562   if (IsMIPS()) {
563     if (elf_abi == "n64")
564       flag |= ArchSpec::eMIPSABI_N64;
565     else if (elf_abi == "n32")
566       flag |= ArchSpec::eMIPSABI_N32;
567     else if (elf_abi == "o32")
568       flag |= ArchSpec::eMIPSABI_O32;
569   }
570   SetFlags(flag);
571 }
572 
GetClangTargetCPU() const573 std::string ArchSpec::GetClangTargetCPU() const {
574   std::string cpu;
575 
576   if (IsMIPS()) {
577     switch (m_core) {
578     case ArchSpec::eCore_mips32:
579     case ArchSpec::eCore_mips32el:
580       cpu = "mips32";
581       break;
582     case ArchSpec::eCore_mips32r2:
583     case ArchSpec::eCore_mips32r2el:
584       cpu = "mips32r2";
585       break;
586     case ArchSpec::eCore_mips32r3:
587     case ArchSpec::eCore_mips32r3el:
588       cpu = "mips32r3";
589       break;
590     case ArchSpec::eCore_mips32r5:
591     case ArchSpec::eCore_mips32r5el:
592       cpu = "mips32r5";
593       break;
594     case ArchSpec::eCore_mips32r6:
595     case ArchSpec::eCore_mips32r6el:
596       cpu = "mips32r6";
597       break;
598     case ArchSpec::eCore_mips64:
599     case ArchSpec::eCore_mips64el:
600       cpu = "mips64";
601       break;
602     case ArchSpec::eCore_mips64r2:
603     case ArchSpec::eCore_mips64r2el:
604       cpu = "mips64r2";
605       break;
606     case ArchSpec::eCore_mips64r3:
607     case ArchSpec::eCore_mips64r3el:
608       cpu = "mips64r3";
609       break;
610     case ArchSpec::eCore_mips64r5:
611     case ArchSpec::eCore_mips64r5el:
612       cpu = "mips64r5";
613       break;
614     case ArchSpec::eCore_mips64r6:
615     case ArchSpec::eCore_mips64r6el:
616       cpu = "mips64r6";
617       break;
618     default:
619       break;
620     }
621   }
622   return cpu;
623 }
624 
GetMachOCPUType() const625 uint32_t ArchSpec::GetMachOCPUType() const {
626   const CoreDefinition *core_def = FindCoreDefinition(m_core);
627   if (core_def) {
628     const ArchDefinitionEntry *arch_def =
629         FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
630     if (arch_def) {
631       return arch_def->cpu;
632     }
633   }
634   return LLDB_INVALID_CPUTYPE;
635 }
636 
GetMachOCPUSubType() const637 uint32_t ArchSpec::GetMachOCPUSubType() const {
638   const CoreDefinition *core_def = FindCoreDefinition(m_core);
639   if (core_def) {
640     const ArchDefinitionEntry *arch_def =
641         FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
642     if (arch_def) {
643       return arch_def->sub;
644     }
645   }
646   return LLDB_INVALID_CPUTYPE;
647 }
648 
GetDataByteSize() const649 uint32_t ArchSpec::GetDataByteSize() const {
650   return 1;
651 }
652 
GetCodeByteSize() const653 uint32_t ArchSpec::GetCodeByteSize() const {
654   return 1;
655 }
656 
GetMachine() const657 llvm::Triple::ArchType ArchSpec::GetMachine() const {
658   const CoreDefinition *core_def = FindCoreDefinition(m_core);
659   if (core_def)
660     return core_def->machine;
661 
662   return llvm::Triple::UnknownArch;
663 }
664 
GetDistributionId() const665 ConstString ArchSpec::GetDistributionId() const {
666   return m_distribution_id;
667 }
668 
SetDistributionId(const char * distribution_id)669 void ArchSpec::SetDistributionId(const char *distribution_id) {
670   m_distribution_id.SetCString(distribution_id);
671 }
672 
GetAddressByteSize() const673 uint32_t ArchSpec::GetAddressByteSize() const {
674   const CoreDefinition *core_def = FindCoreDefinition(m_core);
675   if (core_def) {
676     if (core_def->machine == llvm::Triple::mips64 ||
677         core_def->machine == llvm::Triple::mips64el) {
678       // For N32/O32 applications Address size is 4 bytes.
679       if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
680         return 4;
681     }
682     return core_def->addr_byte_size;
683   }
684   return 0;
685 }
686 
GetDefaultEndian() const687 ByteOrder ArchSpec::GetDefaultEndian() const {
688   const CoreDefinition *core_def = FindCoreDefinition(m_core);
689   if (core_def)
690     return core_def->default_byte_order;
691   return eByteOrderInvalid;
692 }
693 
CharIsSignedByDefault() const694 bool ArchSpec::CharIsSignedByDefault() const {
695   switch (m_triple.getArch()) {
696   default:
697     return true;
698 
699   case llvm::Triple::aarch64:
700   case llvm::Triple::aarch64_32:
701   case llvm::Triple::aarch64_be:
702   case llvm::Triple::arm:
703   case llvm::Triple::armeb:
704   case llvm::Triple::thumb:
705   case llvm::Triple::thumbeb:
706     return m_triple.isOSDarwin() || m_triple.isOSWindows();
707 
708   case llvm::Triple::ppc:
709   case llvm::Triple::ppc64:
710     return m_triple.isOSDarwin();
711 
712   case llvm::Triple::ppc64le:
713   case llvm::Triple::systemz:
714   case llvm::Triple::xcore:
715   case llvm::Triple::arc:
716     return false;
717   }
718 }
719 
GetByteOrder() const720 lldb::ByteOrder ArchSpec::GetByteOrder() const {
721   if (m_byte_order == eByteOrderInvalid)
722     return GetDefaultEndian();
723   return m_byte_order;
724 }
725 
726 //===----------------------------------------------------------------------===//
727 // Mutators.
728 
SetTriple(const llvm::Triple & triple)729 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
730   m_triple = triple;
731   UpdateCore();
732   return IsValid();
733 }
734 
ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,ArchSpec & arch)735 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
736                                                  ArchSpec &arch) {
737   // Accept "12-10" or "12.10" as cpu type/subtype
738   if (triple_str.empty())
739     return false;
740 
741   size_t pos = triple_str.find_first_of("-.");
742   if (pos == llvm::StringRef::npos)
743     return false;
744 
745   llvm::StringRef cpu_str = triple_str.substr(0, pos);
746   llvm::StringRef remainder = triple_str.substr(pos + 1);
747   if (cpu_str.empty() || remainder.empty())
748     return false;
749 
750   llvm::StringRef sub_str;
751   llvm::StringRef vendor;
752   llvm::StringRef os;
753   std::tie(sub_str, remainder) = remainder.split('-');
754   std::tie(vendor, os) = remainder.split('-');
755 
756   uint32_t cpu = 0;
757   uint32_t sub = 0;
758   if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
759     return false;
760 
761   if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
762     return false;
763   if (!vendor.empty() && !os.empty()) {
764     arch.GetTriple().setVendorName(vendor);
765     arch.GetTriple().setOSName(os);
766   }
767 
768   return true;
769 }
770 
SetTriple(llvm::StringRef triple)771 bool ArchSpec::SetTriple(llvm::StringRef triple) {
772   if (triple.empty()) {
773     Clear();
774     return false;
775   }
776 
777   if (ParseMachCPUDashSubtypeTriple(triple, *this))
778     return true;
779 
780   SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
781   return IsValid();
782 }
783 
ContainsOnlyArch(const llvm::Triple & normalized_triple)784 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
785   return !normalized_triple.getArchName().empty() &&
786          normalized_triple.getOSName().empty() &&
787          normalized_triple.getVendorName().empty() &&
788          normalized_triple.getEnvironmentName().empty();
789 }
790 
MergeFrom(const ArchSpec & other)791 void ArchSpec::MergeFrom(const ArchSpec &other) {
792   // ios-macabi always wins over macosx.
793   if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
794        GetTriple().getOS() == llvm::Triple::UnknownOS) &&
795       other.GetTriple().getOS() == llvm::Triple::IOS &&
796       other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
797     (*this) = other;
798     return;
799   }
800 
801   if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
802     GetTriple().setVendor(other.GetTriple().getVendor());
803   if (!TripleOSWasSpecified() && other.TripleOSWasSpecified())
804     GetTriple().setOS(other.GetTriple().getOS());
805   if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
806     GetTriple().setArch(other.GetTriple().getArch());
807 
808     // MachO unknown64 isn't really invalid as the debugger can still obtain
809     // information from the binary, e.g. line tables. As such, we don't update
810     // the core here.
811     if (other.GetCore() != eCore_uknownMach64)
812       UpdateCore();
813   }
814   if (!TripleEnvironmentWasSpecified() &&
815       other.TripleEnvironmentWasSpecified()) {
816     GetTriple().setEnvironment(other.GetTriple().getEnvironment());
817   }
818   // If this and other are both arm ArchSpecs and this ArchSpec is a generic
819   // "some kind of arm" spec but the other ArchSpec is a specific arm core,
820   // adopt the specific arm core.
821   if (GetTriple().getArch() == llvm::Triple::arm &&
822       other.GetTriple().getArch() == llvm::Triple::arm &&
823       IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
824       other.GetCore() != ArchSpec::eCore_arm_generic) {
825     m_core = other.GetCore();
826     CoreUpdated(false);
827   }
828   if (GetFlags() == 0) {
829     SetFlags(other.GetFlags());
830   }
831 }
832 
SetArchitecture(ArchitectureType arch_type,uint32_t cpu,uint32_t sub,uint32_t os)833 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
834                                uint32_t sub, uint32_t os) {
835   m_core = kCore_invalid;
836   bool update_triple = true;
837   const ArchDefinition *arch_def = FindArchDefinition(arch_type);
838   if (arch_def) {
839     const ArchDefinitionEntry *arch_def_entry =
840         FindArchDefinitionEntry(arch_def, cpu, sub);
841     if (arch_def_entry) {
842       const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
843       if (core_def) {
844         m_core = core_def->core;
845         update_triple = false;
846         // Always use the architecture name because it might be more
847         // descriptive than the architecture enum ("armv7" ->
848         // llvm::Triple::arm).
849         m_triple.setArchName(llvm::StringRef(core_def->name));
850         if (arch_type == eArchTypeMachO) {
851           m_triple.setVendor(llvm::Triple::Apple);
852 
853           // Don't set the OS.  It could be simulator, macosx, ios, watchos,
854           // tvos, bridgeos.  We could get close with the cpu type - but we
855           // can't get it right all of the time.  Better to leave this unset
856           // so other sections of code will set it when they have more
857           // information. NB: don't call m_triple.setOS
858           // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
859           // the ArchSpec::TripleVendorWasSpecified() method says that any
860           // OSName setting means it was specified.
861         } else if (arch_type == eArchTypeELF) {
862           switch (os) {
863           case llvm::ELF::ELFOSABI_AIX:
864             m_triple.setOS(llvm::Triple::OSType::AIX);
865             break;
866           case llvm::ELF::ELFOSABI_FREEBSD:
867             m_triple.setOS(llvm::Triple::OSType::FreeBSD);
868             break;
869           case llvm::ELF::ELFOSABI_GNU:
870             m_triple.setOS(llvm::Triple::OSType::Linux);
871             break;
872           case llvm::ELF::ELFOSABI_NETBSD:
873             m_triple.setOS(llvm::Triple::OSType::NetBSD);
874             break;
875           case llvm::ELF::ELFOSABI_OPENBSD:
876             m_triple.setOS(llvm::Triple::OSType::OpenBSD);
877             break;
878           case llvm::ELF::ELFOSABI_SOLARIS:
879             m_triple.setOS(llvm::Triple::OSType::Solaris);
880             break;
881           }
882         } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
883           m_triple.setVendor(llvm::Triple::PC);
884           m_triple.setOS(llvm::Triple::Win32);
885         } else {
886           m_triple.setVendor(llvm::Triple::UnknownVendor);
887           m_triple.setOS(llvm::Triple::UnknownOS);
888         }
889         // Fall back onto setting the machine type if the arch by name
890         // failed...
891         if (m_triple.getArch() == llvm::Triple::UnknownArch)
892           m_triple.setArch(core_def->machine);
893       }
894     } else {
895       Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM));
896       LLDB_LOGF(log,
897                 "Unable to find a core definition for cpu 0x%" PRIx32
898                 " sub %" PRId32,
899                 cpu, sub);
900     }
901   }
902   CoreUpdated(update_triple);
903   return IsValid();
904 }
905 
GetMinimumOpcodeByteSize() const906 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
907   const CoreDefinition *core_def = FindCoreDefinition(m_core);
908   if (core_def)
909     return core_def->min_opcode_byte_size;
910   return 0;
911 }
912 
GetMaximumOpcodeByteSize() const913 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
914   const CoreDefinition *core_def = FindCoreDefinition(m_core);
915   if (core_def)
916     return core_def->max_opcode_byte_size;
917   return 0;
918 }
919 
IsExactMatch(const ArchSpec & rhs) const920 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const {
921   return IsEqualTo(rhs, true);
922 }
923 
IsCompatibleMatch(const ArchSpec & rhs) const924 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const {
925   return IsEqualTo(rhs, false);
926 }
927 
IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,llvm::Triple::EnvironmentType rhs)928 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
929                                     llvm::Triple::EnvironmentType rhs) {
930   if (lhs == rhs)
931     return true;
932 
933   // Apple simulators are a different platform than what they simulate.
934   // As the environments are different at this point, if one of them is a
935   // simulator, then they are different.
936   if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
937     return false;
938 
939   // If any of the environment is unknown then they are compatible
940   if (lhs == llvm::Triple::UnknownEnvironment ||
941       rhs == llvm::Triple::UnknownEnvironment)
942     return true;
943 
944   // If one of the environment is Android and the other one is EABI then they
945   // are considered to be compatible. This is required as a workaround for
946   // shared libraries compiled for Android without the NOTE section indicating
947   // that they are using the Android ABI.
948   if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
949       (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
950       (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
951       (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
952       (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
953       (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
954     return true;
955 
956   return false;
957 }
958 
IsEqualTo(const ArchSpec & rhs,bool exact_match) const959 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const {
960   // explicitly ignoring m_distribution_id in this method.
961 
962   if (GetByteOrder() != rhs.GetByteOrder() ||
963       !cores_match(GetCore(), rhs.GetCore(), true, exact_match))
964     return false;
965 
966   const llvm::Triple &lhs_triple = GetTriple();
967   const llvm::Triple &rhs_triple = rhs.GetTriple();
968 
969   const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
970   const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
971   if (lhs_triple_vendor != rhs_triple_vendor) {
972     const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
973     const bool lhs_vendor_specified = TripleVendorWasSpecified();
974     // Both architectures had the vendor specified, so if they aren't equal
975     // then we return false
976     if (rhs_vendor_specified && lhs_vendor_specified)
977       return false;
978 
979     // Only fail if both vendor types are not unknown
980     if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
981         rhs_triple_vendor != llvm::Triple::UnknownVendor)
982       return false;
983   }
984 
985   const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
986   const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
987   const llvm::Triple::EnvironmentType lhs_triple_env =
988       lhs_triple.getEnvironment();
989   const llvm::Triple::EnvironmentType rhs_triple_env =
990       rhs_triple.getEnvironment();
991 
992   if (!exact_match) {
993     // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
994     if ((lhs_triple_os == llvm::Triple::IOS &&
995          lhs_triple_env == llvm::Triple::MacABI &&
996          rhs_triple_os == llvm::Triple::MacOSX) ||
997         (lhs_triple_os == llvm::Triple::MacOSX &&
998          rhs_triple_os == llvm::Triple::IOS &&
999          rhs_triple_env == llvm::Triple::MacABI))
1000       return true;
1001   }
1002 
1003   // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1004   if (lhs_triple_os == llvm::Triple::IOS &&
1005       rhs_triple_os == llvm::Triple::IOS &&
1006       (lhs_triple_env == llvm::Triple::MacABI ||
1007        rhs_triple_env == llvm::Triple::MacABI) &&
1008       lhs_triple_env != rhs_triple_env)
1009     return false;
1010 
1011   if (lhs_triple_os != rhs_triple_os) {
1012     const bool lhs_os_specified = TripleOSWasSpecified();
1013     const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1014     // If both OS types are specified and different, fail.
1015     if (lhs_os_specified && rhs_os_specified)
1016       return false;
1017 
1018     // If the pair of os+env is both unspecified, match any other os+env combo.
1019     if (!exact_match && ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1020                          (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1021       return true;
1022   }
1023 
1024   return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1025 }
1026 
UpdateCore()1027 void ArchSpec::UpdateCore() {
1028   llvm::StringRef arch_name(m_triple.getArchName());
1029   const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1030   if (core_def) {
1031     m_core = core_def->core;
1032     // Set the byte order to the default byte order for an architecture. This
1033     // can be modified if needed for cases when cores handle both big and
1034     // little endian
1035     m_byte_order = core_def->default_byte_order;
1036   } else {
1037     Clear();
1038   }
1039 }
1040 
1041 //===----------------------------------------------------------------------===//
1042 // Helper methods.
1043 
CoreUpdated(bool update_triple)1044 void ArchSpec::CoreUpdated(bool update_triple) {
1045   const CoreDefinition *core_def = FindCoreDefinition(m_core);
1046   if (core_def) {
1047     if (update_triple)
1048       m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1049     m_byte_order = core_def->default_byte_order;
1050   } else {
1051     if (update_triple)
1052       m_triple = llvm::Triple();
1053     m_byte_order = eByteOrderInvalid;
1054   }
1055 }
1056 
1057 //===----------------------------------------------------------------------===//
1058 // Operators.
1059 
cores_match(const ArchSpec::Core core1,const ArchSpec::Core core2,bool try_inverse,bool enforce_exact_match)1060 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1061                         bool try_inverse, bool enforce_exact_match) {
1062   if (core1 == core2)
1063     return true;
1064 
1065   switch (core1) {
1066   case ArchSpec::kCore_any:
1067     return true;
1068 
1069   case ArchSpec::eCore_arm_generic:
1070     if (enforce_exact_match)
1071       break;
1072     LLVM_FALLTHROUGH;
1073   case ArchSpec::kCore_arm_any:
1074     if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1075       return true;
1076     if (core2 >= ArchSpec::kCore_thumb_first &&
1077         core2 <= ArchSpec::kCore_thumb_last)
1078       return true;
1079     if (core2 == ArchSpec::kCore_arm_any)
1080       return true;
1081     break;
1082 
1083   case ArchSpec::kCore_x86_32_any:
1084     if ((core2 >= ArchSpec::kCore_x86_32_first &&
1085          core2 <= ArchSpec::kCore_x86_32_last) ||
1086         (core2 == ArchSpec::kCore_x86_32_any))
1087       return true;
1088     break;
1089 
1090   case ArchSpec::kCore_x86_64_any:
1091     if ((core2 >= ArchSpec::kCore_x86_64_first &&
1092          core2 <= ArchSpec::kCore_x86_64_last) ||
1093         (core2 == ArchSpec::kCore_x86_64_any))
1094       return true;
1095     break;
1096 
1097   case ArchSpec::kCore_ppc_any:
1098     if ((core2 >= ArchSpec::kCore_ppc_first &&
1099          core2 <= ArchSpec::kCore_ppc_last) ||
1100         (core2 == ArchSpec::kCore_ppc_any))
1101       return true;
1102     break;
1103 
1104   case ArchSpec::kCore_ppc64_any:
1105     if ((core2 >= ArchSpec::kCore_ppc64_first &&
1106          core2 <= ArchSpec::kCore_ppc64_last) ||
1107         (core2 == ArchSpec::kCore_ppc64_any))
1108       return true;
1109     break;
1110 
1111   case ArchSpec::eCore_arm_armv6m:
1112     if (!enforce_exact_match) {
1113       if (core2 == ArchSpec::eCore_arm_generic)
1114         return true;
1115       try_inverse = false;
1116       if (core2 == ArchSpec::eCore_arm_armv7)
1117         return true;
1118       if (core2 == ArchSpec::eCore_arm_armv6m)
1119         return true;
1120     }
1121     break;
1122 
1123   case ArchSpec::kCore_hexagon_any:
1124     if ((core2 >= ArchSpec::kCore_hexagon_first &&
1125          core2 <= ArchSpec::kCore_hexagon_last) ||
1126         (core2 == ArchSpec::kCore_hexagon_any))
1127       return true;
1128     break;
1129 
1130   // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1131   // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 -
1132   // ARMv7E-M - armv7em
1133   case ArchSpec::eCore_arm_armv7em:
1134     if (!enforce_exact_match) {
1135       if (core2 == ArchSpec::eCore_arm_generic)
1136         return true;
1137       if (core2 == ArchSpec::eCore_arm_armv7m)
1138         return true;
1139       if (core2 == ArchSpec::eCore_arm_armv6m)
1140         return true;
1141       if (core2 == ArchSpec::eCore_arm_armv7)
1142         return true;
1143       try_inverse = true;
1144     }
1145     break;
1146 
1147   // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1148   // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 -
1149   // ARMv7E-M - armv7em
1150   case ArchSpec::eCore_arm_armv7m:
1151     if (!enforce_exact_match) {
1152       if (core2 == ArchSpec::eCore_arm_generic)
1153         return true;
1154       if (core2 == ArchSpec::eCore_arm_armv6m)
1155         return true;
1156       if (core2 == ArchSpec::eCore_arm_armv7)
1157         return true;
1158       if (core2 == ArchSpec::eCore_arm_armv7em)
1159         return true;
1160       try_inverse = true;
1161     }
1162     break;
1163 
1164   case ArchSpec::eCore_arm_armv7f:
1165   case ArchSpec::eCore_arm_armv7k:
1166   case ArchSpec::eCore_arm_armv7s:
1167   case ArchSpec::eCore_arm_armv7l:
1168   case ArchSpec::eCore_arm_armv8l:
1169     if (!enforce_exact_match) {
1170       if (core2 == ArchSpec::eCore_arm_generic)
1171         return true;
1172       if (core2 == ArchSpec::eCore_arm_armv7)
1173         return true;
1174       try_inverse = false;
1175     }
1176     break;
1177 
1178   case ArchSpec::eCore_x86_64_x86_64h:
1179     if (!enforce_exact_match) {
1180       try_inverse = false;
1181       if (core2 == ArchSpec::eCore_x86_64_x86_64)
1182         return true;
1183     }
1184     break;
1185 
1186   case ArchSpec::eCore_arm_armv8:
1187     if (!enforce_exact_match) {
1188       if (core2 == ArchSpec::eCore_arm_arm64)
1189         return true;
1190       if (core2 == ArchSpec::eCore_arm_aarch64)
1191         return true;
1192       try_inverse = false;
1193     }
1194     break;
1195 
1196   case ArchSpec::eCore_arm_aarch64:
1197     if (!enforce_exact_match) {
1198       if (core2 == ArchSpec::eCore_arm_arm64)
1199         return true;
1200       if (core2 == ArchSpec::eCore_arm_armv8)
1201         return true;
1202       try_inverse = false;
1203     }
1204     break;
1205 
1206   case ArchSpec::eCore_arm_arm64:
1207     if (!enforce_exact_match) {
1208       if (core2 == ArchSpec::eCore_arm_aarch64)
1209         return true;
1210       if (core2 == ArchSpec::eCore_arm_armv8)
1211         return true;
1212       try_inverse = false;
1213     }
1214     break;
1215 
1216   case ArchSpec::eCore_arm_arm64_32:
1217     if (!enforce_exact_match) {
1218       if (core2 == ArchSpec::eCore_arm_generic)
1219         return true;
1220       try_inverse = false;
1221     }
1222     break;
1223 
1224   case ArchSpec::eCore_mips32:
1225     if (!enforce_exact_match) {
1226       if (core2 >= ArchSpec::kCore_mips32_first &&
1227           core2 <= ArchSpec::kCore_mips32_last)
1228         return true;
1229       try_inverse = false;
1230     }
1231     break;
1232 
1233   case ArchSpec::eCore_mips32el:
1234     if (!enforce_exact_match) {
1235       if (core2 >= ArchSpec::kCore_mips32el_first &&
1236           core2 <= ArchSpec::kCore_mips32el_last)
1237         return true;
1238       try_inverse = true;
1239     }
1240     break;
1241 
1242   case ArchSpec::eCore_mips64:
1243     if (!enforce_exact_match) {
1244       if (core2 >= ArchSpec::kCore_mips32_first &&
1245           core2 <= ArchSpec::kCore_mips32_last)
1246         return true;
1247       if (core2 >= ArchSpec::kCore_mips64_first &&
1248           core2 <= ArchSpec::kCore_mips64_last)
1249         return true;
1250       try_inverse = false;
1251     }
1252     break;
1253 
1254   case ArchSpec::eCore_mips64el:
1255     if (!enforce_exact_match) {
1256       if (core2 >= ArchSpec::kCore_mips32el_first &&
1257           core2 <= ArchSpec::kCore_mips32el_last)
1258         return true;
1259       if (core2 >= ArchSpec::kCore_mips64el_first &&
1260           core2 <= ArchSpec::kCore_mips64el_last)
1261         return true;
1262       try_inverse = false;
1263     }
1264     break;
1265 
1266   case ArchSpec::eCore_mips64r2:
1267   case ArchSpec::eCore_mips64r3:
1268   case ArchSpec::eCore_mips64r5:
1269     if (!enforce_exact_match) {
1270       if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1271         return true;
1272       if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1273         return true;
1274       try_inverse = false;
1275     }
1276     break;
1277 
1278   case ArchSpec::eCore_mips64r2el:
1279   case ArchSpec::eCore_mips64r3el:
1280   case ArchSpec::eCore_mips64r5el:
1281     if (!enforce_exact_match) {
1282       if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1283         return true;
1284       if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1285         return true;
1286       try_inverse = false;
1287     }
1288     break;
1289 
1290   case ArchSpec::eCore_mips32r2:
1291   case ArchSpec::eCore_mips32r3:
1292   case ArchSpec::eCore_mips32r5:
1293     if (!enforce_exact_match) {
1294       if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1295         return true;
1296     }
1297     break;
1298 
1299   case ArchSpec::eCore_mips32r2el:
1300   case ArchSpec::eCore_mips32r3el:
1301   case ArchSpec::eCore_mips32r5el:
1302     if (!enforce_exact_match) {
1303       if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1304         return true;
1305     }
1306     break;
1307 
1308   case ArchSpec::eCore_mips32r6:
1309     if (!enforce_exact_match) {
1310       if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1311         return true;
1312     }
1313     break;
1314 
1315   case ArchSpec::eCore_mips32r6el:
1316     if (!enforce_exact_match) {
1317       if (core2 == ArchSpec::eCore_mips32el ||
1318           core2 == ArchSpec::eCore_mips32r6el)
1319         return true;
1320     }
1321     break;
1322 
1323   case ArchSpec::eCore_mips64r6:
1324     if (!enforce_exact_match) {
1325       if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1326         return true;
1327       if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1328         return true;
1329     }
1330     break;
1331 
1332   case ArchSpec::eCore_mips64r6el:
1333     if (!enforce_exact_match) {
1334       if (core2 == ArchSpec::eCore_mips32el ||
1335           core2 == ArchSpec::eCore_mips32r6el)
1336         return true;
1337       if (core2 == ArchSpec::eCore_mips64el ||
1338           core2 == ArchSpec::eCore_mips64r6el)
1339         return true;
1340     }
1341     break;
1342 
1343   default:
1344     break;
1345   }
1346   if (try_inverse)
1347     return cores_match(core2, core1, false, enforce_exact_match);
1348   return false;
1349 }
1350 
operator <(const ArchSpec & lhs,const ArchSpec & rhs)1351 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1352   const ArchSpec::Core lhs_core = lhs.GetCore();
1353   const ArchSpec::Core rhs_core = rhs.GetCore();
1354   return lhs_core < rhs_core;
1355 }
1356 
1357 
operator ==(const ArchSpec & lhs,const ArchSpec & rhs)1358 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1359   return lhs.GetCore() == rhs.GetCore();
1360 }
1361 
IsFullySpecifiedTriple() const1362 bool ArchSpec::IsFullySpecifiedTriple() const {
1363   const auto &user_specified_triple = GetTriple();
1364 
1365   bool user_triple_fully_specified = false;
1366 
1367   if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) ||
1368       TripleOSWasSpecified()) {
1369     if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) ||
1370         TripleVendorWasSpecified()) {
1371       const unsigned unspecified = 0;
1372       if (!user_specified_triple.isOSDarwin() ||
1373           user_specified_triple.getOSMajorVersion() != unspecified) {
1374         user_triple_fully_specified = true;
1375       }
1376     }
1377   }
1378 
1379   return user_triple_fully_specified;
1380 }
1381 
PiecewiseTripleCompare(const ArchSpec & other,bool & arch_different,bool & vendor_different,bool & os_different,bool & os_version_different,bool & env_different) const1382 void ArchSpec::PiecewiseTripleCompare(
1383     const ArchSpec &other, bool &arch_different, bool &vendor_different,
1384     bool &os_different, bool &os_version_different, bool &env_different) const {
1385   const llvm::Triple &me(GetTriple());
1386   const llvm::Triple &them(other.GetTriple());
1387 
1388   arch_different = (me.getArch() != them.getArch());
1389 
1390   vendor_different = (me.getVendor() != them.getVendor());
1391 
1392   os_different = (me.getOS() != them.getOS());
1393 
1394   os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
1395 
1396   env_different = (me.getEnvironment() != them.getEnvironment());
1397 }
1398 
IsAlwaysThumbInstructions() const1399 bool ArchSpec::IsAlwaysThumbInstructions() const {
1400   std::string Status;
1401   if (GetTriple().getArch() == llvm::Triple::arm ||
1402       GetTriple().getArch() == llvm::Triple::thumb) {
1403     // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1404     //
1405     // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1406     // execute thumb instructions.  We map the cores to arch names like this:
1407     //
1408     // Cortex-M0, Cortex-M0+, Cortex-M1:  armv6m Cortex-M3: armv7m Cortex-M4,
1409     // Cortex-M7: armv7em
1410 
1411     if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1412         GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1413         GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1414         GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1415         GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1416         GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1417       return true;
1418     }
1419     // Windows on ARM is always thumb.
1420     if (GetTriple().isOSWindows())
1421       return true;
1422   }
1423   return false;
1424 }
1425 
DumpTriple(llvm::raw_ostream & s) const1426 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1427   const llvm::Triple &triple = GetTriple();
1428   llvm::StringRef arch_str = triple.getArchName();
1429   llvm::StringRef vendor_str = triple.getVendorName();
1430   llvm::StringRef os_str = triple.getOSName();
1431   llvm::StringRef environ_str = triple.getEnvironmentName();
1432 
1433   s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
1434                      vendor_str.empty() ? "*" : vendor_str,
1435                      os_str.empty() ? "*" : os_str);
1436 
1437   if (!environ_str.empty())
1438     s << "-" << environ_str;
1439 }
1440 
output(const ArchSpec & Val,void *,raw_ostream & Out)1441 void llvm::yaml::ScalarTraits<ArchSpec>::output(const ArchSpec &Val, void *,
1442                                                 raw_ostream &Out) {
1443   Val.DumpTriple(Out);
1444 }
1445 
1446 llvm::StringRef
input(llvm::StringRef Scalar,void *,ArchSpec & Val)1447 llvm::yaml::ScalarTraits<ArchSpec>::input(llvm::StringRef Scalar, void *,
1448                                           ArchSpec &Val) {
1449   Val = ArchSpec(Scalar);
1450   return {};
1451 }
1452