1 /*
2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <bl32/sp_min/platform_sp_min.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <drivers/console.h>
15 #include <lib/mmio.h>
16 #include <plat/arm/common/plat_arm.h>
17 #include <plat/common/platform.h>
18
19 static entry_point_info_t bl33_image_ep_info;
20
21 /* Weak definitions may be overridden in specific ARM standard platform */
22 #pragma weak sp_min_platform_setup
23 #pragma weak sp_min_plat_arch_setup
24 #pragma weak plat_arm_sp_min_early_platform_setup
25
26 #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \
27 BL32_BASE, \
28 BL32_END - BL32_BASE, \
29 MT_MEMORY | MT_RW | MT_SECURE)
30
31 /*
32 * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
33 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
34 */
35 CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
36
37 /*******************************************************************************
38 * Return a pointer to the 'entry_point_info' structure of the next image for the
39 * security state specified. BL33 corresponds to the non-secure image type
40 * while BL32 corresponds to the secure image type. A NULL pointer is returned
41 * if the image does not exist.
42 ******************************************************************************/
sp_min_plat_get_bl33_ep_info(void)43 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
44 {
45 entry_point_info_t *next_image_info;
46
47 next_image_info = &bl33_image_ep_info;
48
49 /*
50 * None of the images on the ARM development platforms can have 0x0
51 * as the entrypoint
52 */
53 if (next_image_info->pc)
54 return next_image_info;
55 else
56 return NULL;
57 }
58
59 /*******************************************************************************
60 * Utility function to perform early platform setup.
61 ******************************************************************************/
arm_sp_min_early_platform_setup(void * from_bl2,uintptr_t tos_fw_config,uintptr_t hw_config,void * plat_params_from_bl2)62 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
63 uintptr_t hw_config, void *plat_params_from_bl2)
64 {
65 /* Initialize the console to provide early debug support */
66 arm_console_boot_init();
67
68 #if RESET_TO_SP_MIN
69 /* There are no parameters from BL2 if SP_MIN is a reset vector */
70 assert(from_bl2 == NULL);
71 assert(plat_params_from_bl2 == NULL);
72
73 /* Populate entry point information for BL33 */
74 SET_PARAM_HEAD(&bl33_image_ep_info,
75 PARAM_EP,
76 VERSION_1,
77 0);
78 /*
79 * Tell SP_MIN where the non-trusted software image
80 * is located and the entry state information
81 */
82 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
83 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
84 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
85
86 # if ARM_LINUX_KERNEL_AS_BL33
87 /*
88 * According to the file ``Documentation/arm/Booting`` of the Linux
89 * kernel tree, Linux expects:
90 * r0 = 0
91 * r1 = machine type number, optional in DT-only platforms (~0 if so)
92 * r2 = Physical address of the device tree blob
93 */
94 bl33_image_ep_info.args.arg0 = 0U;
95 bl33_image_ep_info.args.arg1 = ~0U;
96 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE;
97 # endif
98
99 #else /* RESET_TO_SP_MIN */
100
101 /*
102 * Check params passed from BL2 should not be NULL,
103 */
104 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
105 assert(params_from_bl2 != NULL);
106 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
107 assert(params_from_bl2->h.version >= VERSION_2);
108
109 bl_params_node_t *bl_params = params_from_bl2->head;
110
111 /*
112 * Copy BL33 entry point information.
113 * They are stored in Secure RAM, in BL2's address space.
114 */
115 while (bl_params) {
116 if (bl_params->image_id == BL33_IMAGE_ID) {
117 bl33_image_ep_info = *bl_params->ep_info;
118 break;
119 }
120
121 bl_params = bl_params->next_params_info;
122 }
123
124 if (bl33_image_ep_info.pc == 0)
125 panic();
126
127 #endif /* RESET_TO_SP_MIN */
128
129 }
130
131 /*******************************************************************************
132 * Default implementation for sp_min_platform_setup2() for ARM platforms
133 ******************************************************************************/
plat_arm_sp_min_early_platform_setup(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)134 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
135 u_register_t arg2, u_register_t arg3)
136 {
137 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
138
139 /*
140 * Initialize Interconnect for this cluster during cold boot.
141 * No need for locks as no other CPU is active.
142 */
143 plat_arm_interconnect_init();
144
145 /*
146 * Enable Interconnect coherency for the primary CPU's cluster.
147 * Earlier bootloader stages might already do this (e.g. Trusted
148 * Firmware's BL1 does it) but we can't assume so. There is no harm in
149 * executing this code twice anyway.
150 * Platform specific PSCI code will enable coherency for other
151 * clusters.
152 */
153 plat_arm_interconnect_enter_coherency();
154 }
155
sp_min_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)156 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
157 u_register_t arg2, u_register_t arg3)
158 {
159 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
160 }
161
162 /*******************************************************************************
163 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit.
164 * Common to ARM standard platforms.
165 ******************************************************************************/
arm_sp_min_plat_runtime_setup(void)166 void arm_sp_min_plat_runtime_setup(void)
167 {
168 /* Initialize the runtime console */
169 arm_console_runtime_init();
170
171 #if PLAT_RO_XLAT_TABLES
172 arm_xlat_make_tables_readonly();
173 #endif
174 }
175
176 /*******************************************************************************
177 * Perform platform specific setup for SP_MIN
178 ******************************************************************************/
sp_min_platform_setup(void)179 void sp_min_platform_setup(void)
180 {
181 /* Initialize the GIC driver, cpu and distributor interfaces */
182 plat_arm_gic_driver_init();
183 plat_arm_gic_init();
184
185 /*
186 * Do initial security configuration to allow DRAM/device access
187 * (if earlier BL has not already done so).
188 */
189 #if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
190 plat_arm_security_setup();
191
192 #if defined(PLAT_ARM_MEM_PROT_ADDR)
193 arm_nor_psci_do_dyn_mem_protect();
194 #endif /* PLAT_ARM_MEM_PROT_ADDR */
195
196 #endif
197
198 /* Enable and initialize the System level generic timer */
199 #ifdef ARM_SYS_CNTCTL_BASE
200 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
201 CNTCR_FCREQ(0U) | CNTCR_EN);
202 #endif
203 #ifdef ARM_SYS_TIMCTL_BASE
204 /* Allow access to the System counter timer module */
205 arm_configure_sys_timer();
206 #endif
207 /* Initialize power controller before setting up topology */
208 plat_arm_pwrc_setup();
209 }
210
sp_min_plat_runtime_setup(void)211 void sp_min_plat_runtime_setup(void)
212 {
213 arm_sp_min_plat_runtime_setup();
214 }
215
216 /*******************************************************************************
217 * Perform the very early platform specific architectural setup here. At the
218 * moment this only initializes the MMU
219 ******************************************************************************/
arm_sp_min_plat_arch_setup(void)220 void arm_sp_min_plat_arch_setup(void)
221 {
222 const mmap_region_t bl_regions[] = {
223 MAP_BL_SP_MIN_TOTAL,
224 ARM_MAP_BL_RO,
225 #if USE_COHERENT_MEM
226 ARM_MAP_BL_COHERENT_RAM,
227 #endif
228 {0}
229 };
230
231 setup_page_tables(bl_regions, plat_arm_get_mmap());
232
233 enable_mmu_svc_mon(0);
234 }
235
sp_min_plat_arch_setup(void)236 void sp_min_plat_arch_setup(void)
237 {
238 arm_sp_min_plat_arch_setup();
239 }
240