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1 /*
2  * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <platform_def.h>
10 
11 #include <arch_helpers.h>
12 #include <lib/psci/psci.h>
13 #include <plat/arm/common/plat_arm.h>
14 #include <plat/common/platform.h>
15 
16 /* Allow ARM Standard platforms to override these functions */
17 #pragma weak plat_arm_program_trusted_mailbox
18 
19 #if !ARM_RECOM_STATE_ID_ENC
20 /*******************************************************************************
21  * ARM standard platform handler called to check the validity of the power state
22  * parameter.
23  ******************************************************************************/
arm_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)24 int arm_validate_power_state(unsigned int power_state,
25 			    psci_power_state_t *req_state)
26 {
27 	unsigned int pstate = psci_get_pstate_type(power_state);
28 	unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
29 	unsigned int i;
30 
31 	assert(req_state != NULL);
32 
33 	if (pwr_lvl > PLAT_MAX_PWR_LVL)
34 		return PSCI_E_INVALID_PARAMS;
35 
36 	/* Sanity check the requested state */
37 	if (pstate == PSTATE_TYPE_STANDBY) {
38 		/*
39 		 * It's possible to enter standby only on power level 0
40 		 * Ignore any other power level.
41 		 */
42 		if (pwr_lvl != ARM_PWR_LVL0)
43 			return PSCI_E_INVALID_PARAMS;
44 
45 		req_state->pwr_domain_state[ARM_PWR_LVL0] =
46 					ARM_LOCAL_STATE_RET;
47 	} else {
48 		for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++)
49 			req_state->pwr_domain_state[i] =
50 					ARM_LOCAL_STATE_OFF;
51 	}
52 
53 	/*
54 	 * We expect the 'state id' to be zero.
55 	 */
56 	if (psci_get_pstate_id(power_state) != 0U)
57 		return PSCI_E_INVALID_PARAMS;
58 
59 	return PSCI_E_SUCCESS;
60 }
61 
62 #else
63 /*******************************************************************************
64  * ARM standard platform handler called to check the validity of the power
65  * state parameter. The power state parameter has to be a composite power
66  * state.
67  ******************************************************************************/
arm_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)68 int arm_validate_power_state(unsigned int power_state,
69 				psci_power_state_t *req_state)
70 {
71 	unsigned int state_id;
72 	int i;
73 
74 	assert(req_state != NULL);
75 
76 	/*
77 	 *  Currently we are using a linear search for finding the matching
78 	 *  entry in the idle power state array. This can be made a binary
79 	 *  search if the number of entries justify the additional complexity.
80 	 */
81 	for (i = 0; !!arm_pm_idle_states[i]; i++) {
82 		if (power_state == arm_pm_idle_states[i])
83 			break;
84 	}
85 
86 	/* Return error if entry not found in the idle state array */
87 	if (!arm_pm_idle_states[i])
88 		return PSCI_E_INVALID_PARAMS;
89 
90 	i = 0;
91 	state_id = psci_get_pstate_id(power_state);
92 
93 	/* Parse the State ID and populate the state info parameter */
94 	while (state_id) {
95 		req_state->pwr_domain_state[i++] = state_id &
96 						ARM_LOCAL_PSTATE_MASK;
97 		state_id >>= ARM_LOCAL_PSTATE_WIDTH;
98 	}
99 
100 	return PSCI_E_SUCCESS;
101 }
102 #endif /* __ARM_RECOM_STATE_ID_ENC__ */
103 
104 /*******************************************************************************
105  * ARM standard platform handler called to check the validity of the non secure
106  * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise.
107  ******************************************************************************/
arm_validate_ns_entrypoint(uintptr_t entrypoint)108 int arm_validate_ns_entrypoint(uintptr_t entrypoint)
109 {
110 	/*
111 	 * Check if the non secure entrypoint lies within the non
112 	 * secure DRAM.
113 	 */
114 	if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint <
115 			(ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
116 		return 0;
117 	}
118 #ifdef __aarch64__
119 	if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
120 			(ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
121 		return 0;
122 	}
123 #endif
124 
125 	return -1;
126 }
127 
arm_validate_psci_entrypoint(uintptr_t entrypoint)128 int arm_validate_psci_entrypoint(uintptr_t entrypoint)
129 {
130 	return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS :
131 		PSCI_E_INVALID_ADDRESS;
132 }
133 
134 /******************************************************************************
135  * Helper function to save the platform state before a system suspend. Save the
136  * state of the system components which are not in the Always ON power domain.
137  *****************************************************************************/
arm_system_pwr_domain_save(void)138 void arm_system_pwr_domain_save(void)
139 {
140 	/* Assert system power domain is available on the platform */
141 	assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
142 
143 	plat_arm_gic_save();
144 
145 	/*
146 	 * Unregister console now so that it is not registered for a second
147 	 * time during resume.
148 	 */
149 	arm_console_runtime_end();
150 
151 	/*
152 	 * All the other peripheral which are configured by ARM TF are
153 	 * re-initialized on resume from system suspend. Hence we
154 	 * don't save their state here.
155 	 */
156 }
157 
158 /******************************************************************************
159  * Helper function to resume the platform from system suspend. Reinitialize
160  * the system components which are not in the Always ON power domain.
161  * TODO: Unify the platform setup when waking up from cold boot and system
162  * resume in arm_bl31_platform_setup().
163  *****************************************************************************/
arm_system_pwr_domain_resume(void)164 void arm_system_pwr_domain_resume(void)
165 {
166 	/* Initialize the console */
167 	arm_console_runtime_init();
168 
169 	/* Assert system power domain is available on the platform */
170 	assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
171 
172 	plat_arm_gic_resume();
173 
174 	plat_arm_security_setup();
175 	arm_configure_sys_timer();
176 }
177 
178 /*******************************************************************************
179  * ARM platform function to program the mailbox for a cpu before it is released
180  * from reset. This function assumes that the Trusted mail box base is within
181  * the ARM_SHARED_RAM region
182  ******************************************************************************/
plat_arm_program_trusted_mailbox(uintptr_t address)183 void plat_arm_program_trusted_mailbox(uintptr_t address)
184 {
185 	uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE;
186 
187 	*mailbox = address;
188 
189 	/*
190 	 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within
191 	 * ARM_SHARED_RAM region.
192 	 */
193 	assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) &&
194 		((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \
195 				(ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)));
196 }
197 
198 /*******************************************************************************
199  * The ARM Standard platform definition of platform porting API
200  * `plat_setup_psci_ops`.
201  ******************************************************************************/
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)202 int __init plat_setup_psci_ops(uintptr_t sec_entrypoint,
203 				const plat_psci_ops_t **psci_ops)
204 {
205 	*psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops);
206 
207 	/* Setup mailbox with entry point. */
208 	plat_arm_program_trusted_mailbox(sec_entrypoint);
209 	return 0;
210 }
211