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1 // Copyright 2017 Google LLC
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 //    http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #ifndef CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
16 #define CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
17 
18 #include "cpu_features_cache_info.h"
19 #include "cpu_features_macros.h"
20 
21 CPU_FEATURES_START_CPP_NAMESPACE
22 
23 typedef struct {
24   int fp : 1;          // Floating-point.
25   int asimd : 1;       // Advanced SIMD.
26   int evtstrm : 1;     // Generic timer generated events.
27   int aes : 1;         // Hardware-accelerated Advanced Encryption Standard.
28   int pmull : 1;       // Polynomial multiply long.
29   int sha1 : 1;        // Hardware-accelerated SHA1.
30   int sha2 : 1;        // Hardware-accelerated SHA2-256.
31   int crc32 : 1;       // Hardware-accelerated CRC-32.
32   int atomics : 1;     // Armv8.1 atomic instructions.
33   int fphp : 1;        // Half-precision floating point support.
34   int asimdhp : 1;     // Advanced SIMD half-precision support.
35   int cpuid : 1;       // Access to certain ID registers.
36   int asimdrdm : 1;    // Rounding Double Multiply Accumulate/Subtract.
37   int jscvt : 1;       // Support for JavaScript conversion.
38   int fcma : 1;        // Floating point complex numbers.
39   int lrcpc : 1;       // Support for weaker release consistency.
40   int dcpop : 1;       // Data persistence writeback.
41   int sha3 : 1;        // Hardware-accelerated SHA3.
42   int sm3 : 1;         // Hardware-accelerated SM3.
43   int sm4 : 1;         // Hardware-accelerated SM4.
44   int asimddp : 1;     // Dot product instruction.
45   int sha512 : 1;      // Hardware-accelerated SHA512.
46   int sve : 1;         // Scalable Vector Extension.
47   int asimdfhm : 1;    // Additional half-precision instructions.
48   int dit : 1;         // Data independent timing.
49   int uscat : 1;       // Unaligned atomics support.
50   int ilrcpc : 1;      // Additional support for weaker release consistency.
51   int flagm : 1;       // Flag manipulation instructions.
52   int ssbs : 1;        // Speculative Store Bypass Safe PSTATE bit.
53   int sb : 1;          // Speculation barrier.
54   int paca : 1;        // Address authentication.
55   int pacg : 1;        // Generic authentication.
56   int dcpodp : 1;      // Data cache clean to point of persistence.
57   int sve2 : 1;        // Scalable Vector Extension (version 2).
58   int sveaes : 1;      // SVE AES instructions.
59   int svepmull : 1;    // SVE polynomial multiply long instructions.
60   int svebitperm : 1;  // SVE bit permute instructions.
61   int svesha3 : 1;     // SVE SHA3 instructions.
62   int svesm4 : 1;      // SVE SM4 instructions.
63   int flagm2 : 1;      // Additional flag manipulation instructions.
64   int frint : 1;       // Floating point to integer rounding.
65   int svei8mm : 1;     // SVE Int8 matrix multiplication instructions.
66   int svef32mm : 1;    // SVE FP32 matrix multiplication instruction.
67   int svef64mm : 1;    // SVE FP64 matrix multiplication instructions.
68   int svebf16 : 1;     // SVE BFloat16 instructions.
69   int i8mm : 1;        // Int8 matrix multiplication instructions.
70   int bf16 : 1;        // BFloat16 instructions.
71   int dgh : 1;         // Data Gathering Hint instruction.
72   int rng : 1;         // True random number generator support.
73   int bti : 1;         // Branch target identification.
74 
75   // Make sure to update Aarch64FeaturesEnum below if you add a field here.
76 } Aarch64Features;
77 
78 typedef struct {
79   Aarch64Features features;
80   int implementer;
81   int variant;
82   int part;
83   int revision;
84 } Aarch64Info;
85 
86 Aarch64Info GetAarch64Info(void);
87 
88 ////////////////////////////////////////////////////////////////////////////////
89 // Introspection functions
90 
91 typedef enum {
92   AARCH64_FP,
93   AARCH64_ASIMD,
94   AARCH64_EVTSTRM,
95   AARCH64_AES,
96   AARCH64_PMULL,
97   AARCH64_SHA1,
98   AARCH64_SHA2,
99   AARCH64_CRC32,
100   AARCH64_ATOMICS,
101   AARCH64_FPHP,
102   AARCH64_ASIMDHP,
103   AARCH64_CPUID,
104   AARCH64_ASIMDRDM,
105   AARCH64_JSCVT,
106   AARCH64_FCMA,
107   AARCH64_LRCPC,
108   AARCH64_DCPOP,
109   AARCH64_SHA3,
110   AARCH64_SM3,
111   AARCH64_SM4,
112   AARCH64_ASIMDDP,
113   AARCH64_SHA512,
114   AARCH64_SVE,
115   AARCH64_ASIMDFHM,
116   AARCH64_DIT,
117   AARCH64_USCAT,
118   AARCH64_ILRCPC,
119   AARCH64_FLAGM,
120   AARCH64_SSBS,
121   AARCH64_SB,
122   AARCH64_PACA,
123   AARCH64_PACG,
124   AARCH64_DCPODP,
125   AARCH64_SVE2,
126   AARCH64_SVEAES,
127   AARCH64_SVEPMULL,
128   AARCH64_SVEBITPERM,
129   AARCH64_SVESHA3,
130   AARCH64_SVESM4,
131   AARCH64_FLAGM2,
132   AARCH64_FRINT,
133   AARCH64_SVEI8MM,
134   AARCH64_SVEF32MM,
135   AARCH64_SVEF64MM,
136   AARCH64_SVEBF16,
137   AARCH64_I8MM,
138   AARCH64_BF16,
139   AARCH64_DGH,
140   AARCH64_RNG,
141   AARCH64_BTI,
142   AARCH64_LAST_,
143 } Aarch64FeaturesEnum;
144 
145 int GetAarch64FeaturesEnumValue(const Aarch64Features* features,
146                                 Aarch64FeaturesEnum value);
147 
148 const char* GetAarch64FeaturesEnumName(Aarch64FeaturesEnum);
149 
150 CPU_FEATURES_END_CPP_NAMESPACE
151 
152 #if !defined(CPU_FEATURES_ARCH_AARCH64)
153 #error "Including cpuinfo_aarch64.h from a non-aarch64 target."
154 #endif
155 
156 #endif  // CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
157