1 /*
2 * \file trc_pkt_elem_etmv4i.cpp
3 * \brief OpenCSD :
4 *
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
6 */
7
8 /*
9 * Redistribution and use in source and binary forms, with or without modification,
10 * are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3. Neither the name of the copyright holder nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34 #include <sstream>
35 #include <iomanip>
36
37 #include "opencsd/etmv4/trc_pkt_elem_etmv4i.h"
38
EtmV4ITrcPacket()39 EtmV4ITrcPacket::EtmV4ITrcPacket()
40 {
41 protocol_version = 0x42; // min protocol version.
42 }
43
~EtmV4ITrcPacket()44 EtmV4ITrcPacket::~EtmV4ITrcPacket()
45 {
46 }
47
initStartState()48 void EtmV4ITrcPacket::initStartState()
49 {
50 // clear packet state to start of trace (first sync or post discontinuity)
51
52 // clear all valid bits
53 pkt_valid.val = 0;
54
55 // virtual address
56 v_addr.pkt_bits = 0;
57 v_addr.valid_bits = 0;
58 v_addr_ISA = 0;
59
60 // timestamp
61 ts.bits_changed = 0;
62 ts.timestamp = 0;
63
64 // per packet init
65 initNextPacket();
66 }
67
initNextPacket()68 void EtmV4ITrcPacket::initNextPacket()
69 {
70 // clear valid bits for elements that are only valid over a single packet.
71 pkt_valid.bits.cc_valid = 0;
72 pkt_valid.bits.commit_elem_valid = 0;
73 atom.num = 0;
74 context.updated = 0;
75 context.updated_v = 0;
76 context.updated_c = 0;
77 err_type = ETM4_PKT_I_NO_ERR_TYPE;
78 }
79
80 // printing
toString(std::string & str) const81 void EtmV4ITrcPacket::toString(std::string &str) const
82 {
83 const char *name;
84 const char *desc;
85 std::string valStr, ctxtStr = "";
86
87 name = packetTypeName(type, &desc);
88 str = name + (std::string)" : " + desc;
89
90 // extended descriptions
91 switch (type)
92 {
93 case ETM4_PKT_I_BAD_SEQUENCE:
94 case ETM4_PKT_I_INCOMPLETE_EOT:
95 case ETM4_PKT_I_RESERVED_CFG:
96 name = packetTypeName(err_type, 0);
97 str += "[" + (std::string)name + "]";
98 break;
99
100 case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
101 case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
102 contextStr(ctxtStr);
103 case ETM4_PKT_I_ADDR_L_32IS0:
104 case ETM4_PKT_I_ADDR_L_32IS1:
105 case ETE_PKT_I_SRC_ADDR_L_32IS0:
106 case ETE_PKT_I_SRC_ADDR_L_32IS1:
107 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 32) ? v_addr.pkt_bits : 0);
108 str += "; Addr=" + valStr + "; " + ctxtStr;
109 break;
110
111 case ETM4_PKT_I_ADDR_CTXT_L_64IS0:
112 case ETM4_PKT_I_ADDR_CTXT_L_64IS1:
113 contextStr(ctxtStr);
114 case ETM4_PKT_I_ADDR_L_64IS0:
115 case ETM4_PKT_I_ADDR_L_64IS1:
116 case ETE_PKT_I_SRC_ADDR_L_64IS0:
117 case ETE_PKT_I_SRC_ADDR_L_64IS1:
118 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 64) ? v_addr.pkt_bits : 0);
119 str += "; Addr=" + valStr + "; " + ctxtStr;
120 break;
121
122 case ETM4_PKT_I_CTXT:
123 contextStr(ctxtStr);
124 str += "; " + ctxtStr;
125 break;
126
127 case ETM4_PKT_I_ADDR_S_IS0:
128 case ETM4_PKT_I_ADDR_S_IS1:
129 case ETE_PKT_I_SRC_ADDR_S_IS0:
130 case ETE_PKT_I_SRC_ADDR_S_IS1:
131 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, v_addr.pkt_bits);
132 str += "; Addr=" + valStr;
133 break;
134
135 case ETM4_PKT_I_ADDR_MATCH:
136 case ETE_PKT_I_SRC_ADDR_MATCH:
137 addrMatchIdx(valStr);
138 str += ", " + valStr;
139 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true);
140 str += "; Addr=" + valStr + "; " + ctxtStr;
141 break;
142
143 case ETM4_PKT_I_ATOM_F1:
144 case ETM4_PKT_I_ATOM_F2:
145 case ETM4_PKT_I_ATOM_F3:
146 case ETM4_PKT_I_ATOM_F4:
147 case ETM4_PKT_I_ATOM_F5:
148 case ETM4_PKT_I_ATOM_F6:
149 atomSeq(valStr);
150 str += "; " + valStr;
151 break;
152
153 case ETM4_PKT_I_EXCEPT:
154 exceptionInfo(valStr);
155 str += "; " + valStr;
156 break;
157
158 case ETM4_PKT_I_TIMESTAMP:
159 {
160 std::ostringstream oss;
161 oss << "; Updated val = " << std::hex << "0x" << ts.timestamp;
162 if (pkt_valid.bits.cc_valid)
163 oss << "; CC=" << std::hex << "0x" << cycle_count;
164 str += oss.str();
165 }
166 break;
167
168 case ETM4_PKT_I_TRACE_INFO:
169 {
170 std::ostringstream oss;
171 oss << "; INFO=" << std::hex << "0x" << trace_info.val;
172 oss << " { CC." << std::dec << trace_info.bits.cc_enabled;
173 if (isETE())
174 oss << ", TSTATE." << std::dec << trace_info.bits.in_trans_state;
175 oss << " }";
176 if (trace_info.bits.cc_enabled)
177 oss << "; CC_THRESHOLD=" << std::hex << "0x" << cc_threshold;
178 str += oss.str();
179 }
180 break;
181
182 case ETM4_PKT_I_CCNT_F1:
183 case ETM4_PKT_I_CCNT_F2:
184 case ETM4_PKT_I_CCNT_F3:
185 {
186 std::ostringstream oss;
187 oss << "; Count=" << std::hex << "0x" << cycle_count;
188 str += oss.str();
189 }
190 break;
191
192 case ETM4_PKT_I_CANCEL_F1:
193 {
194 std::ostringstream oss;
195 oss << "; Cancel(" << std::dec << cancel_elements << ")";
196 str += oss.str();
197 }
198 break;
199
200 case ETM4_PKT_I_CANCEL_F1_MISPRED:
201 {
202 std::ostringstream oss;
203 oss << "; Cancel(" << std::dec << cancel_elements << "), Mispredict";
204 str += oss.str();
205 }
206 break;
207
208 case ETM4_PKT_I_MISPREDICT:
209 {
210 std::ostringstream oss;
211 oss << "; ";
212 if (atom.num) {
213 atomSeq(valStr);
214 oss << "Atom: " << valStr << ", ";
215 }
216 oss << "Mispredict";
217 str += oss.str();
218 }
219 break;
220
221 case ETM4_PKT_I_CANCEL_F2:
222 {
223 std::ostringstream oss;
224 oss << "; ";
225 if (atom.num) {
226 atomSeq(valStr);
227 oss << "Atom: " << valStr << ", ";
228 }
229 oss << "Cancel(1), Mispredict";
230 str += oss.str();
231 }
232 break;
233
234 case ETM4_PKT_I_CANCEL_F3:
235 {
236 std::ostringstream oss;
237 oss << "; ";
238 if (atom.num) {
239 oss << "Atom: E, ";
240 }
241 oss << "Cancel(" << std::dec << cancel_elements << "), Mispredict";
242 str += oss.str();
243 }
244 break;
245
246 case ETM4_PKT_I_COMMIT:
247 {
248 std::ostringstream oss;
249 oss << "; Commit(" << std::dec << commit_elements << ")";
250 str += oss.str();
251 }
252 break;
253
254 case ETM4_PKT_I_Q:
255 {
256 std::ostringstream oss;
257 if (Q_pkt.count_present)
258 {
259 oss << "; Count(" << std::dec << Q_pkt.q_count << ")";
260 str += oss.str();
261 }
262 else
263 str += "; Count(Unknown)";
264
265 if (Q_pkt.addr_match)
266 {
267 addrMatchIdx(valStr);
268 str += "; " + valStr;
269 }
270
271 if (Q_pkt.addr_present || Q_pkt.addr_match)
272 {
273 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 64) ? v_addr.pkt_bits : 0);
274 str += "; Addr=" + valStr;
275 }
276 }
277 break;
278 }
279
280 }
281
toStringFmt(const uint32_t fmtFlags,std::string & str) const282 void EtmV4ITrcPacket::toStringFmt(const uint32_t fmtFlags, std::string &str) const
283 {
284 toString(str); // TBD add in formatted response.
285 }
286
packetTypeName(const ocsd_etmv4_i_pkt_type type,const char ** ppDesc) const287 const char *EtmV4ITrcPacket::packetTypeName(const ocsd_etmv4_i_pkt_type type, const char **ppDesc) const
288 {
289 const char *pName = "I_UNKNOWN";
290 const char *pDesc = "Unknown Packet Header";
291
292 switch(type)
293 {
294 case ETM4_PKT_I_NOTSYNC:
295 pName = "I_NOT_SYNC";
296 pDesc = "I Stream not synchronised";
297 break;
298
299 case ETM4_PKT_I_INCOMPLETE_EOT:
300 pName = "I_INCOMPLETE_EOT";
301 pDesc = "Incomplete packet at end of trace.";
302 break;
303
304 case ETM4_PKT_I_NO_ERR_TYPE:
305 pName = "I_NO_ERR_TYPE";
306 pDesc = "No Error Type.";
307 break;
308
309 case ETM4_PKT_I_BAD_SEQUENCE:
310 pName = "I_BAD_SEQUENCE";
311 pDesc = "Invalid Sequence in packet.";
312 break;
313
314 case ETM4_PKT_I_BAD_TRACEMODE:
315 pName = "I_BAD_TRACEMODE";
316 pDesc = "Invalid Packet for trace mode.";
317 break;
318
319 case ETM4_PKT_I_RESERVED:
320 pName = "I_RESERVED";
321 pDesc = "Reserved Packet Header";
322 break;
323
324 case ETM4_PKT_I_RESERVED_CFG:
325 pName = "I_RESERVED_CFG";
326 pDesc = "Reserved header for current configuration.";
327 break;
328
329 case ETM4_PKT_I_EXTENSION:
330 pName = "I_EXTENSION";
331 pDesc = "Extension packet header.";
332 break;
333
334 case ETM4_PKT_I_TRACE_INFO:
335 pName = "I_TRACE_INFO";
336 pDesc = "Trace Info.";
337 break;
338
339 case ETM4_PKT_I_TIMESTAMP:
340 pName = "I_TIMESTAMP";
341 pDesc = "Timestamp.";
342 break;
343
344 case ETM4_PKT_I_TRACE_ON:
345 pName = "I_TRACE_ON";
346 pDesc = "Trace On.";
347 break;
348
349 case ETM4_PKT_I_FUNC_RET:
350 pName = "I_FUNC_RET";
351 pDesc = "V8M - function return.";
352 break;
353
354 case ETM4_PKT_I_EXCEPT:
355 pName = "I_EXCEPT";
356 pDesc = "Exception.";
357 break;
358
359 case ETM4_PKT_I_EXCEPT_RTN:
360 pName = "I_EXCEPT_RTN";
361 pDesc = "Exception Return.";
362 break;
363
364 case ETE_PKT_I_COMMIT_WIN_MV:
365 pName = "I_COMMIT_WIN_MV";
366 pDesc = "Commit window move.";
367 break;
368
369 case ETE_PKT_I_TRANS_ST:
370 pName = "I_TRANS_ST";
371 pDesc = "Transaction Start.";
372 break;
373
374 case ETE_PKT_I_TRANS_COMMIT:
375 pName = "I_TRANS_COMMIT";
376 pDesc = "Transaction Commit.";
377 break;
378
379 case ETM4_PKT_I_CCNT_F1:
380 pName = "I_CCNT_F1";
381 pDesc = "Cycle Count format 1.";
382 break;
383
384 case ETM4_PKT_I_CCNT_F2:
385 pName = "I_CCNT_F2";
386 pDesc = "Cycle Count format 2.";
387 break;
388
389 case ETM4_PKT_I_CCNT_F3:
390 pName = "I_CCNT_F3";
391 pDesc = "Cycle Count format 3.";
392 break;
393
394 case ETM4_PKT_I_NUM_DS_MKR:
395 pName = "I_NUM_DS_MKR";
396 pDesc = "Data Synchronisation Marker - Numbered.";
397 break;
398
399 case ETM4_PKT_I_UNNUM_DS_MKR:
400 pName = "I_UNNUM_DS_MKR";
401 pDesc = "Data Synchronisation Marker - Unnumbered.";
402 break;
403
404 case ETM4_PKT_I_COMMIT:
405 pName = "I_COMMIT";
406 pDesc = "Commit";
407 break;
408
409 case ETM4_PKT_I_CANCEL_F1:
410 pName = "I_CANCEL_F1";
411 pDesc = "Cancel Format 1.";
412 break;
413
414 case ETM4_PKT_I_CANCEL_F1_MISPRED:
415 pName = "I_CANCEL_F1_MISPRED";
416 pDesc = "Cancel Format 1 + Mispredict.";
417 break;
418
419
420 case ETM4_PKT_I_MISPREDICT:
421 pName = "I_MISPREDICT";
422 pDesc = "Mispredict.";
423 break;
424
425 case ETM4_PKT_I_CANCEL_F2:
426 pName = "I_CANCEL_F2";
427 pDesc = "Cancel Format 2.";
428 break;
429
430 case ETM4_PKT_I_CANCEL_F3:
431 pName = "I_CANCEL_F3";
432 pDesc = "Cancel Format 3.";
433 break;
434
435 case ETM4_PKT_I_COND_I_F2:
436 pName = "I_COND_I_F2";
437 pDesc = "Conditional Instruction, format 2.";
438 break;
439
440 case ETM4_PKT_I_COND_FLUSH:
441 pName = "I_COND_FLUSH";
442 pDesc = "Conditional Flush.";
443 break;
444
445 case ETM4_PKT_I_COND_RES_F4:
446 pName = "I_COND_RES_F4";
447 pDesc = "Conditional Result, format 4.";
448 break;
449
450 case ETM4_PKT_I_COND_RES_F2:
451 pName = "I_COND_RES_F2";
452 pDesc = "Conditional Result, format 2.";
453 break;
454
455 case ETM4_PKT_I_COND_RES_F3:
456 pName = "I_COND_RES_F3";
457 pDesc = "Conditional Result, format 3.";
458 break;
459
460 case ETM4_PKT_I_COND_RES_F1:
461 pName = "I_COND_RES_F1";
462 pDesc = "Conditional Result, format 1.";
463 break;
464
465 case ETM4_PKT_I_COND_I_F1:
466 pName = "I_COND_I_F1";
467 pDesc = "Conditional Instruction, format 1.";
468 break;
469
470 case ETM4_PKT_I_COND_I_F3:
471 pName = "I_COND_I_F3";
472 pDesc = "Conditional Instruction, format 3.";
473 break;
474
475 case ETM4_PKT_I_IGNORE:
476 pName = "I_IGNORE";
477 pDesc = "Ignore.";
478 break;
479
480 case ETM4_PKT_I_EVENT:
481 pName = "I_EVENT";
482 pDesc = "Trace Event.";
483 break;
484
485 case ETM4_PKT_I_CTXT:
486 pName = "I_CTXT";
487 pDesc = "Context Packet.";
488 break;
489
490 case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
491 pName = "I_ADDR_CTXT_L_32IS0";
492 pDesc = "Address & Context, Long, 32 bit, IS0.";
493 break;
494
495 case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
496 pName = "I_ADDR_CTXT_L_32IS1";
497 pDesc = "Address & Context, Long, 32 bit, IS0.";
498 break;
499
500 case ETM4_PKT_I_ADDR_CTXT_L_64IS0:
501 pName = "I_ADDR_CTXT_L_64IS0";
502 pDesc = "Address & Context, Long, 64 bit, IS0.";
503 break;
504
505 case ETM4_PKT_I_ADDR_CTXT_L_64IS1:
506 pName = "I_ADDR_CTXT_L_64IS1";
507 pDesc = "Address & Context, Long, 64 bit, IS1.";
508 break;
509
510 case ETE_PKT_I_TS_MARKER:
511 pName = "I_TS_MARKER";
512 pDesc = "Timestamp Marker";
513 break;
514
515 case ETM4_PKT_I_ADDR_MATCH:
516 pName = "I_ADDR_MATCH";
517 pDesc = "Exact Address Match.";
518 break;
519
520 case ETM4_PKT_I_ADDR_S_IS0:
521 pName = "I_ADDR_S_IS0";
522 pDesc = "Address, Short, IS0.";
523 break;
524
525 case ETM4_PKT_I_ADDR_S_IS1:
526 pName = "I_ADDR_S_IS1";
527 pDesc = "Address, Short, IS1.";
528 break;
529
530 case ETM4_PKT_I_ADDR_L_32IS0:
531 pName = "I_ADDR_L_32IS0";
532 pDesc = "Address, Long, 32 bit, IS0.";
533 break;
534
535 case ETM4_PKT_I_ADDR_L_32IS1:
536 pName = "I_ADDR_L_32IS1";
537 pDesc = "Address, Long, 32 bit, IS1.";
538 break;
539
540 case ETM4_PKT_I_ADDR_L_64IS0:
541 pName = "I_ADDR_L_64IS0";
542 pDesc = "Address, Long, 64 bit, IS0.";
543 break;
544
545 case ETM4_PKT_I_ADDR_L_64IS1:
546 pName = "I_ADDR_L_64IS1";
547 pDesc = "Address, Long, 64 bit, IS1.";
548 break;
549
550 case ETM4_PKT_I_Q:
551 pName = "I_Q";
552 pDesc = "Q Packet.";
553 break;
554
555 case ETE_PKT_I_SRC_ADDR_MATCH:
556 pName = "I_SRC_ADDR_MATCH";
557 pDesc = "Exact Source Address Match.";
558 break;
559
560 case ETE_PKT_I_SRC_ADDR_S_IS0:
561 pName = "I_SRC_ADDR_S_IS0";
562 pDesc = "Source Address, Short, IS0.";
563 break;
564
565 case ETE_PKT_I_SRC_ADDR_S_IS1:
566 pName = "I_SRC_ADDR_S_IS1";
567 pDesc = "Source Address, Short, IS1.";
568 break;
569
570 case ETE_PKT_I_SRC_ADDR_L_32IS0:
571 pName = "I_SCR_ADDR_L_32IS0";
572 pDesc = "Source Address, Long, 32 bit, IS0.";
573 break;
574
575 case ETE_PKT_I_SRC_ADDR_L_32IS1:
576 pName = "I_SRC_ADDR_L_32IS1";
577 pDesc = "Source Address, Long, 32 bit, IS1.";
578 break;
579
580 case ETE_PKT_I_SRC_ADDR_L_64IS0:
581 pName = "I_SRC_ADDR_L_64IS0";
582 pDesc = "Source Address, Long, 64 bit, IS0.";
583 break;
584
585 case ETE_PKT_I_SRC_ADDR_L_64IS1:
586 pName = "I_SRC_ADDR_L_64IS1";
587 pDesc = "Source Address, Long, 64 bit, IS1.";
588 break;
589
590 case ETM4_PKT_I_ATOM_F6:
591 pName = "I_ATOM_F6";
592 pDesc = "Atom format 6.";
593 break;
594
595 case ETM4_PKT_I_ATOM_F5:
596 pName = "I_ATOM_F5";
597 pDesc = "Atom format 5.";
598 break;
599
600 case ETM4_PKT_I_ATOM_F2:
601 pName = "I_ATOM_F2";
602 pDesc = "Atom format 2.";
603 break;
604
605 case ETM4_PKT_I_ATOM_F4:
606 pName = "I_ATOM_F4";
607 pDesc = "Atom format 4.";
608 break;
609
610 case ETM4_PKT_I_ATOM_F1:
611 pName = "I_ATOM_F1";
612 pDesc = "Atom format 1.";
613 break;
614
615 case ETM4_PKT_I_ATOM_F3:
616 pName = "I_ATOM_F3";
617 pDesc = "Atom format 3.";
618 break;
619
620 case ETM4_PKT_I_ASYNC:
621 pName = "I_ASYNC";
622 pDesc = "Alignment Synchronisation.";
623 break;
624
625 case ETM4_PKT_I_DISCARD:
626 pName = "I_DISCARD";
627 pDesc = "Discard.";
628 break;
629
630 case ETM4_PKT_I_OVERFLOW:
631 pName = "I_OVERFLOW";
632 pDesc = "Overflow.";
633 break;
634
635 case ETE_PKT_I_PE_RESET:
636 pName = "I_PE_RESET";
637 pDesc = "PE Reset.";
638 break;
639
640 case ETE_PKT_I_TRANS_FAIL:
641 pName = "I_TRANS_FAIL";
642 pDesc = "Transaction Fail.";
643 break;
644
645 default:
646 break;
647 }
648
649 if(ppDesc) *ppDesc = pDesc;
650 return pName;
651 }
652
contextStr(std::string & ctxtStr) const653 void EtmV4ITrcPacket::contextStr(std::string &ctxtStr) const
654 {
655 ctxtStr = "";
656 if(pkt_valid.bits.context_valid)
657 {
658 std::ostringstream oss;
659 if(context.updated)
660 {
661 oss << "Ctxt: " << (context.SF ? "AArch64," : "AArch32, ") << "EL" << context.EL << ", " << (context.NS ? "NS; " : "S; ");
662 if(context.updated_c)
663 {
664 oss << "CID=0x" << std::hex << std::setfill('0') << std::setw(8) << context.ctxtID << "; ";
665 }
666 if(context.updated_v)
667 {
668 oss << "VMID=0x" << std::hex << std::setfill('0') << std::setw(4) << context.VMID << "; ";
669 }
670 }
671 else
672 {
673 oss << "Ctxt: Same";
674 }
675 ctxtStr = oss.str();
676 }
677 }
678
atomSeq(std::string & valStr) const679 void EtmV4ITrcPacket::atomSeq(std::string &valStr) const
680 {
681 std::ostringstream oss;
682 uint32_t bitpattern = atom.En_bits;
683 for(int i = 0; i < atom.num; i++)
684 {
685 oss << ((bitpattern & 0x1) ? "E" : "N");
686 bitpattern >>= 1;
687 }
688 valStr = oss.str();
689 }
690
addrMatchIdx(std::string & valStr) const691 void EtmV4ITrcPacket::addrMatchIdx(std::string &valStr) const
692 {
693 std::ostringstream oss;
694 oss << "[" << (uint16_t)addr_exact_match_idx << "]";
695 valStr = oss.str();
696 }
697
exceptionInfo(std::string & valStr) const698 void EtmV4ITrcPacket::exceptionInfo(std::string &valStr) const
699 {
700 std::ostringstream oss;
701
702 static const char *ARv8Excep[] = {
703 "PE Reset", "Debug Halt", "Call", "Trap",
704 "System Error", "Reserved", "Inst Debug", "Data Debug",
705 "Reserved", "Reserved", "Alignment", "Inst Fault",
706 "Data Fault", "Reserved", "IRQ", "FIQ"
707 };
708
709 static const char *MExcep[] = {
710 "Reserved", "PE Reset", "NMI", "HardFault",
711 "MemManage", "BusFault", "UsageFault", "Reserved",
712 "Reserved","Reserved","Reserved","SVC",
713 "DebugMonitor", "Reserved","PendSV","SysTick",
714 "IRQ0","IRQ1","IRQ2","IRQ3",
715 "IRQ4","IRQ5","IRQ6","IRQ7",
716 "DebugHalt", "LazyFP Push", "Lockup", "Reserved",
717 "Reserved","Reserved","Reserved","Reserved"
718 };
719
720 if(exception_info.m_type == 0)
721 {
722 if(exception_info.exceptionType < 0x10)
723 oss << " " << ARv8Excep[exception_info.exceptionType] << ";";
724 else
725 oss << " Reserved;";
726
727 }
728 else
729 {
730 if(exception_info.exceptionType < 0x20)
731 oss << " " << MExcep[exception_info.exceptionType] << ";";
732 else if((exception_info.exceptionType >= 0x208) && (exception_info.exceptionType <= 0x3EF))
733 oss << " IRQ" << (int)(exception_info.exceptionType - 0x200) << ";";
734 else
735 oss << " Reserved;";
736 if(exception_info.m_fault_pending)
737 oss << " Fault Pending;";
738 }
739
740 if(exception_info.addr_interp == 0x1)
741 oss << " Ret Addr Follows;";
742 else if(exception_info.addr_interp == 0x2)
743 oss << " Ret Addr Follows, Match Prev;";
744
745 valStr = oss.str();
746 }
747
operator =(const ocsd_etmv4_i_pkt * p_pkt)748 EtmV4ITrcPacket &EtmV4ITrcPacket::operator =(const ocsd_etmv4_i_pkt* p_pkt)
749 {
750 *dynamic_cast<ocsd_etmv4_i_pkt *>(this) = *p_pkt;
751 return *this;
752 }
753
754 /* End of File trc_pkt_elem_etmv4i.cpp */
755