1 /*
2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7 #ifdef DRV_ROCKCHIP
8
9 #include <errno.h>
10 #include <inttypes.h>
11 #include <rockchip_drm.h>
12 #include <stdio.h>
13 #include <string.h>
14 #include <sys/mman.h>
15 #include <xf86drm.h>
16
17 #include "drv_priv.h"
18 #include "helpers.h"
19 #include "util.h"
20
21 struct rockchip_private_map_data {
22 void *cached_addr;
23 void *gem_addr;
24 };
25
26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
27 DRM_FORMAT_BGR888, DRM_FORMAT_RGB565,
28 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888 };
29
30 static const uint32_t texture_only_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_YVU420,
31 DRM_FORMAT_YVU420_ANDROID };
32
afbc_bo_from_format(struct bo * bo,uint32_t width,uint32_t height,uint32_t format)33 static int afbc_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
34 {
35 /* We've restricted ourselves to four bytes per pixel. */
36 const uint32_t pixel_size = 4;
37
38 const uint32_t clump_width = 4;
39 const uint32_t clump_height = 4;
40
41 #define AFBC_NARROW 1
42 #if AFBC_NARROW == 1
43 const uint32_t block_width = 4 * clump_width;
44 const uint32_t block_height = 4 * clump_height;
45 #else
46 const uint32_t block_width = 8 * clump_width;
47 const uint32_t block_height = 2 * clump_height;
48 #endif
49
50 const uint32_t header_block_size = 16;
51 const uint32_t body_block_size = block_width * block_height * pixel_size;
52 const uint32_t width_in_blocks = DIV_ROUND_UP(width, block_width);
53 const uint32_t height_in_blocks = DIV_ROUND_UP(height, block_height);
54 const uint32_t total_blocks = width_in_blocks * height_in_blocks;
55
56 const uint32_t header_plane_size = total_blocks * header_block_size;
57 const uint32_t body_plane_size = total_blocks * body_block_size;
58
59 /* GPU requires 64 bytes, but EGL import code expects 1024 byte
60 * alignement for the body plane. */
61 const uint32_t body_plane_alignment = 1024;
62
63 const uint32_t body_plane_offset = ALIGN(header_plane_size, body_plane_alignment);
64 const uint32_t total_size = body_plane_offset + body_plane_size;
65
66 bo->meta.strides[0] = width_in_blocks * block_width * pixel_size;
67 bo->meta.sizes[0] = total_size;
68 bo->meta.offsets[0] = 0;
69
70 bo->meta.total_size = total_size;
71
72 bo->meta.format_modifier = DRM_FORMAT_MOD_CHROMEOS_ROCKCHIP_AFBC;
73
74 return 0;
75 }
76
rockchip_init(struct driver * drv)77 static int rockchip_init(struct driver *drv)
78 {
79 struct format_metadata metadata;
80
81 metadata.tiling = 0;
82 metadata.priority = 1;
83 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
84
85 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
86 &metadata, BO_USE_RENDER_MASK | BO_USE_SCANOUT);
87
88 drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
89 BO_USE_TEXTURE_MASK);
90
91 /* NV12 format for camera, display, decoding and encoding. */
92 /* Camera ISP supports only NV12 output. */
93 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
94 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
95 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
96
97 drv_modify_linear_combinations(drv);
98 /*
99 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
100 * from camera and input/output from hardware decoder/encoder.
101 */
102 drv_add_combination(drv, DRM_FORMAT_R8, &metadata,
103 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SW_MASK |
104 BO_USE_LINEAR | BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
105
106 return 0;
107 }
108
rockchip_bo_create_with_modifiers(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,const uint64_t * modifiers,uint32_t count)109 static int rockchip_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
110 uint32_t format, const uint64_t *modifiers,
111 uint32_t count)
112 {
113 int ret;
114 size_t plane;
115 struct drm_rockchip_gem_create gem_create = { 0 };
116
117 if (format == DRM_FORMAT_NV12) {
118 uint32_t w_mbs = DIV_ROUND_UP(width, 16);
119 uint32_t h_mbs = DIV_ROUND_UP(height, 16);
120
121 uint32_t aligned_width = w_mbs * 16;
122 uint32_t aligned_height = h_mbs * 16;
123
124 drv_bo_from_format(bo, aligned_width, aligned_height, format);
125 /*
126 * drv_bo_from_format updates total_size. Add an extra data space for rockchip video
127 * driver to store motion vectors.
128 */
129 bo->meta.total_size += w_mbs * h_mbs * 128;
130 } else if (width <= 2560 &&
131 drv_has_modifier(modifiers, count, DRM_FORMAT_MOD_CHROMEOS_ROCKCHIP_AFBC) &&
132 bo->drv->compression) {
133 /* If the caller has decided they can use AFBC, always
134 * pick that */
135 afbc_bo_from_format(bo, width, height, format);
136 } else {
137 if (!drv_has_modifier(modifiers, count, DRM_FORMAT_MOD_LINEAR)) {
138 errno = EINVAL;
139 drv_log("no usable modifier found\n");
140 return -errno;
141 }
142
143 uint32_t stride;
144 /*
145 * Since the ARM L1 cache line size is 64 bytes, align to that
146 * as a performance optimization. For YV12, the Mali cmem allocator
147 * requires that chroma planes are aligned to 64-bytes, so align the
148 * luma plane to 128 bytes.
149 */
150 stride = drv_stride_from_format(format, width, 0);
151 if (format == DRM_FORMAT_YVU420 || format == DRM_FORMAT_YVU420_ANDROID)
152 stride = ALIGN(stride, 128);
153 else
154 stride = ALIGN(stride, 64);
155
156 drv_bo_from_format(bo, stride, height, format);
157 }
158
159 gem_create.size = bo->meta.total_size;
160 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_ROCKCHIP_GEM_CREATE, &gem_create);
161
162 if (ret) {
163 drv_log("DRM_IOCTL_ROCKCHIP_GEM_CREATE failed (size=%" PRIu64 ")\n",
164 gem_create.size);
165 return -errno;
166 }
167
168 for (plane = 0; plane < bo->meta.num_planes; plane++)
169 bo->handles[plane].u32 = gem_create.handle;
170
171 return 0;
172 }
173
rockchip_bo_create(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)174 static int rockchip_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
175 uint64_t use_flags)
176 {
177 uint64_t modifiers[] = { DRM_FORMAT_MOD_LINEAR };
178 return rockchip_bo_create_with_modifiers(bo, width, height, format, modifiers,
179 ARRAY_SIZE(modifiers));
180 }
181
rockchip_bo_map(struct bo * bo,struct vma * vma,size_t plane,uint32_t map_flags)182 static void *rockchip_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
183 {
184 int ret;
185 struct rockchip_private_map_data *priv;
186 struct drm_rockchip_gem_map_off gem_map = { 0 };
187
188 /* We can only map buffers created with SW access flags, which should
189 * have no modifiers (ie, not AFBC). */
190 if (bo->meta.format_modifier == DRM_FORMAT_MOD_CHROMEOS_ROCKCHIP_AFBC)
191 return MAP_FAILED;
192
193 gem_map.handle = bo->handles[0].u32;
194 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET, &gem_map);
195 if (ret) {
196 drv_log("DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET failed\n");
197 return MAP_FAILED;
198 }
199
200 void *addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
201 gem_map.offset);
202
203 vma->length = bo->meta.total_size;
204
205 if (bo->meta.use_flags & BO_USE_RENDERSCRIPT) {
206 priv = calloc(1, sizeof(*priv));
207 priv->cached_addr = calloc(1, bo->meta.total_size);
208 priv->gem_addr = addr;
209 vma->priv = priv;
210 addr = priv->cached_addr;
211 }
212
213 return addr;
214 }
215
rockchip_bo_unmap(struct bo * bo,struct vma * vma)216 static int rockchip_bo_unmap(struct bo *bo, struct vma *vma)
217 {
218 if (vma->priv) {
219 struct rockchip_private_map_data *priv = vma->priv;
220 vma->addr = priv->gem_addr;
221 free(priv->cached_addr);
222 free(priv);
223 vma->priv = NULL;
224 }
225
226 return munmap(vma->addr, vma->length);
227 }
228
rockchip_bo_invalidate(struct bo * bo,struct mapping * mapping)229 static int rockchip_bo_invalidate(struct bo *bo, struct mapping *mapping)
230 {
231 if (mapping->vma->priv) {
232 struct rockchip_private_map_data *priv = mapping->vma->priv;
233 memcpy(priv->cached_addr, priv->gem_addr, bo->meta.total_size);
234 }
235
236 return 0;
237 }
238
rockchip_bo_flush(struct bo * bo,struct mapping * mapping)239 static int rockchip_bo_flush(struct bo *bo, struct mapping *mapping)
240 {
241 struct rockchip_private_map_data *priv = mapping->vma->priv;
242 if (priv && (mapping->vma->map_flags & BO_MAP_WRITE))
243 memcpy(priv->gem_addr, priv->cached_addr, bo->meta.total_size);
244
245 return 0;
246 }
247
248 const struct backend backend_rockchip = {
249 .name = "rockchip",
250 .init = rockchip_init,
251 .bo_create = rockchip_bo_create,
252 .bo_create_with_modifiers = rockchip_bo_create_with_modifiers,
253 .bo_destroy = drv_gem_bo_destroy,
254 .bo_import = drv_prime_bo_import,
255 .bo_map = rockchip_bo_map,
256 .bo_unmap = rockchip_bo_unmap,
257 .bo_invalidate = rockchip_bo_invalidate,
258 .bo_flush = rockchip_bo_flush,
259 .resolve_format = drv_resolve_format_helper,
260 };
261
262 #endif
263