/external/llvm-project/llvm/test/MC/AArch64/SVE/ |
D | bics-diagnostics.s | 6 bics p0.h, p0/z, p0.h, p1.h label 11 bics p0.s, p0/z, p0.s, p1.s label 16 bics p0.d, p0/z, p0.d, p1.d label 24 bics p0.b, p0/m, p1.b, p2.b label
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D | bics.s | 10 bics p0.b, p0/z, p0.b, p0.b label 16 bics p15.b, p15/z, p15.b, p15.b label
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/external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
D | m7-int.s | 50 bics r0, r1, #1 label 51 bics r0, r1 label
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D | m4-int.s | 52 bics r0, r1, #1 label 53 bics r0, r1 label
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/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
D | A55-basic-instructions.s | 1310 bics w3, w5, w7 label 1311 bics x3, xzr, x3, lsl #1 label
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/external/vixl/test/aarch64/ |
D | test-assembler-aarch64.cc | 829 TEST(bics) { in TEST() argument 7424 __ bics(xzr, x3, ~0xf); in TEST() local 7425 __ bics(xzr, xzr, ~0xf); in TEST() local 7426 __ bics(xzr, x0, x3); in TEST() local 7427 __ bics(xzr, x3, xzr); in TEST() local 7428 __ bics(xzr, xzr, x3); in TEST() local
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D | test-trace-aarch64.cc | 77 __ bics(w3, w4, w5); in GenerateTestSequenceBase() local 78 __ bics(x6, x7, x8); in GenerateTestSequenceBase() local
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 2089 void bics(Register rd, Register rn, const Operand& operand) { in bics() function 2092 void bics(Condition cond, Register rd, Register rn, const Operand& operand) { in bics() function 2095 void bics(EncodingSize size, in bics() function
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D | assembler-aarch32.cc | 3338 void Assembler::bics(Condition cond, in bics() function in vixl::aarch32::Assembler
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D | disasm-aarch32.cc | 1310 void Disassembler::bics(Condition cond, in bics() function in vixl::aarch32::Disassembler
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/external/vixl/src/aarch64/ |
D | assembler-sve-aarch64.cc | 6000 void Assembler::bics(const PRegisterWithLaneSize& pd, in bics() function in vixl::aarch64::Assembler
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D | assembler-aarch64.cc | 607 void Assembler::bics(const Register& rd, in bics() function in vixl::aarch64::Assembler
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/external/vixl/test/aarch32/ |
D | test-assembler-aarch32.cc | 990 TEST(bics) { in TEST() argument
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