1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <errno.h>
25
26 #include "program/prog_instruction.h"
27
28 #include "blorp_priv.h"
29 #include "compiler/brw_compiler.h"
30 #include "compiler/brw_nir.h"
31
32 const char *
blorp_shader_type_to_name(enum blorp_shader_type type)33 blorp_shader_type_to_name(enum blorp_shader_type type)
34 {
35 static const char *shader_name[] = {
36 [BLORP_SHADER_TYPE_COPY] = "BLORP-copy",
37 [BLORP_SHADER_TYPE_BLIT] = "BLORP-blit",
38 [BLORP_SHADER_TYPE_CLEAR] = "BLORP-clear",
39 [BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE] = "BLORP-mcs-partial-resolve",
40 [BLORP_SHADER_TYPE_LAYER_OFFSET_VS] = "BLORP-layer-offset-vs",
41 [BLORP_SHADER_TYPE_GEN4_SF] = "BLORP-gen4-sf",
42 };
43 assert(type < ARRAY_SIZE(shader_name));
44
45 return shader_name[type];
46 }
47
48 void
blorp_init(struct blorp_context * blorp,void * driver_ctx,struct isl_device * isl_dev)49 blorp_init(struct blorp_context *blorp, void *driver_ctx,
50 struct isl_device *isl_dev)
51 {
52 blorp->driver_ctx = driver_ctx;
53 blorp->isl_dev = isl_dev;
54 }
55
56 void
blorp_finish(struct blorp_context * blorp)57 blorp_finish(struct blorp_context *blorp)
58 {
59 blorp->driver_ctx = NULL;
60 }
61
62 void
blorp_batch_init(struct blorp_context * blorp,struct blorp_batch * batch,void * driver_batch,enum blorp_batch_flags flags)63 blorp_batch_init(struct blorp_context *blorp,
64 struct blorp_batch *batch, void *driver_batch,
65 enum blorp_batch_flags flags)
66 {
67 batch->blorp = blorp;
68 batch->driver_batch = driver_batch;
69 batch->flags = flags;
70 }
71
72 void
blorp_batch_finish(struct blorp_batch * batch)73 blorp_batch_finish(struct blorp_batch *batch)
74 {
75 batch->blorp = NULL;
76 }
77
78 void
brw_blorp_surface_info_init(struct blorp_context * blorp,struct brw_blorp_surface_info * info,const struct blorp_surf * surf,unsigned int level,float layer,enum isl_format format,bool is_render_target)79 brw_blorp_surface_info_init(struct blorp_context *blorp,
80 struct brw_blorp_surface_info *info,
81 const struct blorp_surf *surf,
82 unsigned int level, float layer,
83 enum isl_format format, bool is_render_target)
84 {
85 memset(info, 0, sizeof(*info));
86 assert(level < surf->surf->levels);
87 assert(layer < MAX2(surf->surf->logical_level0_px.depth >> level,
88 surf->surf->logical_level0_px.array_len));
89
90 info->enabled = true;
91
92 if (format == ISL_FORMAT_UNSUPPORTED)
93 format = surf->surf->format;
94
95 info->surf = *surf->surf;
96 info->addr = surf->addr;
97
98 info->aux_usage = surf->aux_usage;
99 if (info->aux_usage != ISL_AUX_USAGE_NONE) {
100 info->aux_surf = *surf->aux_surf;
101 info->aux_addr = surf->aux_addr;
102 }
103
104 info->clear_color = surf->clear_color;
105 info->clear_color_addr = surf->clear_color_addr;
106
107 info->view = (struct isl_view) {
108 .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
109 ISL_SURF_USAGE_TEXTURE_BIT,
110 .format = format,
111 .base_level = level,
112 .levels = 1,
113 .swizzle = ISL_SWIZZLE_IDENTITY,
114 };
115
116 info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
117 info->surf.logical_level0_px.array_len);
118
119 if (!is_render_target &&
120 (info->surf.dim == ISL_SURF_DIM_3D ||
121 info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
122 /* 3-D textures don't support base_array layer and neither do 2-D
123 * multisampled textures on IVB so we need to pass it through the
124 * sampler in those cases. These are also two cases where we are
125 * guaranteed that we won't be doing any funny surface hacks.
126 */
127 info->view.base_array_layer = 0;
128 info->z_offset = layer;
129 } else {
130 info->view.base_array_layer = layer;
131
132 assert(info->view.array_len >= info->view.base_array_layer);
133 info->view.array_len -= info->view.base_array_layer;
134 info->z_offset = 0;
135 }
136
137 /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
138 * layered rendering.
139 */
140 if (is_render_target && blorp->isl_dev->info->gen <= 6)
141 info->view.array_len = MIN2(info->view.array_len, 512);
142
143 if (surf->tile_x_sa || surf->tile_y_sa) {
144 /* This is only allowed on simple 2D surfaces without MSAA */
145 assert(info->surf.dim == ISL_SURF_DIM_2D);
146 assert(info->surf.samples == 1);
147 assert(info->surf.levels == 1);
148 assert(info->surf.logical_level0_px.array_len == 1);
149 assert(info->aux_usage == ISL_AUX_USAGE_NONE);
150
151 info->tile_x_sa = surf->tile_x_sa;
152 info->tile_y_sa = surf->tile_y_sa;
153
154 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
155 * place the image at the tile boundary and offset our sampling or
156 * rendering. For this reason, we need to grow the image by the offset
157 * to ensure that the hardware doesn't think we've gone past the edge.
158 */
159 info->surf.logical_level0_px.w += surf->tile_x_sa;
160 info->surf.logical_level0_px.h += surf->tile_y_sa;
161 info->surf.phys_level0_sa.w += surf->tile_x_sa;
162 info->surf.phys_level0_sa.h += surf->tile_y_sa;
163 }
164 }
165
166
167 void
blorp_params_init(struct blorp_params * params)168 blorp_params_init(struct blorp_params *params)
169 {
170 memset(params, 0, sizeof(*params));
171 params->num_samples = 1;
172 params->num_draw_buffers = 1;
173 params->num_layers = 1;
174 }
175
176 void
brw_blorp_init_wm_prog_key(struct brw_wm_prog_key * wm_key)177 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
178 {
179 memset(wm_key, 0, sizeof(*wm_key));
180 wm_key->nr_color_regions = 1;
181 for (int i = 0; i < MAX_SAMPLERS; i++)
182 wm_key->base.tex.swizzles[i] = SWIZZLE_XYZW;
183 }
184
185 const unsigned *
blorp_compile_fs(struct blorp_context * blorp,void * mem_ctx,struct nir_shader * nir,struct brw_wm_prog_key * wm_key,bool use_repclear,struct brw_wm_prog_data * wm_prog_data)186 blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
187 struct nir_shader *nir,
188 struct brw_wm_prog_key *wm_key,
189 bool use_repclear,
190 struct brw_wm_prog_data *wm_prog_data)
191 {
192 const struct brw_compiler *compiler = blorp->compiler;
193
194 nir->options =
195 compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
196
197 memset(wm_prog_data, 0, sizeof(*wm_prog_data));
198
199 wm_prog_data->base.nr_params = 0;
200 wm_prog_data->base.param = NULL;
201
202 /* BLORP always uses the first two binding table entries:
203 * - Surface 0 is the render target (which always start from 0)
204 * - Surface 1 is the source texture
205 */
206 wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
207
208 brw_preprocess_nir(compiler, nir, NULL);
209 nir_remove_dead_variables(nir, nir_var_shader_in, NULL);
210 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
211
212 if (blorp->compiler->devinfo->gen < 6) {
213 if (nir->info.fs.uses_discard)
214 wm_key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
215
216 wm_key->input_slots_valid = nir->info.inputs_read | VARYING_BIT_POS;
217 }
218
219 const unsigned *program =
220 brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx, wm_key,
221 wm_prog_data, nir, -1, -1, -1, false, use_repclear,
222 NULL, NULL, NULL);
223
224 return program;
225 }
226
227 const unsigned *
blorp_compile_vs(struct blorp_context * blorp,void * mem_ctx,struct nir_shader * nir,struct brw_vs_prog_data * vs_prog_data)228 blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
229 struct nir_shader *nir,
230 struct brw_vs_prog_data *vs_prog_data)
231 {
232 const struct brw_compiler *compiler = blorp->compiler;
233
234 nir->options =
235 compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
236
237 brw_preprocess_nir(compiler, nir, NULL);
238 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
239
240 vs_prog_data->inputs_read = nir->info.inputs_read;
241
242 brw_compute_vue_map(compiler->devinfo,
243 &vs_prog_data->base.vue_map,
244 nir->info.outputs_written,
245 nir->info.separate_shader,
246 1);
247
248 struct brw_vs_prog_key vs_key = { 0, };
249
250 const unsigned *program =
251 brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
252 &vs_key, vs_prog_data, nir, -1, NULL, NULL);
253
254 return program;
255 }
256
257 struct blorp_sf_key {
258 enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_GEN4_SF */
259
260 struct brw_sf_prog_key key;
261 };
262
263 bool
blorp_ensure_sf_program(struct blorp_batch * batch,struct blorp_params * params)264 blorp_ensure_sf_program(struct blorp_batch *batch,
265 struct blorp_params *params)
266 {
267 struct blorp_context *blorp = batch->blorp;
268 const struct brw_wm_prog_data *wm_prog_data = params->wm_prog_data;
269 assert(params->wm_prog_data);
270
271 /* Gen6+ doesn't need a strips and fans program */
272 if (blorp->compiler->devinfo->gen >= 6)
273 return true;
274
275 struct blorp_sf_key key = {
276 .shader_type = BLORP_SHADER_TYPE_GEN4_SF,
277 };
278
279 /* Everything gets compacted in vertex setup, so we just need a
280 * pass-through for the correct number of input varyings.
281 */
282 const uint64_t slots_valid = VARYING_BIT_POS |
283 ((1ull << wm_prog_data->num_varying_inputs) - 1) << VARYING_SLOT_VAR0;
284
285 key.key.attrs = slots_valid;
286 key.key.primitive = BRW_SF_PRIM_TRIANGLES;
287 key.key.contains_flat_varying = wm_prog_data->contains_flat_varying;
288
289 STATIC_ASSERT(sizeof(key.key.interp_mode) ==
290 sizeof(wm_prog_data->interp_mode));
291 memcpy(key.key.interp_mode, wm_prog_data->interp_mode,
292 sizeof(key.key.interp_mode));
293
294 if (blorp->lookup_shader(batch, &key, sizeof(key),
295 ¶ms->sf_prog_kernel, ¶ms->sf_prog_data))
296 return true;
297
298 void *mem_ctx = ralloc_context(NULL);
299
300 const unsigned *program;
301 unsigned program_size;
302
303 struct brw_vue_map vue_map;
304 brw_compute_vue_map(blorp->compiler->devinfo, &vue_map, slots_valid, false, 1);
305
306 struct brw_sf_prog_data prog_data_tmp;
307 program = brw_compile_sf(blorp->compiler, mem_ctx, &key.key,
308 &prog_data_tmp, &vue_map, &program_size);
309
310 bool result =
311 blorp->upload_shader(batch, MESA_SHADER_NONE,
312 &key, sizeof(key), program, program_size,
313 (void *)&prog_data_tmp, sizeof(prog_data_tmp),
314 ¶ms->sf_prog_kernel, ¶ms->sf_prog_data);
315
316 ralloc_free(mem_ctx);
317
318 return result;
319 }
320
321 void
blorp_hiz_op(struct blorp_batch * batch,struct blorp_surf * surf,uint32_t level,uint32_t start_layer,uint32_t num_layers,enum isl_aux_op op)322 blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
323 uint32_t level, uint32_t start_layer, uint32_t num_layers,
324 enum isl_aux_op op)
325 {
326 struct blorp_params params;
327 blorp_params_init(¶ms);
328
329 params.hiz_op = op;
330 params.full_surface_hiz_op = true;
331
332 for (uint32_t a = 0; a < num_layers; a++) {
333 const uint32_t layer = start_layer + a;
334
335 brw_blorp_surface_info_init(batch->blorp, ¶ms.depth, surf, level,
336 layer, surf->surf->format, true);
337
338 /* Align the rectangle primitive to 8x4 pixels.
339 *
340 * During fast depth clears, the emitted rectangle primitive must be
341 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
342 * 11.5.3.1 Depth Buffer Clear (and the matching section in the
343 * Sandybridge PRM):
344 *
345 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
346 * aligned to an 8x4 pixel block relative to the upper left corner
347 * of the depth buffer [...]
348 *
349 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
350 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
351 * Ivybridge simulator require the alignment.
352 *
353 * To be safe, let's just align the rect for all hiz operations and all
354 * hardware generations.
355 *
356 * However, for some miptree slices of a Z24 texture, emitting an 8x4
357 * aligned rectangle that covers the slice may clobber adjacent slices
358 * if we strictly adhered to the texture alignments specified in the
359 * PRM. The Ivybridge PRM, Section "Alignment Unit Size", states that
360 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
361 * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
362 * 8, which prevents the clobbering.
363 */
364 params.x1 = minify(params.depth.surf.logical_level0_px.width,
365 params.depth.view.base_level);
366 params.y1 = minify(params.depth.surf.logical_level0_px.height,
367 params.depth.view.base_level);
368 params.x1 = ALIGN(params.x1, 8);
369 params.y1 = ALIGN(params.y1, 4);
370
371 if (params.depth.view.base_level == 0) {
372 /* TODO: What about MSAA? */
373 params.depth.surf.logical_level0_px.width = params.x1;
374 params.depth.surf.logical_level0_px.height = params.y1;
375 }
376
377 params.dst.surf.samples = params.depth.surf.samples;
378 params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
379 params.depth_format =
380 isl_format_get_depth_format(surf->surf->format, false);
381 params.num_samples = params.depth.surf.samples;
382
383 batch->blorp->exec(batch, ¶ms);
384 }
385 }
386
387 void
blorp_hiz_stencil_op(struct blorp_batch * batch,struct blorp_surf * stencil,uint32_t level,uint32_t start_layer,uint32_t num_layers,enum isl_aux_op op)388 blorp_hiz_stencil_op(struct blorp_batch *batch, struct blorp_surf *stencil,
389 uint32_t level, uint32_t start_layer,
390 uint32_t num_layers, enum isl_aux_op op)
391 {
392 struct blorp_params params;
393 blorp_params_init(¶ms);
394
395 params.hiz_op = op;
396 params.full_surface_hiz_op = true;
397
398 for (uint32_t a = 0; a < num_layers; a++) {
399 const uint32_t layer = start_layer + a;
400
401 brw_blorp_surface_info_init(batch->blorp, ¶ms.stencil, stencil, level,
402 layer, stencil->surf->format, true);
403 params.x1 = minify(params.stencil.surf.logical_level0_px.width,
404 params.stencil.view.base_level);
405 params.y1 = minify(params.stencil.surf.logical_level0_px.height,
406 params.stencil.view.base_level);
407 params.dst.surf.samples = params.stencil.surf.samples;
408 params.dst.surf.logical_level0_px =
409 params.stencil.surf.logical_level0_px;
410 params.dst.view = params.stencil.view;
411 params.num_samples = params.stencil.surf.samples;
412
413 batch->blorp->exec(batch, ¶ms);
414 }
415 }
416