1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
33
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "intel_buffer_objects.h"
40 #include "intel_fbo.h"
41 #include "dev/gen_debug.h"
42
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
44
45 static bool
brw_blorp_lookup_shader(struct blorp_batch * batch,const void * key,uint32_t key_size,uint32_t * kernel_out,void * prog_data_out)46 brw_blorp_lookup_shader(struct blorp_batch *batch,
47 const void *key, uint32_t key_size,
48 uint32_t *kernel_out, void *prog_data_out)
49 {
50 struct brw_context *brw = batch->driver_batch;
51 return brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
52 kernel_out, prog_data_out, true);
53 }
54
55 static bool
brw_blorp_upload_shader(struct blorp_batch * batch,uint32_t stage,const void * key,uint32_t key_size,const void * kernel,uint32_t kernel_size,const struct brw_stage_prog_data * prog_data,uint32_t prog_data_size,uint32_t * kernel_out,void * prog_data_out)56 brw_blorp_upload_shader(struct blorp_batch *batch, uint32_t stage,
57 const void *key, uint32_t key_size,
58 const void *kernel, uint32_t kernel_size,
59 const struct brw_stage_prog_data *prog_data,
60 uint32_t prog_data_size,
61 uint32_t *kernel_out, void *prog_data_out)
62 {
63 struct brw_context *brw = batch->driver_batch;
64 brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
65 kernel, kernel_size, prog_data, prog_data_size,
66 kernel_out, prog_data_out);
67 return true;
68 }
69
70 void
brw_blorp_init(struct brw_context * brw)71 brw_blorp_init(struct brw_context *brw)
72 {
73 const struct gen_device_info *devinfo = &brw->screen->devinfo;
74
75 blorp_init(&brw->blorp, brw, &brw->isl_dev);
76
77 brw->blorp.compiler = brw->screen->compiler;
78
79 switch (devinfo->gen) {
80 case 4:
81 if (devinfo->is_g4x) {
82 brw->blorp.exec = gen45_blorp_exec;
83 } else {
84 brw->blorp.exec = gen4_blorp_exec;
85 }
86 break;
87 case 5:
88 brw->blorp.exec = gen5_blorp_exec;
89 break;
90 case 6:
91 brw->blorp.exec = gen6_blorp_exec;
92 break;
93 case 7:
94 if (devinfo->is_haswell) {
95 brw->blorp.exec = gen75_blorp_exec;
96 } else {
97 brw->blorp.exec = gen7_blorp_exec;
98 }
99 break;
100 case 8:
101 brw->blorp.exec = gen8_blorp_exec;
102 break;
103 case 9:
104 brw->blorp.exec = gen9_blorp_exec;
105 break;
106 case 11:
107 brw->blorp.exec = gen11_blorp_exec;
108 break;
109
110 default:
111 unreachable("Invalid gen");
112 }
113
114 brw->blorp.lookup_shader = brw_blorp_lookup_shader;
115 brw->blorp.upload_shader = brw_blorp_upload_shader;
116 }
117
118 static void
blorp_surf_for_miptree(struct brw_context * brw,struct blorp_surf * surf,const struct intel_mipmap_tree * mt,enum isl_aux_usage aux_usage,bool is_render_target,unsigned * level,unsigned start_layer,unsigned num_layers)119 blorp_surf_for_miptree(struct brw_context *brw,
120 struct blorp_surf *surf,
121 const struct intel_mipmap_tree *mt,
122 enum isl_aux_usage aux_usage,
123 bool is_render_target,
124 unsigned *level,
125 unsigned start_layer, unsigned num_layers)
126 {
127 const struct gen_device_info *devinfo = &brw->screen->devinfo;
128
129 if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
130 const unsigned num_samples = mt->surf.samples;
131 for (unsigned i = 0; i < num_layers; i++) {
132 for (unsigned s = 0; s < num_samples; s++) {
133 const unsigned phys_layer = (start_layer + i) * num_samples + s;
134 intel_miptree_check_level_layer(mt, *level, phys_layer);
135 }
136 }
137 } else {
138 for (unsigned i = 0; i < num_layers; i++)
139 intel_miptree_check_level_layer(mt, *level, start_layer + i);
140 }
141
142 *surf = (struct blorp_surf) {
143 .surf = &mt->surf,
144 .addr = (struct blorp_address) {
145 .buffer = mt->bo,
146 .offset = mt->offset,
147 .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
148 .mocs = brw_get_bo_mocs(devinfo, mt->bo),
149 },
150 .aux_usage = aux_usage,
151 .tile_x_sa = mt->level[*level].level_x,
152 .tile_y_sa = mt->level[*level].level_y,
153 };
154
155 if (surf->aux_usage == ISL_AUX_USAGE_HIZ &&
156 !intel_miptree_level_has_hiz(mt, *level))
157 surf->aux_usage = ISL_AUX_USAGE_NONE;
158
159 if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
160 /* We only really need a clear color if we also have an auxiliary
161 * surface. Without one, it does nothing.
162 */
163 surf->clear_color =
164 intel_miptree_get_clear_color(mt, (struct brw_bo **)
165 &surf->clear_color_addr.buffer,
166 &surf->clear_color_addr.offset);
167
168 surf->aux_surf = &mt->aux_buf->surf;
169 surf->aux_addr = (struct blorp_address) {
170 .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
171 .mocs = surf->addr.mocs,
172 };
173
174 surf->aux_addr.buffer = mt->aux_buf->bo;
175 surf->aux_addr.offset = mt->aux_buf->offset;
176 } else {
177 surf->aux_addr = (struct blorp_address) {
178 .buffer = NULL,
179 };
180 memset(&surf->clear_color, 0, sizeof(surf->clear_color));
181 }
182 assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
183 (surf->aux_addr.buffer == NULL));
184
185 if (!is_render_target && brw->screen->devinfo.gen == 9)
186 gen9_apply_single_tex_astc5x5_wa(brw, mt->format, surf->aux_usage);
187
188 /* ISL wants real levels, not offset ones. */
189 *level -= mt->first_level;
190 }
191
192 static bool
brw_blorp_supports_dst_format(struct brw_context * brw,mesa_format format)193 brw_blorp_supports_dst_format(struct brw_context *brw, mesa_format format)
194 {
195 /* If it's renderable, it's definitely supported. */
196 if (brw->mesa_format_supports_render[format])
197 return true;
198
199 /* BLORP can't compress anything */
200 if (_mesa_is_format_compressed(format))
201 return false;
202
203 /* No exotic formats such as GL_LUMINANCE_ALPHA */
204 if (_mesa_get_format_bits(format, GL_RED_BITS) == 0 &&
205 _mesa_get_format_bits(format, GL_DEPTH_BITS) == 0 &&
206 _mesa_get_format_bits(format, GL_STENCIL_BITS) == 0)
207 return false;
208
209 return true;
210 }
211
212 static enum isl_format
brw_blorp_to_isl_format(struct brw_context * brw,mesa_format format,bool is_render_target)213 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
214 bool is_render_target)
215 {
216 switch (format) {
217 case MESA_FORMAT_NONE:
218 return ISL_FORMAT_UNSUPPORTED;
219 case MESA_FORMAT_S_UINT8:
220 return ISL_FORMAT_R8_UINT;
221 case MESA_FORMAT_Z24_UNORM_X8_UINT:
222 case MESA_FORMAT_Z24_UNORM_S8_UINT:
223 return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
224 case MESA_FORMAT_Z_FLOAT32:
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
226 return ISL_FORMAT_R32_FLOAT;
227 case MESA_FORMAT_Z_UNORM16:
228 return ISL_FORMAT_R16_UNORM;
229 default:
230 if (is_render_target) {
231 assert(brw_blorp_supports_dst_format(brw, format));
232 if (brw->mesa_format_supports_render[format]) {
233 return brw->mesa_to_isl_render_format[format];
234 } else {
235 return brw_isl_format_for_mesa_format(format);
236 }
237 } else {
238 /* Some destinations (is_render_target == true) are supported by
239 * blorp even though we technically can't render to them.
240 */
241 return brw_isl_format_for_mesa_format(format);
242 }
243 }
244 }
245
246 /**
247 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
248 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
249 *
250 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
251 * 0 1 2 3 4 5
252 * 4 5 6 7 0 1
253 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
254 *
255 * which is simply adding 4 then modding by 8 (or anding with 7).
256 *
257 * We then may need to apply workarounds for textureGather hardware bugs.
258 */
259 static enum isl_channel_select
swizzle_to_scs(GLenum swizzle)260 swizzle_to_scs(GLenum swizzle)
261 {
262 return (enum isl_channel_select)((swizzle + 4) & 7);
263 }
264
265 /**
266 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
267 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
268 * the physical layer holding sample 0. So, for example, if
269 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
270 * 4*n.
271 */
272 void
brw_blorp_blit_miptrees(struct brw_context * brw,struct intel_mipmap_tree * src_mt,unsigned src_level,unsigned src_layer,mesa_format src_format,int src_swizzle,struct intel_mipmap_tree * dst_mt,unsigned dst_level,unsigned dst_layer,mesa_format dst_format,float src_x0,float src_y0,float src_x1,float src_y1,float dst_x0,float dst_y0,float dst_x1,float dst_y1,GLenum gl_filter,bool mirror_x,bool mirror_y,bool decode_srgb,bool encode_srgb)273 brw_blorp_blit_miptrees(struct brw_context *brw,
274 struct intel_mipmap_tree *src_mt,
275 unsigned src_level, unsigned src_layer,
276 mesa_format src_format, int src_swizzle,
277 struct intel_mipmap_tree *dst_mt,
278 unsigned dst_level, unsigned dst_layer,
279 mesa_format dst_format,
280 float src_x0, float src_y0,
281 float src_x1, float src_y1,
282 float dst_x0, float dst_y0,
283 float dst_x1, float dst_y1,
284 GLenum gl_filter, bool mirror_x, bool mirror_y,
285 bool decode_srgb, bool encode_srgb)
286 {
287 const struct gen_device_info *devinfo = &brw->screen->devinfo;
288
289 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f) "
290 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
291 __func__,
292 src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
293 src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
294 dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format), dst_mt,
295 dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
296 mirror_x, mirror_y);
297
298 if (src_format == MESA_FORMAT_NONE)
299 src_format = src_mt->format;
300
301 if (dst_format == MESA_FORMAT_NONE)
302 dst_format = dst_mt->format;
303
304 if (!decode_srgb)
305 src_format = _mesa_get_srgb_format_linear(src_format);
306
307 if (!encode_srgb)
308 dst_format = _mesa_get_srgb_format_linear(dst_format);
309
310 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
311 * texture, the above code configures the source format for L32_FLOAT or
312 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
313 * the SAMPLE message appears to handle multisampled L32_FLOAT and
314 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
315 * around the problem by using a source format of R32_FLOAT. This
316 * shouldn't affect rendering correctness, since the destination format is
317 * R32_FLOAT, so only the contents of the red channel matters.
318 */
319 if (devinfo->gen == 6 &&
320 src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
321 src_mt->format == dst_mt->format &&
322 (dst_format == MESA_FORMAT_L_FLOAT32 ||
323 dst_format == MESA_FORMAT_I_FLOAT32)) {
324 src_format = dst_format = MESA_FORMAT_R_FLOAT32;
325 }
326
327 enum blorp_filter blorp_filter;
328 if (fabsf(dst_x1 - dst_x0) == fabsf(src_x1 - src_x0) &&
329 fabsf(dst_y1 - dst_y0) == fabsf(src_y1 - src_y0)) {
330 if (src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1) {
331 /* From the OpenGL ES 3.2 specification, section 16.2.1:
332 *
333 * "If the read framebuffer is multisampled (its effective value
334 * of SAMPLE_BUFFERS is one) and the draw framebuffer is not (its
335 * value of SAMPLE_BUFFERS is zero), the samples corresponding to
336 * each pixel location in the source are converted to a single
337 * sample before being written to the destination. The filter
338 * parameter is ignored. If the source formats are integer types
339 * or stencil values, a single sample’s value is selected for each
340 * pixel. If the source formats are floating-point or normalized
341 * types, the sample values for each pixel are resolved in an
342 * implementation-dependent manner. If the source formats are
343 * depth values, sample values are resolved in an implementation-
344 * dependent manner where the result will be between the minimum
345 * and maximum depth values in the pixel."
346 *
347 * For depth and stencil resolves, we choose to always use the value
348 * at sample 0.
349 */
350 GLenum base_format = _mesa_get_format_base_format(src_mt->format);
351 if (base_format == GL_DEPTH_COMPONENT ||
352 base_format == GL_STENCIL_INDEX ||
353 base_format == GL_DEPTH_STENCIL ||
354 _mesa_is_format_integer(src_mt->format)) {
355 /* The OpenGL ES 3.2 spec says:
356 *
357 * "If the source formats are integer types or stencil values,
358 * a single sample's value is selected for each pixel."
359 *
360 * Just take sample 0 in this case.
361 */
362 blorp_filter = BLORP_FILTER_SAMPLE_0;
363 } else {
364 blorp_filter = BLORP_FILTER_AVERAGE;
365 }
366 } else {
367 /* From the OpenGL 4.6 specification, section 18.3.1:
368 *
369 * "If the source and destination dimensions are identical, no
370 * filtering is applied."
371 *
372 * Using BLORP_FILTER_NONE will also handle the upsample case by
373 * replicating the one value in the source to all values in the
374 * destination.
375 */
376 blorp_filter = BLORP_FILTER_NONE;
377 }
378 } else if (gl_filter == GL_LINEAR ||
379 gl_filter == GL_SCALED_RESOLVE_FASTEST_EXT ||
380 gl_filter == GL_SCALED_RESOLVE_NICEST_EXT) {
381 blorp_filter = BLORP_FILTER_BILINEAR;
382 } else {
383 blorp_filter = BLORP_FILTER_NEAREST;
384 }
385
386 enum isl_format src_isl_format =
387 brw_blorp_to_isl_format(brw, src_format, false);
388 enum isl_aux_usage src_aux_usage =
389 intel_miptree_texture_aux_usage(brw, src_mt, src_isl_format,
390 0 /* The astc5x5 WA isn't needed */);
391 /* We do format workarounds for some depth formats so we can't reliably
392 * sample with HiZ. One of these days, we should fix that.
393 */
394 if (src_aux_usage == ISL_AUX_USAGE_HIZ && src_mt->format != src_format)
395 src_aux_usage = ISL_AUX_USAGE_NONE;
396 const bool src_clear_supported =
397 src_aux_usage != ISL_AUX_USAGE_NONE && src_mt->format == src_format;
398 intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
399 src_aux_usage, src_clear_supported);
400
401 enum isl_format dst_isl_format =
402 brw_blorp_to_isl_format(brw, dst_format, true);
403 enum isl_aux_usage dst_aux_usage =
404 intel_miptree_render_aux_usage(brw, dst_mt, dst_isl_format,
405 false, false);
406 const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
407 intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
408 dst_aux_usage, dst_clear_supported);
409
410 struct blorp_surf src_surf, dst_surf;
411 blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false,
412 &src_level, src_layer, 1);
413 blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true,
414 &dst_level, dst_layer, 1);
415
416 struct isl_swizzle src_isl_swizzle = {
417 .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
418 .g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)),
419 .b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)),
420 .a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)),
421 };
422
423 struct blorp_batch batch;
424 blorp_batch_init(&brw->blorp, &batch, brw, 0);
425 blorp_blit(&batch, &src_surf, src_level, src_layer,
426 src_isl_format, src_isl_swizzle,
427 &dst_surf, dst_level, dst_layer,
428 dst_isl_format, ISL_SWIZZLE_IDENTITY,
429 src_x0, src_y0, src_x1, src_y1,
430 dst_x0, dst_y0, dst_x1, dst_y1,
431 blorp_filter, mirror_x, mirror_y);
432 blorp_batch_finish(&batch);
433
434 intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
435 dst_aux_usage);
436 }
437
438 void
brw_blorp_copy_miptrees(struct brw_context * brw,struct intel_mipmap_tree * src_mt,unsigned src_level,unsigned src_layer,struct intel_mipmap_tree * dst_mt,unsigned dst_level,unsigned dst_layer,unsigned src_x,unsigned src_y,unsigned dst_x,unsigned dst_y,unsigned src_width,unsigned src_height)439 brw_blorp_copy_miptrees(struct brw_context *brw,
440 struct intel_mipmap_tree *src_mt,
441 unsigned src_level, unsigned src_layer,
442 struct intel_mipmap_tree *dst_mt,
443 unsigned dst_level, unsigned dst_layer,
444 unsigned src_x, unsigned src_y,
445 unsigned dst_x, unsigned dst_y,
446 unsigned src_width, unsigned src_height)
447 {
448 const struct gen_device_info *devinfo = &brw->screen->devinfo;
449
450 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
451 "to %dx %s mt %p %d %d (%d,%d)\n",
452 __func__,
453 src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
454 src_level, src_layer, src_x, src_y, src_width, src_height,
455 dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format), dst_mt,
456 dst_level, dst_layer, dst_x, dst_y);
457
458 enum isl_aux_usage src_aux_usage, dst_aux_usage;
459 bool src_clear_supported, dst_clear_supported;
460
461 switch (src_mt->aux_usage) {
462 case ISL_AUX_USAGE_HIZ:
463 if (intel_miptree_sample_with_hiz(brw, src_mt)) {
464 src_aux_usage = src_mt->aux_usage;
465 src_clear_supported = true;
466 } else {
467 src_aux_usage = ISL_AUX_USAGE_NONE;
468 src_clear_supported = false;
469 }
470 break;
471 case ISL_AUX_USAGE_MCS:
472 case ISL_AUX_USAGE_CCS_E:
473 src_aux_usage = src_mt->aux_usage;
474 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
475 * we're going to re-interpret the format as an integer format possibly
476 * with a different number of components, we can't handle clear colors
477 * until gen9.
478 */
479 src_clear_supported = devinfo->gen >= 9;
480 break;
481 default:
482 src_aux_usage = ISL_AUX_USAGE_NONE;
483 src_clear_supported = false;
484 break;
485 }
486
487 switch (dst_mt->aux_usage) {
488 case ISL_AUX_USAGE_MCS:
489 case ISL_AUX_USAGE_CCS_E:
490 dst_aux_usage = dst_mt->aux_usage;
491 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
492 * we're going to re-interpret the format as an integer format possibly
493 * with a different number of components, we can't handle clear colors
494 * until gen9.
495 */
496 dst_clear_supported = devinfo->gen >= 9;
497 break;
498 default:
499 dst_aux_usage = ISL_AUX_USAGE_NONE;
500 dst_clear_supported = false;
501 break;
502 }
503
504 intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
505 src_aux_usage, src_clear_supported);
506 intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
507 dst_aux_usage, dst_clear_supported);
508
509 struct blorp_surf src_surf, dst_surf;
510 blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false,
511 &src_level, src_layer, 1);
512 blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true,
513 &dst_level, dst_layer, 1);
514
515 /* The hardware seems to have issues with having a two different format
516 * views of the same texture in the sampler cache at the same time. It's
517 * unclear exactly what the issue is but it hurts glCopyImageSubData
518 * particularly badly because it does a lot of format reinterprets. We
519 * badly need better understanding of the issue and a better fix but this
520 * works for now and fixes CTS tests.
521 *
522 * TODO: Remove this hack!
523 */
524 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL |
525 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
526
527 struct blorp_batch batch;
528 blorp_batch_init(&brw->blorp, &batch, brw, 0);
529 blorp_copy(&batch, &src_surf, src_level, src_layer,
530 &dst_surf, dst_level, dst_layer,
531 src_x, src_y, dst_x, dst_y, src_width, src_height);
532 blorp_batch_finish(&batch);
533
534 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL |
535 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
536
537 intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
538 dst_aux_usage);
539 }
540
541 void
brw_blorp_copy_buffers(struct brw_context * brw,struct brw_bo * src_bo,unsigned src_offset,struct brw_bo * dst_bo,unsigned dst_offset,unsigned size)542 brw_blorp_copy_buffers(struct brw_context *brw,
543 struct brw_bo *src_bo,
544 unsigned src_offset,
545 struct brw_bo *dst_bo,
546 unsigned dst_offset,
547 unsigned size)
548 {
549 DBG("%s %d bytes from %p[%d] to %p[%d]",
550 __func__, size, src_bo, src_offset, dst_bo, dst_offset);
551
552 struct blorp_batch batch;
553 struct blorp_address src = { .buffer = src_bo, .offset = src_offset };
554 struct blorp_address dst = { .buffer = dst_bo, .offset = dst_offset };
555
556 blorp_batch_init(&brw->blorp, &batch, brw, 0);
557 blorp_buffer_copy(&batch, src, dst, size);
558 blorp_batch_finish(&batch);
559 }
560
561
562 static struct intel_mipmap_tree *
find_miptree(GLbitfield buffer_bit,struct intel_renderbuffer * irb)563 find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb)
564 {
565 struct intel_mipmap_tree *mt = irb->mt;
566 if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt)
567 mt = mt->stencil_mt;
568 return mt;
569 }
570
571 static int
blorp_get_texture_swizzle(const struct intel_renderbuffer * irb)572 blorp_get_texture_swizzle(const struct intel_renderbuffer *irb)
573 {
574 return irb->Base.Base._BaseFormat == GL_RGB ?
575 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) :
576 SWIZZLE_XYZW;
577 }
578
579 static void
do_blorp_blit(struct brw_context * brw,GLbitfield buffer_bit,struct intel_renderbuffer * src_irb,mesa_format src_format,struct intel_renderbuffer * dst_irb,mesa_format dst_format,GLfloat srcX0,GLfloat srcY0,GLfloat srcX1,GLfloat srcY1,GLfloat dstX0,GLfloat dstY0,GLfloat dstX1,GLfloat dstY1,GLenum filter,bool mirror_x,bool mirror_y)580 do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
581 struct intel_renderbuffer *src_irb, mesa_format src_format,
582 struct intel_renderbuffer *dst_irb, mesa_format dst_format,
583 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
584 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
585 GLenum filter, bool mirror_x, bool mirror_y)
586 {
587 const struct gl_context *ctx = &brw->ctx;
588
589 /* Find source/dst miptrees */
590 struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
591 struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
592
593 const bool do_srgb = ctx->Color.sRGBEnabled;
594
595 /* Do the blit */
596 brw_blorp_blit_miptrees(brw,
597 src_mt, src_irb->mt_level, src_irb->mt_layer,
598 src_format, blorp_get_texture_swizzle(src_irb),
599 dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
600 dst_format,
601 srcX0, srcY0, srcX1, srcY1,
602 dstX0, dstY0, dstX1, dstY1,
603 filter, mirror_x, mirror_y,
604 do_srgb, do_srgb);
605
606 dst_irb->need_downsample = true;
607 }
608
609 static bool
try_blorp_blit(struct brw_context * brw,const struct gl_framebuffer * read_fb,const struct gl_framebuffer * draw_fb,GLfloat srcX0,GLfloat srcY0,GLfloat srcX1,GLfloat srcY1,GLfloat dstX0,GLfloat dstY0,GLfloat dstX1,GLfloat dstY1,GLenum filter,GLbitfield buffer_bit)610 try_blorp_blit(struct brw_context *brw,
611 const struct gl_framebuffer *read_fb,
612 const struct gl_framebuffer *draw_fb,
613 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
614 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
615 GLenum filter, GLbitfield buffer_bit)
616 {
617 const struct gen_device_info *devinfo = &brw->screen->devinfo;
618 struct gl_context *ctx = &brw->ctx;
619
620 /* Sync up the state of window system buffers. We need to do this before
621 * we go looking for the buffers.
622 */
623 intel_prepare_render(brw);
624
625 bool mirror_x, mirror_y;
626 if (brw_meta_mirror_clip_and_scissor(ctx, read_fb, draw_fb,
627 &srcX0, &srcY0, &srcX1, &srcY1,
628 &dstX0, &dstY0, &dstX1, &dstY1,
629 &mirror_x, &mirror_y))
630 return true;
631
632 /* Find buffers */
633 struct intel_renderbuffer *src_irb;
634 struct intel_renderbuffer *dst_irb;
635 struct intel_mipmap_tree *src_mt;
636 struct intel_mipmap_tree *dst_mt;
637 switch (buffer_bit) {
638 case GL_COLOR_BUFFER_BIT:
639 src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer);
640 for (unsigned i = 0; i < draw_fb->_NumColorDrawBuffers; ++i) {
641 dst_irb = intel_renderbuffer(draw_fb->_ColorDrawBuffers[i]);
642 if (dst_irb)
643 do_blorp_blit(brw, buffer_bit,
644 src_irb, src_irb->Base.Base.Format,
645 dst_irb, dst_irb->Base.Base.Format,
646 srcX0, srcY0, srcX1, srcY1,
647 dstX0, dstY0, dstX1, dstY1,
648 filter, mirror_x, mirror_y);
649 }
650 break;
651 case GL_DEPTH_BUFFER_BIT:
652 src_irb =
653 intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
654 dst_irb =
655 intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
656 src_mt = find_miptree(buffer_bit, src_irb);
657 dst_mt = find_miptree(buffer_bit, dst_irb);
658
659 /* We also can't handle any combined depth-stencil formats because we
660 * have to reinterpret as a color format.
661 */
662 if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
663 _mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
664 return false;
665
666 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
667 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
668 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
669 filter, mirror_x, mirror_y);
670 break;
671 case GL_STENCIL_BUFFER_BIT:
672 /* Blorp doesn't support combined depth stencil which is all we have
673 * prior to gen6.
674 */
675 if (devinfo->gen < 6)
676 return false;
677
678 src_irb =
679 intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
680 dst_irb =
681 intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
682 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
683 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
684 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
685 filter, mirror_x, mirror_y);
686 break;
687 default:
688 unreachable("not reached");
689 }
690
691 return true;
692 }
693
694 static void
apply_y_flip(int * y0,int * y1,int height)695 apply_y_flip(int *y0, int *y1, int height)
696 {
697 int tmp = height - *y0;
698 *y0 = height - *y1;
699 *y1 = tmp;
700 }
701
702 bool
brw_blorp_copytexsubimage(struct brw_context * brw,struct gl_renderbuffer * src_rb,struct gl_texture_image * dst_image,int slice,int srcX0,int srcY0,int dstX0,int dstY0,int width,int height)703 brw_blorp_copytexsubimage(struct brw_context *brw,
704 struct gl_renderbuffer *src_rb,
705 struct gl_texture_image *dst_image,
706 int slice,
707 int srcX0, int srcY0,
708 int dstX0, int dstY0,
709 int width, int height)
710 {
711 struct gl_context *ctx = &brw->ctx;
712 struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
713 struct intel_texture_image *intel_image = intel_texture_image(dst_image);
714
715 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
716 if (brw->ctx._ImageTransferState)
717 return false;
718
719 /* Sync up the state of window system buffers. We need to do this before
720 * we go looking at the src renderbuffer's miptree.
721 */
722 intel_prepare_render(brw);
723
724 struct intel_mipmap_tree *src_mt = src_irb->mt;
725 struct intel_mipmap_tree *dst_mt = intel_image->mt;
726
727 /* We can't handle any combined depth-stencil formats because we have to
728 * reinterpret as a color format.
729 */
730 if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
731 _mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
732 return false;
733
734 if (!brw_blorp_supports_dst_format(brw, dst_image->TexFormat))
735 return false;
736
737 /* Source clipping shouldn't be necessary, since copytexsubimage (in
738 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
739 * takes care of it.
740 *
741 * Destination clipping shouldn't be necessary since the restrictions on
742 * glCopyTexSubImage prevent the user from specifying a destination rectangle
743 * that falls outside the bounds of the destination texture.
744 * See error_check_subtexture_dimensions().
745 */
746
747 int srcY1 = srcY0 + height;
748 int srcX1 = srcX0 + width;
749 int dstX1 = dstX0 + width;
750 int dstY1 = dstY0 + height;
751
752 /* Account for the fact that in the system framebuffer, the origin is at
753 * the lower left.
754 */
755 bool mirror_y = ctx->ReadBuffer->FlipY;
756 if (mirror_y)
757 apply_y_flip(&srcY0, &srcY1, src_rb->Height);
758
759 /* Account for face selection and texture view MinLayer */
760 int dst_slice = slice + dst_image->TexObject->MinLayer + dst_image->Face;
761 int dst_level = dst_image->Level + dst_image->TexObject->MinLevel;
762
763 brw_blorp_blit_miptrees(brw,
764 src_mt, src_irb->mt_level, src_irb->mt_layer,
765 src_rb->Format, blorp_get_texture_swizzle(src_irb),
766 dst_mt, dst_level, dst_slice,
767 dst_image->TexFormat,
768 srcX0, srcY0, srcX1, srcY1,
769 dstX0, dstY0, dstX1, dstY1,
770 GL_NEAREST, false, mirror_y,
771 false, false);
772
773 /* If we're copying to a packed depth stencil texture and the source
774 * framebuffer has separate stencil, we need to also copy the stencil data
775 * over.
776 */
777 src_rb = ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
778 if (_mesa_get_format_bits(dst_image->TexFormat, GL_STENCIL_BITS) > 0 &&
779 src_rb != NULL) {
780 src_irb = intel_renderbuffer(src_rb);
781 src_mt = src_irb->mt;
782
783 if (src_mt->stencil_mt)
784 src_mt = src_mt->stencil_mt;
785 if (dst_mt->stencil_mt)
786 dst_mt = dst_mt->stencil_mt;
787
788 if (src_mt != dst_mt) {
789 brw_blorp_blit_miptrees(brw,
790 src_mt, src_irb->mt_level, src_irb->mt_layer,
791 src_mt->format,
792 blorp_get_texture_swizzle(src_irb),
793 dst_mt, dst_level, dst_slice,
794 dst_mt->format,
795 srcX0, srcY0, srcX1, srcY1,
796 dstX0, dstY0, dstX1, dstY1,
797 GL_NEAREST, false, mirror_y,
798 false, false);
799 }
800 }
801
802 return true;
803 }
804
805
806 GLbitfield
brw_blorp_framebuffer(struct brw_context * brw,struct gl_framebuffer * readFb,struct gl_framebuffer * drawFb,GLint srcX0,GLint srcY0,GLint srcX1,GLint srcY1,GLint dstX0,GLint dstY0,GLint dstX1,GLint dstY1,GLbitfield mask,GLenum filter)807 brw_blorp_framebuffer(struct brw_context *brw,
808 struct gl_framebuffer *readFb,
809 struct gl_framebuffer *drawFb,
810 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
811 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
812 GLbitfield mask, GLenum filter)
813 {
814 static GLbitfield buffer_bits[] = {
815 GL_COLOR_BUFFER_BIT,
816 GL_DEPTH_BUFFER_BIT,
817 GL_STENCIL_BUFFER_BIT,
818 };
819
820 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) {
821 if ((mask & buffer_bits[i]) &&
822 try_blorp_blit(brw, readFb, drawFb,
823 srcX0, srcY0, srcX1, srcY1,
824 dstX0, dstY0, dstX1, dstY1,
825 filter, buffer_bits[i])) {
826 mask &= ~buffer_bits[i];
827 }
828 }
829
830 /* try_blorp_blit should always be successful for color blits. */
831 assert(!(mask & GL_COLOR_BUFFER_BIT));
832 return mask;
833 }
834
835 static struct brw_bo *
blorp_get_client_bo(struct brw_context * brw,unsigned w,unsigned h,unsigned d,GLenum target,GLenum format,GLenum type,const void * pixels,const struct gl_pixelstore_attrib * packing,uint32_t * offset_out,uint32_t * row_stride_out,uint32_t * image_stride_out,bool read_only)836 blorp_get_client_bo(struct brw_context *brw,
837 unsigned w, unsigned h, unsigned d,
838 GLenum target, GLenum format, GLenum type,
839 const void *pixels,
840 const struct gl_pixelstore_attrib *packing,
841 uint32_t *offset_out, uint32_t *row_stride_out,
842 uint32_t *image_stride_out, bool read_only)
843 {
844 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
845 const GLuint dims = _mesa_get_texture_dimensions(target);
846 const uint32_t first_pixel = _mesa_image_offset(dims, packing, w, h,
847 format, type, 0, 0, 0);
848 const uint32_t last_pixel = _mesa_image_offset(dims, packing, w, h,
849 format, type,
850 d - 1, h - 1, w);
851 const uint32_t stride = _mesa_image_row_stride(packing, w, format, type);
852 const uint32_t size = last_pixel - first_pixel;
853
854 *row_stride_out = stride;
855 *image_stride_out = _mesa_image_image_stride(packing, w, h, format, type);
856
857 if (packing->BufferObj) {
858 const uint32_t offset = first_pixel + (intptr_t)pixels;
859
860 if (!read_only) {
861 const int32_t cpp = _mesa_bytes_per_pixel(format, type);
862 assert(cpp > 0);
863
864 if ((offset % cpp) || (stride % cpp)) {
865 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
866 return NULL;
867 }
868 }
869
870 /* This is a user-provided PBO. We just need to get the BO out */
871 struct intel_buffer_object *intel_pbo =
872 intel_buffer_object(packing->BufferObj);
873 struct brw_bo *bo =
874 intel_bufferobj_buffer(brw, intel_pbo, offset, size, !read_only);
875
876 /* We take a reference to the BO so that the caller can just always
877 * unref without having to worry about whether it's a user PBO or one
878 * we created.
879 */
880 brw_bo_reference(bo);
881
882 *offset_out = offset;
883 return bo;
884 } else {
885 /* Someone should have already checked that there is data to upload. */
886 assert(pixels);
887
888 /* Creating a temp buffer currently only works for upload */
889 assert(read_only);
890
891 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
892 * data which we need to copy into a BO.
893 */
894 struct brw_bo *bo =
895 brw_bo_alloc(brw->bufmgr, "tmp_tex_subimage_src", size,
896 BRW_MEMZONE_OTHER);
897 if (bo == NULL) {
898 perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
899 size);
900 return NULL;
901 }
902
903 if (brw_bo_subdata(bo, 0, size, pixels + first_pixel)) {
904 perf_debug("intel_texsubimage: temp bo upload failed\n");
905 brw_bo_unreference(bo);
906 return NULL;
907 }
908
909 *offset_out = 0;
910 return bo;
911 }
912 }
913
914 /* Consider all the restrictions and determine the format of the source. */
915 static mesa_format
blorp_get_client_format(struct brw_context * brw,GLenum format,GLenum type,const struct gl_pixelstore_attrib * packing)916 blorp_get_client_format(struct brw_context *brw,
917 GLenum format, GLenum type,
918 const struct gl_pixelstore_attrib *packing)
919 {
920 if (brw->ctx._ImageTransferState)
921 return MESA_FORMAT_NONE;
922
923 if (packing->SwapBytes || packing->LsbFirst || packing->Invert) {
924 perf_debug("intel_texsubimage_blorp: unsupported gl_pixelstore_attrib\n");
925 return MESA_FORMAT_NONE;
926 }
927
928 if (format != GL_RED &&
929 format != GL_RG &&
930 format != GL_RGB &&
931 format != GL_BGR &&
932 format != GL_RGBA &&
933 format != GL_BGRA &&
934 format != GL_ALPHA &&
935 format != GL_RED_INTEGER &&
936 format != GL_RG_INTEGER &&
937 format != GL_RGB_INTEGER &&
938 format != GL_BGR_INTEGER &&
939 format != GL_RGBA_INTEGER &&
940 format != GL_BGRA_INTEGER) {
941 perf_debug("intel_texsubimage_blorp: %s not supported",
942 _mesa_enum_to_string(format));
943 return MESA_FORMAT_NONE;
944 }
945
946 return _mesa_tex_format_from_format_and_type(&brw->ctx, format, type);
947 }
948
949 bool
brw_blorp_upload_miptree(struct brw_context * brw,struct intel_mipmap_tree * dst_mt,mesa_format dst_format,uint32_t level,uint32_t x,uint32_t y,uint32_t z,uint32_t width,uint32_t height,uint32_t depth,GLenum target,GLenum format,GLenum type,const void * pixels,const struct gl_pixelstore_attrib * packing)950 brw_blorp_upload_miptree(struct brw_context *brw,
951 struct intel_mipmap_tree *dst_mt,
952 mesa_format dst_format,
953 uint32_t level, uint32_t x, uint32_t y, uint32_t z,
954 uint32_t width, uint32_t height, uint32_t depth,
955 GLenum target, GLenum format, GLenum type,
956 const void *pixels,
957 const struct gl_pixelstore_attrib *packing)
958 {
959 const mesa_format src_format =
960 blorp_get_client_format(brw, format, type, packing);
961 if (src_format == MESA_FORMAT_NONE)
962 return false;
963
964 if (!brw->mesa_format_supports_render[dst_format]) {
965 perf_debug("intel_texsubimage: can't use %s as render target\n",
966 _mesa_get_format_name(dst_format));
967 return false;
968 }
969
970 uint32_t src_offset, src_row_stride, src_image_stride;
971 struct brw_bo *src_bo =
972 blorp_get_client_bo(brw, width, height, depth,
973 target, format, type, pixels, packing,
974 &src_offset, &src_row_stride,
975 &src_image_stride, true);
976 if (src_bo == NULL)
977 return false;
978
979 /* Now that source is offset to correct starting point, adjust the
980 * given dimensions to treat 1D arrays as 2D.
981 */
982 if (target == GL_TEXTURE_1D_ARRAY) {
983 assert(depth == 1);
984 assert(z == 0);
985 depth = height;
986 height = 1;
987 z = y;
988 y = 0;
989 src_image_stride = src_row_stride;
990 }
991
992 intel_miptree_check_level_layer(dst_mt, level, z + depth - 1);
993
994 bool result = false;
995
996 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
997 * in case of linear buffers hardware wants image arrays to be aligned by
998 * four rows. This way hardware only gets one image at a time and any
999 * source alignment will do.
1000 */
1001 for (unsigned i = 0; i < depth; ++i) {
1002 struct intel_mipmap_tree *src_mt = intel_miptree_create_for_bo(
1003 brw, src_bo, src_format,
1004 src_offset + i * src_image_stride,
1005 width, height, 1,
1006 src_row_stride,
1007 ISL_TILING_LINEAR, 0);
1008
1009 if (!src_mt) {
1010 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1011 goto err;
1012 }
1013
1014 /* In case exact match is needed, copy using equivalent UINT formats
1015 * preventing hardware from changing presentation for SNORM -1.
1016 */
1017 if (src_mt->format == dst_format) {
1018 brw_blorp_copy_miptrees(brw, src_mt, 0, 0,
1019 dst_mt, level, z + i,
1020 0, 0, x, y, width, height);
1021 } else {
1022 brw_blorp_blit_miptrees(brw, src_mt, 0, 0,
1023 src_format, SWIZZLE_XYZW,
1024 dst_mt, level, z + i,
1025 dst_format,
1026 0, 0, width, height,
1027 x, y, x + width, y + height,
1028 GL_NEAREST, false, false, false, false);
1029 }
1030
1031 intel_miptree_release(&src_mt);
1032 }
1033
1034 result = true;
1035
1036 err:
1037 brw_bo_unreference(src_bo);
1038
1039 return result;
1040 }
1041
1042 bool
brw_blorp_download_miptree(struct brw_context * brw,struct intel_mipmap_tree * src_mt,mesa_format src_format,uint32_t src_swizzle,uint32_t level,uint32_t x,uint32_t y,uint32_t z,uint32_t width,uint32_t height,uint32_t depth,GLenum target,GLenum format,GLenum type,bool y_flip,const void * pixels,const struct gl_pixelstore_attrib * packing)1043 brw_blorp_download_miptree(struct brw_context *brw,
1044 struct intel_mipmap_tree *src_mt,
1045 mesa_format src_format, uint32_t src_swizzle,
1046 uint32_t level, uint32_t x, uint32_t y, uint32_t z,
1047 uint32_t width, uint32_t height, uint32_t depth,
1048 GLenum target, GLenum format, GLenum type,
1049 bool y_flip, const void *pixels,
1050 const struct gl_pixelstore_attrib *packing)
1051 {
1052 const mesa_format dst_format =
1053 blorp_get_client_format(brw, format, type, packing);
1054 if (dst_format == MESA_FORMAT_NONE)
1055 return false;
1056
1057 if (!brw->mesa_format_supports_render[dst_format]) {
1058 perf_debug("intel_texsubimage: can't use %s as render target\n",
1059 _mesa_get_format_name(dst_format));
1060 return false;
1061 }
1062
1063 /* We can't fetch from LUMINANCE or intensity as that would require a
1064 * non-trivial swizzle.
1065 */
1066 switch (_mesa_get_format_base_format(src_format)) {
1067 case GL_LUMINANCE:
1068 case GL_LUMINANCE_ALPHA:
1069 case GL_INTENSITY:
1070 return false;
1071 default:
1072 break;
1073 }
1074
1075 /* This pass only works for PBOs */
1076 assert(packing->BufferObj);
1077
1078 uint32_t dst_offset, dst_row_stride, dst_image_stride;
1079 struct brw_bo *dst_bo =
1080 blorp_get_client_bo(brw, width, height, depth,
1081 target, format, type, pixels, packing,
1082 &dst_offset, &dst_row_stride,
1083 &dst_image_stride, false);
1084 if (dst_bo == NULL)
1085 return false;
1086
1087 /* Now that source is offset to correct starting point, adjust the
1088 * given dimensions to treat 1D arrays as 2D.
1089 */
1090 if (target == GL_TEXTURE_1D_ARRAY) {
1091 assert(depth == 1);
1092 assert(z == 0);
1093 depth = height;
1094 height = 1;
1095 z = y;
1096 y = 0;
1097 dst_image_stride = dst_row_stride;
1098 }
1099
1100 intel_miptree_check_level_layer(src_mt, level, z + depth - 1);
1101
1102 int y0 = y;
1103 int y1 = y + height;
1104 if (y_flip) {
1105 apply_y_flip(&y0, &y1, minify(src_mt->surf.phys_level0_sa.height,
1106 level - src_mt->first_level));
1107 }
1108
1109 bool result = false;
1110
1111 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1112 * in case of linear buffers hardware wants image arrays to be aligned by
1113 * four rows. This way hardware only gets one image at a time and any
1114 * source alignment will do.
1115 */
1116 for (unsigned i = 0; i < depth; ++i) {
1117 struct intel_mipmap_tree *dst_mt = intel_miptree_create_for_bo(
1118 brw, dst_bo, dst_format,
1119 dst_offset + i * dst_image_stride,
1120 width, height, 1,
1121 dst_row_stride,
1122 ISL_TILING_LINEAR, 0);
1123
1124 if (!dst_mt) {
1125 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1126 goto err;
1127 }
1128
1129 /* In case exact match is needed, copy using equivalent UINT formats
1130 * preventing hardware from changing presentation for SNORM -1.
1131 */
1132 if (dst_mt->format == src_format && !y_flip &&
1133 src_swizzle == SWIZZLE_XYZW) {
1134 brw_blorp_copy_miptrees(brw, src_mt, level, z + i,
1135 dst_mt, 0, 0,
1136 x, y, 0, 0, width, height);
1137 } else {
1138 brw_blorp_blit_miptrees(brw, src_mt, level, z + i,
1139 src_format, src_swizzle,
1140 dst_mt, 0, 0, dst_format,
1141 x, y0, x + width, y1,
1142 0, 0, width, height,
1143 GL_NEAREST, false, y_flip, false, false);
1144 }
1145
1146 intel_miptree_release(&dst_mt);
1147 }
1148
1149 result = true;
1150
1151 /* As we implement PBO transfers by binding the user-provided BO as a
1152 * fake framebuffer and rendering to it. This breaks the invariant of the
1153 * GL that nothing is able to render to a BO, causing nondeterministic
1154 * corruption issues because the render cache is not coherent with a
1155 * number of other caches that the BO could potentially be bound to
1156 * afterwards.
1157 *
1158 * This could be solved in the same way that we guarantee texture
1159 * coherency after a texture is attached to a framebuffer and
1160 * rendered to, but that would involve checking *all* BOs bound to
1161 * the pipeline for the case we need to emit a cache flush due to
1162 * previous rendering to any of them -- Including vertex, index,
1163 * uniform, atomic counter, shader image, transform feedback,
1164 * indirect draw buffers, etc.
1165 *
1166 * That would increase the per-draw call overhead even though it's
1167 * very unlikely that any of the BOs bound to the pipeline has been
1168 * rendered to via a PBO at any point, so it seems better to just
1169 * flush here unconditionally.
1170 */
1171 brw_emit_mi_flush(brw);
1172
1173 err:
1174 brw_bo_unreference(dst_bo);
1175
1176 return result;
1177 }
1178
1179 static bool
set_write_disables(const struct intel_renderbuffer * irb,const unsigned color_mask,bool * color_write_disable)1180 set_write_disables(const struct intel_renderbuffer *irb,
1181 const unsigned color_mask, bool *color_write_disable)
1182 {
1183 /* Format information in the renderbuffer represents the requirements
1184 * given by the client. There are cases where the backing miptree uses,
1185 * for example, RGBA to represent RGBX. Since the client is only expecting
1186 * RGB we can treat alpha as not used and write whatever we like into it.
1187 */
1188 const GLenum base_format = irb->Base.Base._BaseFormat;
1189 const int components = _mesa_components_in_format(base_format);
1190 bool disables = false;
1191
1192 assert(components > 0);
1193
1194 for (int i = 0; i < components; i++) {
1195 color_write_disable[i] = !(color_mask & (1 << i));
1196 disables = disables || color_write_disable[i];
1197 }
1198
1199 return disables;
1200 }
1201
1202 static void
do_single_blorp_clear(struct brw_context * brw,struct gl_framebuffer * fb,struct gl_renderbuffer * rb,unsigned buf,bool partial_clear,bool encode_srgb)1203 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
1204 struct gl_renderbuffer *rb, unsigned buf,
1205 bool partial_clear, bool encode_srgb)
1206 {
1207 struct gl_context *ctx = &brw->ctx;
1208 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1209 uint32_t x0, x1, y0, y1;
1210
1211 mesa_format format = irb->Base.Base.Format;
1212 if (!encode_srgb)
1213 format = _mesa_get_srgb_format_linear(format);
1214 enum isl_format isl_format = brw->mesa_to_isl_render_format[format];
1215
1216 x0 = fb->_Xmin;
1217 x1 = fb->_Xmax;
1218 if (fb->FlipY) {
1219 y0 = rb->Height - fb->_Ymax;
1220 y1 = rb->Height - fb->_Ymin;
1221 } else {
1222 y0 = fb->_Ymin;
1223 y1 = fb->_Ymax;
1224 }
1225
1226 /* If the clear region is empty, just return. */
1227 if (x0 == x1 || y0 == y1)
1228 return;
1229
1230 bool can_fast_clear = !partial_clear;
1231
1232 if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
1233 can_fast_clear = false;
1234
1235 bool color_write_disable[4] = { false, false, false, false };
1236 if (set_write_disables(irb, GET_COLORMASK(ctx->Color.ColorMask, buf),
1237 color_write_disable))
1238 can_fast_clear = false;
1239
1240 /* We store clear colors as floats or uints as needed. If there are
1241 * texture views in play, the formats will not properly be respected
1242 * during resolves because the resolve operations only know about the
1243 * miptree and not the renderbuffer.
1244 */
1245 if (irb->Base.Base.Format != irb->mt->format)
1246 can_fast_clear = false;
1247
1248 if (!irb->mt->supports_fast_clear ||
1249 !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
1250 can_fast_clear = false;
1251
1252 /* Surface state can only record one fast clear color value. Therefore
1253 * unless different levels/layers agree on the color it can be used to
1254 * represent only single level/layer. Here it will be reserved for the
1255 * first slice (level 0, layer 0).
1256 */
1257 if (irb->layer_count > 1 || irb->mt_level || irb->mt_layer)
1258 can_fast_clear = false;
1259
1260 unsigned level = irb->mt_level;
1261 const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
1262
1263 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1264 */
1265 if (can_fast_clear && !irb->mt->aux_buf) {
1266 assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
1267 if (!intel_miptree_alloc_aux(brw, irb->mt)) {
1268 /* We're out of memory. Fall back to a non-fast clear. */
1269 can_fast_clear = false;
1270 }
1271 }
1272
1273 if (can_fast_clear) {
1274 const enum isl_aux_state aux_state =
1275 intel_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
1276 union isl_color_value clear_color =
1277 brw_meta_convert_fast_clear_color(brw, irb->mt,
1278 &ctx->Color.ClearColor);
1279
1280 /* If the buffer is already in ISL_AUX_STATE_CLEAR and the clear color
1281 * hasn't changed, the clear is redundant and can be skipped.
1282 */
1283 if (!intel_miptree_set_clear_color(brw, irb->mt, clear_color) &&
1284 aux_state == ISL_AUX_STATE_CLEAR) {
1285 return;
1286 }
1287
1288 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
1289 irb->mt, irb->mt_level, irb->mt_layer, num_layers);
1290
1291 /* We can't setup the blorp_surf until we've allocated the MCS above */
1292 struct blorp_surf surf;
1293 blorp_surf_for_miptree(brw, &surf, irb->mt, irb->mt->aux_usage, true,
1294 &level, irb->mt_layer, num_layers);
1295
1296 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1297 *
1298 * "Any transition from any value in {Clear, Render, Resolve} to a
1299 * different value in {Clear, Render, Resolve} requires end of pipe
1300 * synchronization."
1301 *
1302 * In other words, fast clear ops are not properly synchronized with
1303 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1304 * contents of the previous draw hit the render target before we resolve
1305 * and again afterwards to ensure that the resolve is complete before we
1306 * do any more regular drawing.
1307 */
1308 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
1309
1310 struct blorp_batch batch;
1311 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1312 blorp_fast_clear(&batch, &surf, isl_format_srgb_to_linear(isl_format),
1313 ISL_SWIZZLE_IDENTITY,
1314 level, irb->mt_layer, num_layers, x0, y0, x1, y1);
1315 blorp_batch_finish(&batch);
1316
1317 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
1318
1319 /* Now that the fast clear has occurred, put the buffer in
1320 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1321 * redundant clears.
1322 */
1323 intel_miptree_set_aux_state(brw, irb->mt, irb->mt_level,
1324 irb->mt_layer, num_layers,
1325 ISL_AUX_STATE_CLEAR);
1326 } else {
1327 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
1328 irb->mt, irb->mt_level, irb->mt_layer, num_layers);
1329
1330 enum isl_aux_usage aux_usage =
1331 intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
1332 false, false);
1333 intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
1334 num_layers, aux_usage);
1335
1336 struct blorp_surf surf;
1337 blorp_surf_for_miptree(brw, &surf, irb->mt, aux_usage, true,
1338 &level, irb->mt_layer, num_layers);
1339
1340 union isl_color_value clear_color;
1341 memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
1342
1343 struct blorp_batch batch;
1344 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1345 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
1346 level, irb->mt_layer, num_layers,
1347 x0, y0, x1, y1,
1348 clear_color, color_write_disable);
1349 blorp_batch_finish(&batch);
1350
1351 intel_miptree_finish_render(brw, irb->mt, level, irb->mt_layer,
1352 num_layers, aux_usage);
1353 }
1354
1355 return;
1356 }
1357
1358 void
brw_blorp_clear_color(struct brw_context * brw,struct gl_framebuffer * fb,GLbitfield mask,bool partial_clear,bool encode_srgb)1359 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
1360 GLbitfield mask, bool partial_clear, bool encode_srgb)
1361 {
1362 for (unsigned buf = 0; buf < fb->_NumColorDrawBuffers; buf++) {
1363 struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buf];
1364 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1365
1366 /* Only clear the buffers present in the provided mask */
1367 if (((1 << fb->_ColorDrawBufferIndexes[buf]) & mask) == 0)
1368 continue;
1369
1370 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1371 * the framebuffer can be complete with some attachments missing. In
1372 * this case the _ColorDrawBuffers pointer will be NULL.
1373 */
1374 if (rb == NULL)
1375 continue;
1376
1377 do_single_blorp_clear(brw, fb, rb, buf, partial_clear, encode_srgb);
1378 irb->need_downsample = true;
1379 }
1380
1381 return;
1382 }
1383
1384 void
brw_blorp_clear_depth_stencil(struct brw_context * brw,struct gl_framebuffer * fb,GLbitfield mask,bool partial_clear)1385 brw_blorp_clear_depth_stencil(struct brw_context *brw,
1386 struct gl_framebuffer *fb,
1387 GLbitfield mask, bool partial_clear)
1388 {
1389 const struct gl_context *ctx = &brw->ctx;
1390 struct gl_renderbuffer *depth_rb =
1391 fb->Attachment[BUFFER_DEPTH].Renderbuffer;
1392 struct gl_renderbuffer *stencil_rb =
1393 fb->Attachment[BUFFER_STENCIL].Renderbuffer;
1394
1395 if (!depth_rb || ctx->Depth.Mask == GL_FALSE)
1396 mask &= ~BUFFER_BIT_DEPTH;
1397
1398 if (!stencil_rb || (ctx->Stencil.WriteMask[0] & 0xff) == 0)
1399 mask &= ~BUFFER_BIT_STENCIL;
1400
1401 if (!(mask & (BUFFER_BITS_DEPTH_STENCIL)))
1402 return;
1403
1404 uint32_t x0, x1, y0, y1, rb_height;
1405 if (depth_rb) {
1406 rb_height = depth_rb->Height;
1407 if (stencil_rb) {
1408 assert(depth_rb->Width == stencil_rb->Width);
1409 assert(depth_rb->Height == stencil_rb->Height);
1410 }
1411 } else {
1412 assert(stencil_rb);
1413 rb_height = stencil_rb->Height;
1414 }
1415
1416 x0 = fb->_Xmin;
1417 x1 = fb->_Xmax;
1418 if (fb->FlipY) {
1419 y0 = rb_height - fb->_Ymax;
1420 y1 = rb_height - fb->_Ymin;
1421 } else {
1422 y0 = fb->_Ymin;
1423 y1 = fb->_Ymax;
1424 }
1425
1426 /* If the clear region is empty, just return. */
1427 if (x0 == x1 || y0 == y1)
1428 return;
1429
1430 uint32_t level = 0, start_layer = 0, num_layers;
1431 struct blorp_surf depth_surf, stencil_surf;
1432
1433 struct intel_mipmap_tree *depth_mt = NULL;
1434 if (mask & BUFFER_BIT_DEPTH) {
1435 struct intel_renderbuffer *irb = intel_renderbuffer(depth_rb);
1436 depth_mt = find_miptree(GL_DEPTH_BUFFER_BIT, irb);
1437
1438 level = irb->mt_level;
1439 start_layer = irb->mt_layer;
1440 num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
1441
1442 intel_miptree_prepare_depth(brw, depth_mt, level,
1443 start_layer, num_layers);
1444
1445 unsigned depth_level = level;
1446 blorp_surf_for_miptree(brw, &depth_surf, depth_mt, depth_mt->aux_usage,
1447 true, &depth_level, start_layer, num_layers);
1448 assert(depth_level == level);
1449 }
1450
1451 uint8_t stencil_mask = 0;
1452 struct intel_mipmap_tree *stencil_mt = NULL;
1453 if (mask & BUFFER_BIT_STENCIL) {
1454 struct intel_renderbuffer *irb = intel_renderbuffer(stencil_rb);
1455 stencil_mt = find_miptree(GL_STENCIL_BUFFER_BIT, irb);
1456
1457 if (mask & BUFFER_BIT_DEPTH) {
1458 assert(level == irb->mt_level);
1459 assert(start_layer == irb->mt_layer);
1460 assert(num_layers == fb->MaxNumLayers ? irb->layer_count : 1);
1461 }
1462
1463 level = irb->mt_level;
1464 start_layer = irb->mt_layer;
1465 num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
1466
1467 stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;
1468
1469 intel_miptree_prepare_access(brw, stencil_mt, level, 1,
1470 start_layer, num_layers,
1471 ISL_AUX_USAGE_NONE, false);
1472
1473 unsigned stencil_level = level;
1474 blorp_surf_for_miptree(brw, &stencil_surf, stencil_mt,
1475 ISL_AUX_USAGE_NONE, true,
1476 &stencil_level, start_layer, num_layers);
1477 }
1478
1479 assert((mask & BUFFER_BIT_DEPTH) || stencil_mask);
1480
1481 struct blorp_batch batch;
1482 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1483 blorp_clear_depth_stencil(&batch, &depth_surf, &stencil_surf,
1484 level, start_layer, num_layers,
1485 x0, y0, x1, y1,
1486 (mask & BUFFER_BIT_DEPTH), ctx->Depth.Clear,
1487 stencil_mask, ctx->Stencil.Clear);
1488 blorp_batch_finish(&batch);
1489
1490 if (mask & BUFFER_BIT_DEPTH) {
1491 intel_miptree_finish_depth(brw, depth_mt, level,
1492 start_layer, num_layers, true);
1493 }
1494
1495 if (stencil_mask) {
1496 intel_miptree_finish_write(brw, stencil_mt, level,
1497 start_layer, num_layers,
1498 ISL_AUX_USAGE_NONE);
1499 }
1500 }
1501
1502 void
brw_blorp_resolve_color(struct brw_context * brw,struct intel_mipmap_tree * mt,unsigned level,unsigned layer,enum isl_aux_op resolve_op)1503 brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
1504 unsigned level, unsigned layer,
1505 enum isl_aux_op resolve_op)
1506 {
1507 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
1508
1509 const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
1510
1511 struct blorp_surf surf;
1512 blorp_surf_for_miptree(brw, &surf, mt, mt->aux_usage, true,
1513 &level, layer, 1 /* num_layers */);
1514
1515 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1516 *
1517 * "Any transition from any value in {Clear, Render, Resolve} to a
1518 * different value in {Clear, Render, Resolve} requires end of pipe
1519 * synchronization."
1520 *
1521 * In other words, fast clear ops are not properly synchronized with
1522 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1523 * contents of the previous draw hit the render target before we resolve
1524 * and again afterwards to ensure that the resolve is complete before we
1525 * do any more regular drawing.
1526 */
1527 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
1528
1529
1530 struct blorp_batch batch;
1531 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1532 blorp_ccs_resolve(&batch, &surf, level, layer, 1,
1533 brw_blorp_to_isl_format(brw, format, true),
1534 resolve_op);
1535 blorp_batch_finish(&batch);
1536
1537 /* See comment above */
1538 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
1539 }
1540
1541 void
brw_blorp_mcs_partial_resolve(struct brw_context * brw,struct intel_mipmap_tree * mt,uint32_t start_layer,uint32_t num_layers)1542 brw_blorp_mcs_partial_resolve(struct brw_context *brw,
1543 struct intel_mipmap_tree *mt,
1544 uint32_t start_layer, uint32_t num_layers)
1545 {
1546 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
1547 start_layer, start_layer + num_layers - 1);
1548
1549 assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
1550
1551 const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
1552 enum isl_format isl_format = brw_blorp_to_isl_format(brw, format, true);
1553
1554 struct blorp_surf surf;
1555 uint32_t level = 0;
1556 blorp_surf_for_miptree(brw, &surf, mt, ISL_AUX_USAGE_MCS, true,
1557 &level, start_layer, num_layers);
1558
1559 struct blorp_batch batch;
1560 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1561 blorp_mcs_partial_resolve(&batch, &surf, isl_format,
1562 start_layer, num_layers);
1563 blorp_batch_finish(&batch);
1564 }
1565
1566 /**
1567 * Perform a HiZ or depth resolve operation.
1568 *
1569 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1570 * PRM, Volume 1, Part 2:
1571 * - 7.5.3.1 Depth Buffer Clear
1572 * - 7.5.3.2 Depth Buffer Resolve
1573 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1574 */
1575 void
intel_hiz_exec(struct brw_context * brw,struct intel_mipmap_tree * mt,unsigned int level,unsigned int start_layer,unsigned int num_layers,enum isl_aux_op op)1576 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
1577 unsigned int level, unsigned int start_layer,
1578 unsigned int num_layers, enum isl_aux_op op)
1579 {
1580 assert(intel_miptree_level_has_hiz(mt, level));
1581 assert(op != ISL_AUX_OP_NONE);
1582 const struct gen_device_info *devinfo = &brw->screen->devinfo;
1583 const char *opname = NULL;
1584
1585 switch (op) {
1586 case ISL_AUX_OP_FULL_RESOLVE:
1587 opname = "depth resolve";
1588 break;
1589 case ISL_AUX_OP_AMBIGUATE:
1590 opname = "hiz ambiguate";
1591 break;
1592 case ISL_AUX_OP_FAST_CLEAR:
1593 opname = "depth clear";
1594 break;
1595 case ISL_AUX_OP_PARTIAL_RESOLVE:
1596 case ISL_AUX_OP_NONE:
1597 unreachable("Invalid HiZ op");
1598 }
1599
1600 DBG("%s %s to mt %p level %d layers %d-%d\n",
1601 __func__, opname, mt, level, start_layer, start_layer + num_layers - 1);
1602
1603 /* The following stalls and flushes are only documented to be required for
1604 * HiZ clear operations. However, they also seem to be required for
1605 * resolve operations.
1606 */
1607 if (devinfo->gen == 6) {
1608 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1609 *
1610 * "If other rendering operations have preceded this clear, a
1611 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1612 * disabled must be issued before the rectangle primitive used for
1613 * the depth buffer clear operation.
1614 */
1615 brw_emit_pipe_control_flush(brw,
1616 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1617 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1618 PIPE_CONTROL_CS_STALL);
1619 } else if (devinfo->gen >= 7) {
1620 /*
1621 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1622 *
1623 * If other rendering operations have preceded this clear, a
1624 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1625 * enabled must be issued before the rectangle primitive used for
1626 * the depth buffer clear operation.
1627 *
1628 * Same applies for Gen8 and Gen9.
1629 *
1630 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1631 * PIPE_CONTROL, Depth Cache Flush Enable:
1632 *
1633 * This bit must not be set when Depth Stall Enable bit is set in
1634 * this packet.
1635 *
1636 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1637 *
1638 * Therefore issue two pipe control flushes, one for cache flush and
1639 * another for depth stall.
1640 */
1641 brw_emit_pipe_control_flush(brw,
1642 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1643 PIPE_CONTROL_CS_STALL);
1644
1645 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
1646 }
1647
1648 assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
1649
1650 struct blorp_surf surf;
1651 blorp_surf_for_miptree(brw, &surf, mt, ISL_AUX_USAGE_HIZ, true,
1652 &level, start_layer, num_layers);
1653
1654 struct blorp_batch batch;
1655 blorp_batch_init(&brw->blorp, &batch, brw,
1656 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
1657 blorp_hiz_op(&batch, &surf, level, start_layer, num_layers, op);
1658 blorp_batch_finish(&batch);
1659
1660 /* The following stalls and flushes are only documented to be required for
1661 * HiZ clear operations. However, they also seem to be required for
1662 * resolve operations.
1663 */
1664 if (devinfo->gen == 6) {
1665 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1666 *
1667 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1668 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1669 * and Then followed by Depth FLUSH'
1670 */
1671 brw_emit_pipe_control_flush(brw,
1672 PIPE_CONTROL_DEPTH_STALL);
1673
1674 brw_emit_pipe_control_flush(brw,
1675 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1676 PIPE_CONTROL_CS_STALL);
1677 } else if (devinfo->gen >= 8) {
1678 /*
1679 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1680 *
1681 * "Depth buffer clear pass using any of the methods (WM_STATE,
1682 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1683 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1684 * "set" before starting to render. DepthStall and DepthFlush are
1685 * not needed between consecutive depth clear passes nor is it
1686 * required if the depth clear pass was done with
1687 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1688 *
1689 * TODO: Such as the spec says, this could be conditional.
1690 */
1691 brw_emit_pipe_control_flush(brw,
1692 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1693 PIPE_CONTROL_DEPTH_STALL);
1694
1695 }
1696 }
1697