1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23 #include "main/mtypes.h"
24
25 #include "isl/isl.h"
26
27 #include "brw_context.h"
28 #include "brw_state.h"
29 #include "brw_defines.h"
30
31 enum isl_format
brw_isl_format_for_mesa_format(mesa_format mesa_format)32 brw_isl_format_for_mesa_format(mesa_format mesa_format)
33 {
34 /* This table is ordered according to the enum ordering in formats.h. We do
35 * expect that enum to be extended without our explicit initialization
36 * staying in sync, so we initialize to 0 even though
37 * ISL_FORMAT_R32G32B32A32_FLOAT happens to also be 0.
38 */
39 static const enum isl_format table[MESA_FORMAT_COUNT] = {
40 [0 ... MESA_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,
41
42 [MESA_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
43 [MESA_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
44 [MESA_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
45 [MESA_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
46 [MESA_FORMAT_RGB_UNORM8] = ISL_FORMAT_R8G8B8_UNORM,
47 [MESA_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
48 [MESA_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
49 [MESA_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
50 [MESA_FORMAT_LA_UNORM8] = ISL_FORMAT_L8A8_UNORM,
51 [MESA_FORMAT_LA_UNORM16] = ISL_FORMAT_L16A16_UNORM,
52 [MESA_FORMAT_A_UNORM8] = ISL_FORMAT_A8_UNORM,
53 [MESA_FORMAT_A_UNORM16] = ISL_FORMAT_A16_UNORM,
54 [MESA_FORMAT_L_UNORM8] = ISL_FORMAT_L8_UNORM,
55 [MESA_FORMAT_L_UNORM16] = ISL_FORMAT_L16_UNORM,
56 [MESA_FORMAT_I_UNORM8] = ISL_FORMAT_I8_UNORM,
57 [MESA_FORMAT_I_UNORM16] = ISL_FORMAT_I16_UNORM,
58 [MESA_FORMAT_YCBCR_REV] = ISL_FORMAT_YCRCB_NORMAL,
59 [MESA_FORMAT_YCBCR] = ISL_FORMAT_YCRCB_SWAPUVY,
60 [MESA_FORMAT_R_UNORM8] = ISL_FORMAT_R8_UNORM,
61 [MESA_FORMAT_RG_UNORM8] = ISL_FORMAT_R8G8_UNORM,
62 [MESA_FORMAT_R_UNORM16] = ISL_FORMAT_R16_UNORM,
63 [MESA_FORMAT_RG_UNORM16] = ISL_FORMAT_R16G16_UNORM,
64 [MESA_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
65 [MESA_FORMAT_S_UINT8] = ISL_FORMAT_R8_UINT,
66
67 [MESA_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
68 [MESA_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
69 [MESA_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
70 [MESA_FORMAT_R_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
71 [MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
72 [MESA_FORMAT_LA_SRGB8] = ISL_FORMAT_L8A8_UNORM_SRGB,
73 [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
74 [MESA_FORMAT_SRGBA_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
75 [MESA_FORMAT_SRGBA_DXT3] = ISL_FORMAT_BC2_UNORM_SRGB,
76 [MESA_FORMAT_SRGBA_DXT5] = ISL_FORMAT_BC3_UNORM_SRGB,
77
78 [MESA_FORMAT_RGB_FXT1] = ISL_FORMAT_FXT1,
79 [MESA_FORMAT_RGBA_FXT1] = ISL_FORMAT_FXT1,
80 [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_BC1_UNORM,
81 [MESA_FORMAT_RGBA_DXT1] = ISL_FORMAT_BC1_UNORM,
82 [MESA_FORMAT_RGBA_DXT3] = ISL_FORMAT_BC2_UNORM,
83 [MESA_FORMAT_RGBA_DXT5] = ISL_FORMAT_BC3_UNORM,
84
85 [MESA_FORMAT_RGBA_FLOAT32] = ISL_FORMAT_R32G32B32A32_FLOAT,
86 [MESA_FORMAT_RGBA_FLOAT16] = ISL_FORMAT_R16G16B16A16_FLOAT,
87 [MESA_FORMAT_RGB_FLOAT32] = ISL_FORMAT_R32G32B32_FLOAT,
88 [MESA_FORMAT_A_FLOAT32] = ISL_FORMAT_A32_FLOAT,
89 [MESA_FORMAT_A_FLOAT16] = ISL_FORMAT_A16_FLOAT,
90 [MESA_FORMAT_L_FLOAT32] = ISL_FORMAT_L32_FLOAT,
91 [MESA_FORMAT_L_FLOAT16] = ISL_FORMAT_L16_FLOAT,
92 [MESA_FORMAT_LA_FLOAT32] = ISL_FORMAT_L32A32_FLOAT,
93 [MESA_FORMAT_LA_FLOAT16] = ISL_FORMAT_L16A16_FLOAT,
94 [MESA_FORMAT_I_FLOAT32] = ISL_FORMAT_I32_FLOAT,
95 [MESA_FORMAT_I_FLOAT16] = ISL_FORMAT_I16_FLOAT,
96 [MESA_FORMAT_R_FLOAT32] = ISL_FORMAT_R32_FLOAT,
97 [MESA_FORMAT_R_FLOAT16] = ISL_FORMAT_R16_FLOAT,
98 [MESA_FORMAT_RG_FLOAT32] = ISL_FORMAT_R32G32_FLOAT,
99 [MESA_FORMAT_RG_FLOAT16] = ISL_FORMAT_R16G16_FLOAT,
100
101 [MESA_FORMAT_R_SINT8] = ISL_FORMAT_R8_SINT,
102 [MESA_FORMAT_RG_SINT8] = ISL_FORMAT_R8G8_SINT,
103 [MESA_FORMAT_RGB_SINT8] = ISL_FORMAT_R8G8B8_SINT,
104 [MESA_FORMAT_RGBA_SINT8] = ISL_FORMAT_R8G8B8A8_SINT,
105 [MESA_FORMAT_R_SINT16] = ISL_FORMAT_R16_SINT,
106 [MESA_FORMAT_RG_SINT16] = ISL_FORMAT_R16G16_SINT,
107 [MESA_FORMAT_RGB_SINT16] = ISL_FORMAT_R16G16B16_SINT,
108 [MESA_FORMAT_RGBA_SINT16] = ISL_FORMAT_R16G16B16A16_SINT,
109 [MESA_FORMAT_R_SINT32] = ISL_FORMAT_R32_SINT,
110 [MESA_FORMAT_RG_SINT32] = ISL_FORMAT_R32G32_SINT,
111 [MESA_FORMAT_RGB_SINT32] = ISL_FORMAT_R32G32B32_SINT,
112 [MESA_FORMAT_RGBA_SINT32] = ISL_FORMAT_R32G32B32A32_SINT,
113
114 [MESA_FORMAT_R_UINT8] = ISL_FORMAT_R8_UINT,
115 [MESA_FORMAT_RG_UINT8] = ISL_FORMAT_R8G8_UINT,
116 [MESA_FORMAT_RGB_UINT8] = ISL_FORMAT_R8G8B8_UINT,
117 [MESA_FORMAT_RGBA_UINT8] = ISL_FORMAT_R8G8B8A8_UINT,
118 [MESA_FORMAT_R_UINT16] = ISL_FORMAT_R16_UINT,
119 [MESA_FORMAT_RG_UINT16] = ISL_FORMAT_R16G16_UINT,
120 [MESA_FORMAT_RGB_UINT16] = ISL_FORMAT_R16G16B16_UINT,
121 [MESA_FORMAT_RGBA_UINT16] = ISL_FORMAT_R16G16B16A16_UINT,
122 [MESA_FORMAT_R_UINT32] = ISL_FORMAT_R32_UINT,
123 [MESA_FORMAT_RG_UINT32] = ISL_FORMAT_R32G32_UINT,
124 [MESA_FORMAT_RGB_UINT32] = ISL_FORMAT_R32G32B32_UINT,
125 [MESA_FORMAT_RGBA_UINT32] = ISL_FORMAT_R32G32B32A32_UINT,
126
127 [MESA_FORMAT_R_SNORM8] = ISL_FORMAT_R8_SNORM,
128 [MESA_FORMAT_RG_SNORM8] = ISL_FORMAT_R8G8_SNORM,
129 [MESA_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
130 [MESA_FORMAT_R_SNORM16] = ISL_FORMAT_R16_SNORM,
131 [MESA_FORMAT_RG_SNORM16] = ISL_FORMAT_R16G16_SNORM,
132 [MESA_FORMAT_RGB_SNORM16] = ISL_FORMAT_R16G16B16_SNORM,
133 [MESA_FORMAT_RGBA_SNORM16] = ISL_FORMAT_R16G16B16A16_SNORM,
134 [MESA_FORMAT_RGBA_UNORM16] = ISL_FORMAT_R16G16B16A16_UNORM,
135
136 [MESA_FORMAT_R_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
137 [MESA_FORMAT_R_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
138 [MESA_FORMAT_RG_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
139 [MESA_FORMAT_RG_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
140
141 [MESA_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
142 [MESA_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
143 [MESA_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
144 [MESA_FORMAT_ETC2_RGBA8_EAC] = ISL_FORMAT_ETC2_EAC_RGBA8,
145 [MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
146 [MESA_FORMAT_ETC2_R11_EAC] = ISL_FORMAT_EAC_R11,
147 [MESA_FORMAT_ETC2_RG11_EAC] = ISL_FORMAT_EAC_RG11,
148 [MESA_FORMAT_ETC2_SIGNED_R11_EAC] = ISL_FORMAT_EAC_SIGNED_R11,
149 [MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = ISL_FORMAT_EAC_SIGNED_RG11,
150 [MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_RGB8_PTA,
151 [MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_SRGB8_PTA,
152
153 [MESA_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
154 [MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM] = ISL_FORMAT_BC7_UNORM_SRGB,
155 [MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT] = ISL_FORMAT_BC6H_SF16,
156 [MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT] = ISL_FORMAT_BC6H_UF16,
157
158 [MESA_FORMAT_RGBA_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
159 [MESA_FORMAT_RGBA_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
160 [MESA_FORMAT_RGBA_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
161 [MESA_FORMAT_RGBA_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
162 [MESA_FORMAT_RGBA_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
163 [MESA_FORMAT_RGBA_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
164 [MESA_FORMAT_RGBA_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
165 [MESA_FORMAT_RGBA_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
166 [MESA_FORMAT_RGBA_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
167 [MESA_FORMAT_RGBA_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
168 [MESA_FORMAT_RGBA_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
169 [MESA_FORMAT_RGBA_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
170 [MESA_FORMAT_RGBA_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
171 [MESA_FORMAT_RGBA_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
172 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
173 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
174 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
175 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
176 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
177 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
178 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
179 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
180 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
181 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
182 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
183 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
184 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
185 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
186
187 [MESA_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
188 [MESA_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
189
190 [MESA_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
191 [MESA_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
192 [MESA_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
193
194 [MESA_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
195 [MESA_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
196 [MESA_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
197 [MESA_FORMAT_RGBX_UNORM16] = ISL_FORMAT_R16G16B16X16_UNORM,
198 [MESA_FORMAT_RGBX_FLOAT16] = ISL_FORMAT_R16G16B16X16_FLOAT,
199 [MESA_FORMAT_RGBX_FLOAT32] = ISL_FORMAT_R32G32B32X32_FLOAT,
200 };
201
202 assert(mesa_format < MESA_FORMAT_COUNT);
203 return table[mesa_format];
204 }
205
206 void
intel_screen_init_surface_formats(struct intel_screen * screen)207 intel_screen_init_surface_formats(struct intel_screen *screen)
208 {
209 const struct gen_device_info *devinfo = &screen->devinfo;
210 mesa_format format;
211
212 memset(&screen->mesa_format_supports_texture, 0,
213 sizeof(screen->mesa_format_supports_texture));
214
215 int gen = devinfo->gen * 10;
216 if (devinfo->is_g4x || devinfo->is_haswell)
217 gen += 5;
218
219 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
220 if (!_mesa_get_format_name(format))
221 continue;
222 enum isl_format texture, render;
223 bool is_integer = _mesa_is_format_integer_color(format);
224
225 render = texture = brw_isl_format_for_mesa_format(format);
226
227 if (texture == ISL_FORMAT_UNSUPPORTED)
228 continue;
229
230 /* Don't advertise 8 and 16-bit RGB formats to core mesa. This ensures
231 * that they are renderable from an API perspective since core mesa will
232 * fall back to RGBA or RGBX (we can't render to non-power-of-two
233 * formats). For 8-bit, formats, this also keeps us from hitting some
234 * nasty corners in intel_miptree_map_blit if you ever try to map one.
235 */
236 int format_size = _mesa_get_format_bytes(format);
237 if (format_size == 3 || format_size == 6)
238 continue;
239
240 if (isl_format_supports_sampling(devinfo, texture) &&
241 (isl_format_supports_filtering(devinfo, texture) || is_integer))
242 screen->mesa_format_supports_texture[format] = true;
243
244 /* Re-map some render target formats to make them supported when they
245 * wouldn't be using their format for texturing.
246 */
247 switch (render) {
248 /* For these formats, we just need to read/write the first
249 * channel into R, which is to say that we just treat them as
250 * GL_RED.
251 */
252 case ISL_FORMAT_I32_FLOAT:
253 case ISL_FORMAT_L32_FLOAT:
254 render = ISL_FORMAT_R32_FLOAT;
255 break;
256 case ISL_FORMAT_I16_FLOAT:
257 case ISL_FORMAT_L16_FLOAT:
258 render = ISL_FORMAT_R16_FLOAT;
259 break;
260 case ISL_FORMAT_I8_UNORM:
261 case ISL_FORMAT_L8_UNORM:
262 render = ISL_FORMAT_R8_UNORM;
263 break;
264 case ISL_FORMAT_I16_UNORM:
265 case ISL_FORMAT_L16_UNORM:
266 render = ISL_FORMAT_R16_UNORM;
267 break;
268 case ISL_FORMAT_R16G16B16X16_UNORM:
269 render = ISL_FORMAT_R16G16B16A16_UNORM;
270 break;
271 case ISL_FORMAT_R16G16B16X16_FLOAT:
272 render = ISL_FORMAT_R16G16B16A16_FLOAT;
273 break;
274 case ISL_FORMAT_B8G8R8X8_UNORM:
275 /* XRGB is handled as ARGB because the chips in this family
276 * cannot render to XRGB targets. This means that we have to
277 * mask writes to alpha (ala glColorMask) and reconfigure the
278 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
279 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
280 * used. On Gen8+ BGRX is actually allowed (but not RGBX).
281 */
282 if (!isl_format_supports_rendering(devinfo, texture))
283 render = ISL_FORMAT_B8G8R8A8_UNORM;
284 break;
285 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB:
286 if (!isl_format_supports_rendering(devinfo, texture))
287 render = ISL_FORMAT_B8G8R8A8_UNORM_SRGB;
288 break;
289 case ISL_FORMAT_R8G8B8X8_UNORM:
290 render = ISL_FORMAT_R8G8B8A8_UNORM;
291 break;
292 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB:
293 render = ISL_FORMAT_R8G8B8A8_UNORM_SRGB;
294 break;
295 default:
296 break;
297 }
298
299 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
300 * integer, so we don't need hardware support for blending on it. Other
301 * than that, GL in general requires alpha blending for render targets,
302 * even though we don't support it for some formats.
303 */
304 if (isl_format_supports_rendering(devinfo, render) &&
305 (isl_format_supports_alpha_blending(devinfo, render) || is_integer)) {
306 screen->mesa_to_isl_render_format[format] = render;
307 screen->mesa_format_supports_render[format] = true;
308 }
309 }
310
311 /* We will check this table for FBO completeness, but the surface format
312 * table above only covered color rendering.
313 */
314 screen->mesa_format_supports_render[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
315 screen->mesa_format_supports_render[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
316 screen->mesa_format_supports_render[MESA_FORMAT_S_UINT8] = true;
317 screen->mesa_format_supports_render[MESA_FORMAT_Z_FLOAT32] = true;
318 screen->mesa_format_supports_render[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
319 if (gen >= 80)
320 screen->mesa_format_supports_render[MESA_FORMAT_Z_UNORM16] = true;
321
322 /* We remap depth formats to a supported texturing format in
323 * translate_tex_format().
324 */
325 screen->mesa_format_supports_texture[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
326 screen->mesa_format_supports_texture[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
327 screen->mesa_format_supports_texture[MESA_FORMAT_Z_FLOAT32] = true;
328 screen->mesa_format_supports_texture[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
329 screen->mesa_format_supports_texture[MESA_FORMAT_S_UINT8] = true;
330
331 /* Benchmarking shows that Z16 is slower than Z24, so there's no reason to
332 * use it unless you're under memory (not memory bandwidth) pressure.
333 *
334 * Apparently, the GPU's depth scoreboarding works on a 32-bit granularity,
335 * which corresponds to one pixel in the depth buffer for Z24 or Z32 formats.
336 * However, it corresponds to two pixels with Z16, which means both need to
337 * hit the early depth case in order for it to happen.
338 *
339 * Other speculation is that we may be hitting increased fragment shader
340 * execution from GL_LEQUAL/GL_EQUAL depth tests at reduced precision.
341 *
342 * With the PMA stall workaround in place, Z16 is faster than Z24, as it
343 * should be.
344 */
345 if (gen >= 80)
346 screen->mesa_format_supports_texture[MESA_FORMAT_Z_UNORM16] = true;
347
348 /* The RGBX formats are not renderable. Normally these get mapped
349 * internally to RGBA formats when rendering. However on Gen9+ when this
350 * internal override is used fast clears don't work so they are disabled in
351 * brw_meta_fast_clear. To avoid this problem we can just pretend not to
352 * support RGBX formats at all. This will cause the upper layers of Mesa to
353 * pick the RGBA formats instead. This works fine because when it is used
354 * as a texture source the swizzle state is programmed to force the alpha
355 * channel to 1.0 anyway. We could also do this for all gens except that
356 * it's a bit more difficult when the hardware doesn't support texture
357 * swizzling. Gens using the blorp have further problems because that
358 * doesn't implement this swizzle override. We don't need to do this for
359 * BGRX because that actually is supported natively on Gen8+.
360 */
361 if (gen >= 90) {
362 static const mesa_format rgbx_formats[] = {
363 MESA_FORMAT_R8G8B8X8_UNORM,
364 MESA_FORMAT_R8G8B8X8_SRGB,
365 MESA_FORMAT_RGBX_UNORM16,
366 MESA_FORMAT_RGBX_FLOAT16,
367 MESA_FORMAT_RGBX_FLOAT32
368 };
369
370 for (int i = 0; i < ARRAY_SIZE(rgbx_formats); i++) {
371 screen->mesa_format_supports_texture[rgbx_formats[i]] = false;
372 screen->mesa_format_supports_render[rgbx_formats[i]] = false;
373 }
374 }
375
376 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
377 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
378 */
379 screen->mesa_format_supports_texture[MESA_FORMAT_ETC1_RGB8] = true;
380
381 /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
382 * MESA_FORMAT during glCompressedTexImage2D().
383 * See intel_mipmap_tree::wraps_etc2.
384 */
385 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGB8] = true;
386 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8] = true;
387 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
388 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
389 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_R11_EAC] = true;
390 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RG11_EAC] = true;
391 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
392 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
393 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
394 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
395 }
396
397 void
brw_init_surface_formats(struct brw_context * brw)398 brw_init_surface_formats(struct brw_context *brw)
399 {
400 struct intel_screen *screen = brw->screen;
401 struct gl_context *ctx = &brw->ctx;
402
403 brw->mesa_format_supports_render = screen->mesa_format_supports_render;
404 brw->mesa_to_isl_render_format = screen->mesa_to_isl_render_format;
405
406 STATIC_ASSERT(ARRAY_SIZE(ctx->TextureFormatSupported) ==
407 ARRAY_SIZE(screen->mesa_format_supports_texture));
408
409 for (unsigned i = 0; i < ARRAY_SIZE(ctx->TextureFormatSupported); ++i) {
410 ctx->TextureFormatSupported[i] = screen->mesa_format_supports_texture[i];
411 }
412 }
413
414 bool
brw_render_target_supported(struct brw_context * brw,struct gl_renderbuffer * rb)415 brw_render_target_supported(struct brw_context *brw,
416 struct gl_renderbuffer *rb)
417 {
418 const struct gen_device_info *devinfo = &brw->screen->devinfo;
419 mesa_format format = rb->Format;
420
421 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
422 * we would consider them renderable even though we don't have surface
423 * support for their alpha behavior and don't have the blending unit
424 * available to fake it like we do for XRGB8888. Force them to being
425 * unsupported.
426 */
427 if (_mesa_is_format_integer_color(format) &&
428 rb->_BaseFormat != GL_RGBA &&
429 rb->_BaseFormat != GL_RG &&
430 rb->_BaseFormat != GL_RED)
431 return false;
432
433 /* Under some conditions, MSAA is not supported for formats whose width is
434 * more than 64 bits.
435 */
436 if (devinfo->gen < 8 &&
437 rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
438 /* Gen6: MSAA on >64 bit formats is unsupported. */
439 if (devinfo->gen <= 6)
440 return false;
441
442 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
443 if (rb->NumSamples >= 8)
444 return false;
445 }
446
447 return brw->mesa_format_supports_render[format];
448 }
449
450 enum isl_format
translate_tex_format(struct brw_context * brw,mesa_format mesa_format,GLenum srgb_decode)451 translate_tex_format(struct brw_context *brw,
452 mesa_format mesa_format,
453 GLenum srgb_decode)
454 {
455 struct gl_context *ctx = &brw->ctx;
456 if (srgb_decode == GL_SKIP_DECODE_EXT)
457 mesa_format = _mesa_get_srgb_format_linear(mesa_format);
458
459 switch( mesa_format ) {
460
461 case MESA_FORMAT_Z_UNORM16:
462 return ISL_FORMAT_R16_UNORM;
463
464 case MESA_FORMAT_Z24_UNORM_S8_UINT:
465 case MESA_FORMAT_Z24_UNORM_X8_UINT:
466 return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
467
468 case MESA_FORMAT_Z_FLOAT32:
469 return ISL_FORMAT_R32_FLOAT;
470
471 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
472 return ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS;
473
474 case MESA_FORMAT_RGBA_FLOAT32:
475 /* The value of this ISL surface format is 0, which tricks the
476 * assertion below.
477 */
478 return ISL_FORMAT_R32G32B32A32_FLOAT;
479
480 case MESA_FORMAT_RGBA_ASTC_4x4:
481 case MESA_FORMAT_RGBA_ASTC_5x4:
482 case MESA_FORMAT_RGBA_ASTC_5x5:
483 case MESA_FORMAT_RGBA_ASTC_6x5:
484 case MESA_FORMAT_RGBA_ASTC_6x6:
485 case MESA_FORMAT_RGBA_ASTC_8x5:
486 case MESA_FORMAT_RGBA_ASTC_8x6:
487 case MESA_FORMAT_RGBA_ASTC_8x8:
488 case MESA_FORMAT_RGBA_ASTC_10x5:
489 case MESA_FORMAT_RGBA_ASTC_10x6:
490 case MESA_FORMAT_RGBA_ASTC_10x8:
491 case MESA_FORMAT_RGBA_ASTC_10x10:
492 case MESA_FORMAT_RGBA_ASTC_12x10:
493 case MESA_FORMAT_RGBA_ASTC_12x12: {
494 enum isl_format isl_fmt =
495 brw_isl_format_for_mesa_format(mesa_format);
496
497 /**
498 * It is possible to process these formats using the LDR Profile
499 * or the Full Profile mode of the hardware. Because, it isn't
500 * possible to determine if an HDR or LDR texture is being rendered, we
501 * can't determine which mode to enable in the hardware. Therefore, to
502 * handle all cases, always default to Full profile unless we are
503 * processing sRGBs, which are incompatible with this mode.
504 */
505 if (ctx->Extensions.KHR_texture_compression_astc_hdr)
506 isl_fmt |= GEN9_SURFACE_ASTC_HDR_FORMAT_BIT;
507
508 return isl_fmt;
509 }
510
511 default:
512 return brw_isl_format_for_mesa_format(mesa_format);
513 }
514 }
515
516 /**
517 * Convert a MESA_FORMAT to the corresponding BRW_DEPTHFORMAT enum.
518 */
519 uint32_t
brw_depth_format(struct brw_context * brw,mesa_format format)520 brw_depth_format(struct brw_context *brw, mesa_format format)
521 {
522 const struct gen_device_info *devinfo = &brw->screen->devinfo;
523
524 switch (format) {
525 case MESA_FORMAT_Z_UNORM16:
526 return BRW_DEPTHFORMAT_D16_UNORM;
527 case MESA_FORMAT_Z_FLOAT32:
528 return BRW_DEPTHFORMAT_D32_FLOAT;
529 case MESA_FORMAT_Z24_UNORM_X8_UINT:
530 if (devinfo->gen >= 6) {
531 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
532 } else {
533 /* Use D24_UNORM_S8, not D24_UNORM_X8.
534 *
535 * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
536 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
537 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
538 *
539 * However, on Gen5, D24_UNORM_X8 may be used only if separate
540 * stencil is enabled, and we never enable it. From the Ironlake PRM,
541 * same section as above, 3DSTATE_DEPTH_BUFFER's
542 * "Separate Stencil Buffer Enable" bit:
543 *
544 * "If this field is disabled, the Surface Format of the depth
545 * buffer cannot be D24_UNORM_X8_UINT."
546 */
547 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
548 }
549 case MESA_FORMAT_Z24_UNORM_S8_UINT:
550 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
551 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
552 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT;
553 default:
554 unreachable("Unexpected depth format.");
555 }
556 }
557