1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
25
26 #ifndef RADEON_WINSYS_H
27 #define RADEON_WINSYS_H
28
29 /* The public winsys interface header for the radeon driver. */
30
31 /* Skip command submission. Same as RADEON_NOOP=1. */
32 #define RADEON_FLUSH_NOOP (1u << 29)
33
34 /* Toggle the secure submission boolean after the flush */
35 #define RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION (1u << 30)
36
37 /* Whether the next IB can start immediately and not wait for draws and
38 * dispatches from the current IB to finish. */
39 #define RADEON_FLUSH_START_NEXT_GFX_IB_NOW (1u << 31)
40
41 #define RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW \
42 (PIPE_FLUSH_ASYNC | RADEON_FLUSH_START_NEXT_GFX_IB_NOW)
43
44 #include "amd/common/ac_gpu_info.h"
45 #include "amd/common/ac_surface.h"
46 #include "pipebuffer/pb_buffer.h"
47
48 /* Tiling flags. */
49 enum radeon_bo_layout
50 {
51 RADEON_LAYOUT_LINEAR = 0,
52 RADEON_LAYOUT_TILED,
53 RADEON_LAYOUT_SQUARETILED,
54
55 RADEON_LAYOUT_UNKNOWN
56 };
57
58 enum radeon_bo_domain
59 { /* bitfield */
60 RADEON_DOMAIN_GTT = 2,
61 RADEON_DOMAIN_VRAM = 4,
62 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
63 RADEON_DOMAIN_GDS = 8,
64 RADEON_DOMAIN_OA = 16,
65 };
66
67 enum radeon_bo_flag
68 { /* bitfield */
69 RADEON_FLAG_GTT_WC = (1 << 0),
70 RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
71 RADEON_FLAG_NO_SUBALLOC = (1 << 2),
72 RADEON_FLAG_SPARSE = (1 << 3),
73 RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
74 RADEON_FLAG_READ_ONLY = (1 << 5),
75 RADEON_FLAG_32BIT = (1 << 6),
76 RADEON_FLAG_ENCRYPTED = (1 << 7),
77 RADEON_FLAG_UNCACHED = (1 << 8), /* only gfx9 and newer */
78 RADEON_FLAG_DRIVER_INTERNAL = (1 << 9),
79 };
80
81 enum radeon_dependency_flag
82 {
83 /* Add the dependency to the parallel compute IB only. */
84 RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY = 1 << 0,
85
86 /* Instead of waiting for a job to finish execution, the dependency will
87 * be signaled when the job starts execution.
88 */
89 RADEON_DEPENDENCY_START_FENCE = 1 << 1,
90 };
91
92 enum radeon_bo_usage
93 { /* bitfield */
94 RADEON_USAGE_READ = 2,
95 RADEON_USAGE_WRITE = 4,
96 RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
97
98 /* The winsys ensures that the CS submission will be scheduled after
99 * previously flushed CSs referencing this BO in a conflicting way.
100 */
101 RADEON_USAGE_SYNCHRONIZED = 8
102 };
103
104 enum radeon_map_flags
105 {
106 /* Indicates that the caller will unmap the buffer.
107 *
108 * Not unmapping buffers is an important performance optimization for
109 * OpenGL (avoids kernel overhead for frequently mapped buffers).
110 */
111 RADEON_MAP_TEMPORARY = (PIPE_MAP_DRV_PRV << 0),
112 };
113
114 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
115
116 enum radeon_value_id
117 {
118 RADEON_REQUESTED_VRAM_MEMORY,
119 RADEON_REQUESTED_GTT_MEMORY,
120 RADEON_MAPPED_VRAM,
121 RADEON_MAPPED_GTT,
122 RADEON_BUFFER_WAIT_TIME_NS,
123 RADEON_NUM_MAPPED_BUFFERS,
124 RADEON_TIMESTAMP,
125 RADEON_NUM_GFX_IBS,
126 RADEON_NUM_SDMA_IBS,
127 RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
128 RADEON_GFX_IB_SIZE_COUNTER,
129 RADEON_NUM_BYTES_MOVED,
130 RADEON_NUM_EVICTIONS,
131 RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
132 RADEON_VRAM_USAGE,
133 RADEON_VRAM_VIS_USAGE,
134 RADEON_GTT_USAGE,
135 RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
136 RADEON_CURRENT_SCLK,
137 RADEON_CURRENT_MCLK,
138 RADEON_CS_THREAD_TIME,
139 };
140
141 enum radeon_bo_priority
142 {
143 /* Each group of two has the same priority. */
144 RADEON_PRIO_FENCE = 0,
145 RADEON_PRIO_TRACE,
146
147 RADEON_PRIO_SO_FILLED_SIZE = 2,
148 RADEON_PRIO_QUERY,
149
150 RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
151 RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
152
153 RADEON_PRIO_DRAW_INDIRECT = 6,
154 RADEON_PRIO_INDEX_BUFFER,
155
156 RADEON_PRIO_CP_DMA = 8,
157 RADEON_PRIO_BORDER_COLORS,
158
159 RADEON_PRIO_CONST_BUFFER = 10,
160 RADEON_PRIO_DESCRIPTORS,
161
162 RADEON_PRIO_SAMPLER_BUFFER = 12,
163 RADEON_PRIO_VERTEX_BUFFER,
164
165 RADEON_PRIO_SHADER_RW_BUFFER = 14,
166 RADEON_PRIO_COMPUTE_GLOBAL,
167
168 RADEON_PRIO_SAMPLER_TEXTURE = 16,
169 RADEON_PRIO_SHADER_RW_IMAGE,
170
171 RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 18,
172 RADEON_PRIO_COLOR_BUFFER,
173
174 RADEON_PRIO_DEPTH_BUFFER = 20,
175
176 RADEON_PRIO_COLOR_BUFFER_MSAA = 22,
177
178 RADEON_PRIO_DEPTH_BUFFER_MSAA = 24,
179
180 RADEON_PRIO_SEPARATE_META = 26,
181 RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
182
183 RADEON_PRIO_SHADER_RINGS = 28,
184
185 RADEON_PRIO_SCRATCH_BUFFER = 30,
186 /* 31 is the maximum value */
187 };
188
189 struct winsys_handle;
190 struct radeon_winsys_ctx;
191
192 struct radeon_cmdbuf_chunk {
193 unsigned cdw; /* Number of used dwords. */
194 unsigned max_dw; /* Maximum number of dwords. */
195 uint32_t *buf; /* The base pointer of the chunk. */
196 };
197
198 struct radeon_cmdbuf {
199 struct radeon_cmdbuf_chunk current;
200 struct radeon_cmdbuf_chunk *prev;
201 unsigned num_prev; /* Number of previous chunks. */
202 unsigned max_prev; /* Space in array pointed to by prev. */
203 unsigned prev_dw; /* Total number of dwords in previous chunks. */
204
205 /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
206 uint64_t used_vram;
207 uint64_t used_gart;
208 uint64_t gpu_address;
209 };
210
211 /* Tiling info for display code, DRI sharing, and other data. */
212 struct radeon_bo_metadata {
213 /* Tiling flags describing the texture layout for display code
214 * and DRI sharing.
215 */
216 union {
217 struct {
218 enum radeon_bo_layout microtile;
219 enum radeon_bo_layout macrotile;
220 unsigned pipe_config;
221 unsigned bankw;
222 unsigned bankh;
223 unsigned tile_split;
224 unsigned mtilea;
225 unsigned num_banks;
226 unsigned stride;
227 bool scanout;
228 } legacy;
229 } u;
230
231 enum radeon_surf_mode mode; /* Output from buffer_get_metadata */
232
233 /* Additional metadata associated with the buffer, in bytes.
234 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
235 * Supported by amdgpu only.
236 */
237 uint32_t size_metadata;
238 uint32_t metadata[64];
239 };
240
241 enum radeon_feature_id
242 {
243 RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
244 RADEON_FID_R300_CMASK_ACCESS,
245 };
246
247 struct radeon_bo_list_item {
248 uint64_t bo_size;
249 uint64_t vm_address;
250 uint32_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
251 };
252
253 struct radeon_winsys {
254 /**
255 * The screen object this winsys was created for
256 */
257 struct pipe_screen *screen;
258 /**
259 * Has the application created at least one TMZ buffer.
260 */
261 const bool uses_secure_bos;
262
263 /**
264 * Decrement the winsys reference count.
265 *
266 * \param ws The winsys this function is called for.
267 * \return True if the winsys and screen should be destroyed.
268 */
269 bool (*unref)(struct radeon_winsys *ws);
270
271 /**
272 * Destroy this winsys.
273 *
274 * \param ws The winsys this function is called from.
275 */
276 void (*destroy)(struct radeon_winsys *ws);
277
278 /**
279 * Query an info structure from winsys.
280 *
281 * \param ws The winsys this function is called from.
282 * \param info Return structure
283 */
284 void (*query_info)(struct radeon_winsys *ws, struct radeon_info *info);
285
286 /**
287 * A hint for the winsys that it should pin its execution threads to
288 * a group of cores sharing a specific L3 cache if the CPU has multiple
289 * L3 caches. This is needed for good multithreading performance on
290 * AMD Zen CPUs.
291 */
292 void (*pin_threads_to_L3_cache)(struct radeon_winsys *ws, unsigned cache);
293
294 /**************************************************************************
295 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
296 *
297 * Remember that gallium gets to choose the interface it needs, and the
298 * window systems must then implement that interface (rather than the
299 * other way around...).
300 *************************************************************************/
301
302 /**
303 * Create a buffer object.
304 *
305 * \param ws The winsys this function is called from.
306 * \param size The size to allocate.
307 * \param alignment An alignment of the buffer in memory.
308 * \param use_reusable_pool Whether the cache buffer manager should be used.
309 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
310 * \return The created buffer object.
311 */
312 struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment,
313 enum radeon_bo_domain domain, enum radeon_bo_flag flags);
314
315 /**
316 * Map the entire data store of a buffer object into the client's address
317 * space.
318 *
319 * Callers are expected to unmap buffers again if and only if the
320 * RADEON_MAP_TEMPORARY flag is set in \p usage.
321 *
322 * \param buf A winsys buffer object to map.
323 * \param cs A command stream to flush if the buffer is referenced by it.
324 * \param usage A bitmask of the PIPE_MAP_* and RADEON_MAP_* flags.
325 * \return The pointer at the beginning of the buffer.
326 */
327 void *(*buffer_map)(struct pb_buffer *buf, struct radeon_cmdbuf *cs,
328 enum pipe_map_flags usage);
329
330 /**
331 * Unmap a buffer object from the client's address space.
332 *
333 * \param buf A winsys buffer object to unmap.
334 */
335 void (*buffer_unmap)(struct pb_buffer *buf);
336
337 /**
338 * Wait for the buffer and return true if the buffer is not used
339 * by the device.
340 *
341 * The timeout of 0 will only return the status.
342 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
343 * is idle.
344 */
345 bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout, enum radeon_bo_usage usage);
346
347 /**
348 * Return buffer metadata.
349 * (tiling info for display code, DRI sharing, and other data)
350 *
351 * \param buf A winsys buffer object to get the flags from.
352 * \param md Metadata
353 */
354 void (*buffer_get_metadata)(struct pb_buffer *buf, struct radeon_bo_metadata *md,
355 struct radeon_surf *surf);
356
357 /**
358 * Set buffer metadata.
359 * (tiling info for display code, DRI sharing, and other data)
360 *
361 * \param buf A winsys buffer object to set the flags for.
362 * \param md Metadata
363 */
364 void (*buffer_set_metadata)(struct pb_buffer *buf, struct radeon_bo_metadata *md,
365 struct radeon_surf *surf);
366
367 /**
368 * Get a winsys buffer from a winsys handle. The internal structure
369 * of the handle is platform-specific and only a winsys should access it.
370 *
371 * \param ws The winsys this function is called from.
372 * \param whandle A winsys handle pointer as was received from a state
373 * tracker.
374 */
375 struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws, struct winsys_handle *whandle,
376 unsigned vm_alignment);
377
378 /**
379 * Get a winsys buffer from a user pointer. The resulting buffer can't
380 * be exported. Both pointer and size must be page aligned.
381 *
382 * \param ws The winsys this function is called from.
383 * \param pointer User pointer to turn into a buffer object.
384 * \param Size Size in bytes for the new buffer.
385 */
386 struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws, void *pointer, uint64_t size);
387
388 /**
389 * Whether the buffer was created from a user pointer.
390 *
391 * \param buf A winsys buffer object
392 * \return whether \p buf was created via buffer_from_ptr
393 */
394 bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
395
396 /** Whether the buffer was suballocated. */
397 bool (*buffer_is_suballocated)(struct pb_buffer *buf);
398
399 /**
400 * Get a winsys handle from a winsys buffer. The internal structure
401 * of the handle is platform-specific and only a winsys should access it.
402 *
403 * \param ws The winsys instance for which the handle is to be valid
404 * \param buf A winsys buffer object to get the handle from.
405 * \param whandle A winsys handle pointer.
406 * \return true on success.
407 */
408 bool (*buffer_get_handle)(struct radeon_winsys *ws, struct pb_buffer *buf,
409 struct winsys_handle *whandle);
410
411 /**
412 * Change the commitment of a (64KB-page aligned) region of the given
413 * sparse buffer.
414 *
415 * \warning There is no automatic synchronization with command submission.
416 *
417 * \note Only implemented by the amdgpu winsys.
418 *
419 * \return false on out of memory or other failure, true on success.
420 */
421 bool (*buffer_commit)(struct pb_buffer *buf, uint64_t offset, uint64_t size, bool commit);
422
423 /**
424 * Return the virtual address of a buffer.
425 *
426 * When virtual memory is not in use, this is the offset relative to the
427 * relocation base (non-zero for sub-allocated buffers).
428 *
429 * \param buf A winsys buffer object
430 * \return virtual address
431 */
432 uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
433
434 /**
435 * Return the offset of this buffer relative to the relocation base.
436 * This is only non-zero for sub-allocated buffers.
437 *
438 * This is only supported in the radeon winsys, since amdgpu uses virtual
439 * addresses in submissions even for the video engines.
440 *
441 * \param buf A winsys buffer object
442 * \return the offset for relocations
443 */
444 unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
445
446 /**
447 * Query the initial placement of the buffer from the kernel driver.
448 */
449 enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
450
451 /**
452 * Query the flags used for creation of this buffer.
453 *
454 * Note that for imported buffer this may be lossy since not all flags
455 * are passed 1:1.
456 */
457 enum radeon_bo_flag (*buffer_get_flags)(struct pb_buffer *buf);
458
459 /**************************************************************************
460 * Command submission.
461 *
462 * Each pipe context should create its own command stream and submit
463 * commands independently of other contexts.
464 *************************************************************************/
465
466 /**
467 * Create a command submission context.
468 * Various command streams can be submitted to the same context.
469 */
470 struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
471
472 /**
473 * Destroy a context.
474 */
475 void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
476
477 /**
478 * Query a GPU reset status.
479 */
480 enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
481
482 /**
483 * Create a command stream.
484 *
485 * \param ctx The submission context
486 * \param ring_type The ring type (GFX, DMA, UVD)
487 * \param flush Flush callback function associated with the command stream.
488 * \param user User pointer that will be passed to the flush callback.
489 */
490 struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type,
491 void (*flush)(void *ctx, unsigned flags,
492 struct pipe_fence_handle **fence),
493 void *flush_ctx, bool stop_exec_on_failure);
494
495 /**
496 * Add a parallel compute IB to a gfx IB. It will share the buffer list
497 * and fence dependencies with the gfx IB. The gfx flush call will submit
498 * both IBs at the same time.
499 *
500 * The compute IB doesn't have an output fence, so the primary IB has
501 * to use a wait packet for synchronization.
502 *
503 * The returned IB is only a stream for writing packets to the new
504 * IB. Calling other winsys functions with it is not allowed, not even
505 * "cs_destroy". Use the gfx IB instead.
506 *
507 * \param cs Gfx IB
508 */
509 struct radeon_cmdbuf *(*cs_add_parallel_compute_ib)(struct radeon_cmdbuf *cs,
510 bool uses_gds_ordered_append);
511
512 /**
513 * Set up and enable mid command buffer preemption for the command stream.
514 *
515 * \param cs Command stream
516 * \param preamble_ib Non-preemptible preamble IB for the context.
517 * \param preamble_num_dw Number of dwords in the preamble IB.
518 */
519 bool (*cs_setup_preemption)(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib,
520 unsigned preamble_num_dw);
521
522 /**
523 * Destroy a command stream.
524 *
525 * \param cs A command stream to destroy.
526 */
527 void (*cs_destroy)(struct radeon_cmdbuf *cs);
528
529 /**
530 * Add a buffer. Each buffer used by a CS must be added using this function.
531 *
532 * \param cs Command stream
533 * \param buf Buffer
534 * \param usage Whether the buffer is used for read and/or write.
535 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
536 * \param priority A higher number means a greater chance of being
537 * placed in the requested domain. 15 is the maximum.
538 * \return Buffer index.
539 */
540 unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf,
541 enum radeon_bo_usage usage, enum radeon_bo_domain domain,
542 enum radeon_bo_priority priority);
543
544 /**
545 * Return the index of an already-added buffer.
546 *
547 * Not supported on amdgpu. Drivers with GPUVM should not care about
548 * buffer indices.
549 *
550 * \param cs Command stream
551 * \param buf Buffer
552 * \return The buffer index, or -1 if the buffer has not been added.
553 */
554 int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf);
555
556 /**
557 * Return true if there is enough memory in VRAM and GTT for the buffers
558 * added so far. If the validation fails, all buffers which have
559 * been added since the last call of cs_validate will be removed and
560 * the CS will be flushed (provided there are still any buffers).
561 *
562 * \param cs A command stream to validate.
563 */
564 bool (*cs_validate)(struct radeon_cmdbuf *cs);
565
566 /**
567 * Check whether the given number of dwords is available in the IB.
568 * Optionally chain a new chunk of the IB if necessary and supported.
569 *
570 * \param cs A command stream.
571 * \param dw Number of CS dwords requested by the caller.
572 * \param force_chaining Chain the IB into a new buffer now to discard
573 * the CP prefetch cache (to emulate PKT3_REWIND)
574 * \return true if there is enough space
575 */
576 bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw, bool force_chaining);
577
578 /**
579 * Return the buffer list.
580 *
581 * This is the buffer list as passed to the kernel, i.e. it only contains
582 * the parent buffers of sub-allocated buffers.
583 *
584 * \param cs Command stream
585 * \param list Returned buffer list. Set to NULL to query the count only.
586 * \return The buffer count.
587 */
588 unsigned (*cs_get_buffer_list)(struct radeon_cmdbuf *cs, struct radeon_bo_list_item *list);
589
590 /**
591 * Flush a command stream.
592 *
593 * \param cs A command stream to flush.
594 * \param flags, PIPE_FLUSH_* flags.
595 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
596 * after the CS and is returned through this parameter.
597 * \return Negative POSIX error code or 0 for success.
598 * Asynchronous submissions never return an error.
599 */
600 int (*cs_flush)(struct radeon_cmdbuf *cs, unsigned flags, struct pipe_fence_handle **fence);
601
602 /**
603 * Create a fence before the CS is flushed.
604 * The user must flush manually to complete the initializaton of the fence.
605 *
606 * The fence must not be used for anything except \ref cs_add_fence_dependency
607 * before the flush.
608 */
609 struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_cmdbuf *cs);
610
611 /**
612 * Return true if a buffer is referenced by a command stream.
613 *
614 * \param cs A command stream.
615 * \param buf A winsys buffer.
616 */
617 bool (*cs_is_buffer_referenced)(struct radeon_cmdbuf *cs, struct pb_buffer *buf,
618 enum radeon_bo_usage usage);
619
620 /**
621 * Request access to a feature for a command stream.
622 *
623 * \param cs A command stream.
624 * \param fid Feature ID, one of RADEON_FID_*
625 * \param enable Whether to enable or disable the feature.
626 */
627 bool (*cs_request_feature)(struct radeon_cmdbuf *cs, enum radeon_feature_id fid, bool enable);
628 /**
629 * Make sure all asynchronous flush of the cs have completed
630 *
631 * \param cs A command stream.
632 */
633 void (*cs_sync_flush)(struct radeon_cmdbuf *cs);
634
635 /**
636 * Add a fence dependency to the CS, so that the CS will wait for
637 * the fence before execution.
638 *
639 * \param dependency_flags Bitmask of RADEON_DEPENDENCY_*
640 */
641 void (*cs_add_fence_dependency)(struct radeon_cmdbuf *cs, struct pipe_fence_handle *fence,
642 unsigned dependency_flags);
643
644 /**
645 * Signal a syncobj when the CS finishes execution.
646 */
647 void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *cs, struct pipe_fence_handle *fence);
648
649 /**
650 * Wait for the fence and return true if the fence has been signalled.
651 * The timeout of 0 will only return the status.
652 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
653 * is signalled.
654 */
655 bool (*fence_wait)(struct radeon_winsys *ws, struct pipe_fence_handle *fence, uint64_t timeout);
656
657 /**
658 * Reference counting for fences.
659 */
660 void (*fence_reference)(struct pipe_fence_handle **dst, struct pipe_fence_handle *src);
661
662 /**
663 * Create a new fence object corresponding to the given syncobj fd.
664 */
665 struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws, int fd);
666
667 /**
668 * Create a new fence object corresponding to the given sync_file.
669 */
670 struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws, int fd);
671
672 /**
673 * Return a sync_file FD corresponding to the given fence object.
674 */
675 int (*fence_export_sync_file)(struct radeon_winsys *ws, struct pipe_fence_handle *fence);
676
677 /**
678 * Return a sync file FD that is already signalled.
679 */
680 int (*export_signalled_sync_file)(struct radeon_winsys *ws);
681
682 /**
683 * Initialize surface
684 *
685 * \param ws The winsys this function is called from.
686 * \param tex Input texture description
687 * \param flags Bitmask of RADEON_SURF_* flags
688 * \param bpe Bytes per pixel, it can be different for Z buffers.
689 * \param mode Preferred tile mode. (linear, 1D, or 2D)
690 * \param surf Output structure
691 */
692 int (*surface_init)(struct radeon_winsys *ws, const struct pipe_resource *tex, unsigned flags,
693 unsigned bpe, enum radeon_surf_mode mode, struct radeon_surf *surf);
694
695 uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value);
696
697 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
698 uint32_t *out);
699
700 /**
701 * Secure context
702 */
703 bool (*cs_is_secure)(struct radeon_cmdbuf *cs);
704 };
705
radeon_emitted(struct radeon_cmdbuf * cs,unsigned num_dw)706 static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw)
707 {
708 return cs && (cs->prev_dw + cs->current.cdw > num_dw);
709 }
710
radeon_emit(struct radeon_cmdbuf * cs,uint32_t value)711 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
712 {
713 cs->current.buf[cs->current.cdw++] = value;
714 }
715
radeon_emit_array(struct radeon_cmdbuf * cs,const uint32_t * values,unsigned count)716 static inline void radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values,
717 unsigned count)
718 {
719 memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
720 cs->current.cdw += count;
721 }
722
radeon_uses_secure_bos(struct radeon_winsys * ws)723 static inline bool radeon_uses_secure_bos(struct radeon_winsys* ws)
724 {
725 return ws->uses_secure_bos;
726 }
727
728 enum radeon_heap
729 {
730 RADEON_HEAP_VRAM_NO_CPU_ACCESS,
731 RADEON_HEAP_VRAM_READ_ONLY,
732 RADEON_HEAP_VRAM_READ_ONLY_32BIT,
733 RADEON_HEAP_VRAM_32BIT,
734 RADEON_HEAP_VRAM,
735 RADEON_HEAP_GTT_WC,
736 RADEON_HEAP_GTT_WC_READ_ONLY,
737 RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
738 RADEON_HEAP_GTT_WC_32BIT,
739 RADEON_HEAP_GTT,
740 RADEON_HEAP_GTT_UNCACHED_WC,
741 RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY,
742 RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT,
743 RADEON_HEAP_GTT_UNCACHED_WC_32BIT,
744 RADEON_HEAP_GTT_UNCACHED,
745 RADEON_MAX_SLAB_HEAPS,
746 RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
747 };
748
radeon_domain_from_heap(enum radeon_heap heap)749 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
750 {
751 switch (heap) {
752 case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
753 case RADEON_HEAP_VRAM_READ_ONLY:
754 case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
755 case RADEON_HEAP_VRAM_32BIT:
756 case RADEON_HEAP_VRAM:
757 return RADEON_DOMAIN_VRAM;
758 case RADEON_HEAP_GTT_WC:
759 case RADEON_HEAP_GTT_WC_READ_ONLY:
760 case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
761 case RADEON_HEAP_GTT_WC_32BIT:
762 case RADEON_HEAP_GTT:
763 case RADEON_HEAP_GTT_UNCACHED_WC:
764 case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY:
765 case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT:
766 case RADEON_HEAP_GTT_UNCACHED_WC_32BIT:
767 case RADEON_HEAP_GTT_UNCACHED:
768 return RADEON_DOMAIN_GTT;
769 default:
770 assert(0);
771 return (enum radeon_bo_domain)0;
772 }
773 }
774
radeon_flags_from_heap(enum radeon_heap heap)775 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
776 {
777 unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING;
778
779 switch (heap) {
780 case RADEON_HEAP_GTT:
781 case RADEON_HEAP_GTT_UNCACHED:
782 break;
783 default:
784 flags |= RADEON_FLAG_GTT_WC;
785 }
786
787 switch (heap) {
788 case RADEON_HEAP_GTT_UNCACHED_WC:
789 case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY:
790 case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT:
791 case RADEON_HEAP_GTT_UNCACHED_WC_32BIT:
792 case RADEON_HEAP_GTT_UNCACHED:
793 flags |= RADEON_FLAG_UNCACHED;
794 break;
795 default:
796 break;
797 }
798
799 switch (heap) {
800 case RADEON_HEAP_VRAM_READ_ONLY:
801 case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
802 case RADEON_HEAP_GTT_WC_READ_ONLY:
803 case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
804 case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY:
805 case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT:
806 flags |= RADEON_FLAG_READ_ONLY;
807 break;
808 default:
809 break;
810 }
811
812 switch (heap) {
813 case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
814 case RADEON_HEAP_VRAM_32BIT:
815 case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
816 case RADEON_HEAP_GTT_WC_32BIT:
817 case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT:
818 case RADEON_HEAP_GTT_UNCACHED_WC_32BIT:
819 flags |= RADEON_FLAG_32BIT;
820 default:
821 break;
822 }
823
824 switch (heap) {
825 case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
826 flags |= RADEON_FLAG_NO_CPU_ACCESS;
827 break;
828 default:
829 break;
830 }
831
832 return flags;
833 }
834
835 /* Return the heap index for winsys allocators, or -1 on failure. */
radeon_get_heap_index(enum radeon_bo_domain domain,enum radeon_bo_flag flags)836 static inline int radeon_get_heap_index(enum radeon_bo_domain domain, enum radeon_bo_flag flags)
837 {
838 bool uncached;
839
840 /* VRAM implies WC (write combining) */
841 assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
842 /* NO_CPU_ACCESS implies VRAM only. */
843 assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
844
845 /* Resources with interprocess sharing don't use any winsys allocators. */
846 if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
847 return -1;
848
849 /* Unsupported flags: NO_SUBALLOC, SPARSE. */
850 if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_UNCACHED |
851 RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT |
852 RADEON_FLAG_DRIVER_INTERNAL))
853 return -1;
854
855 switch (domain) {
856 case RADEON_DOMAIN_VRAM:
857 switch (flags & (RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT)) {
858 case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
859 case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
860 assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
861 return -1;
862 case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
863 assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
864 return -1;
865 case RADEON_FLAG_NO_CPU_ACCESS:
866 return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
867 case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
868 return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
869 case RADEON_FLAG_READ_ONLY:
870 return RADEON_HEAP_VRAM_READ_ONLY;
871 case RADEON_FLAG_32BIT:
872 return RADEON_HEAP_VRAM_32BIT;
873 case 0:
874 return RADEON_HEAP_VRAM;
875 }
876 break;
877 case RADEON_DOMAIN_GTT:
878 uncached = flags & RADEON_FLAG_UNCACHED;
879
880 switch (flags & (RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT)) {
881 case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
882 return uncached ? RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT
883 : RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
884 case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
885 return uncached ? RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY
886 : RADEON_HEAP_GTT_WC_READ_ONLY;
887 case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
888 return uncached ? RADEON_HEAP_GTT_UNCACHED_WC_32BIT
889 : RADEON_HEAP_GTT_WC_32BIT;
890 case RADEON_FLAG_GTT_WC:
891 return uncached ? RADEON_HEAP_GTT_UNCACHED_WC : RADEON_HEAP_GTT_WC;
892 case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
893 case RADEON_FLAG_READ_ONLY:
894 assert(!"READ_ONLY without WC is disallowed");
895 return -1;
896 case RADEON_FLAG_32BIT:
897 assert(!"32BIT without WC is disallowed");
898 return -1;
899 case 0:
900 return uncached ? RADEON_HEAP_GTT_UNCACHED : RADEON_HEAP_GTT;
901 }
902 break;
903 default:
904 break;
905 }
906 return -1;
907 }
908
909 #endif
910