1 /*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9 #include <string.h>
10
11 #include <platform_def.h>
12
13 #include <arch.h>
14 #include <arch_helpers.h>
15 #include <arch_features.h>
16 #include <bl31/interrupt_mgmt.h>
17 #include <common/bl_common.h>
18 #include <context.h>
19 #include <lib/el3_runtime/context_mgmt.h>
20 #include <lib/el3_runtime/pubsub_events.h>
21 #include <lib/extensions/amu.h>
22 #include <lib/extensions/mpam.h>
23 #include <lib/extensions/spe.h>
24 #include <lib/extensions/sve.h>
25 #include <lib/extensions/twed.h>
26 #include <lib/utils.h>
27
28
29 /*******************************************************************************
30 * Context management library initialisation routine. This library is used by
31 * runtime services to share pointers to 'cpu_context' structures for the secure
32 * and non-secure states. Management of the structures and their associated
33 * memory is not done by the context management library e.g. the PSCI service
34 * manages the cpu context used for entry from and exit to the non-secure state.
35 * The Secure payload dispatcher service manages the context(s) corresponding to
36 * the secure state. It also uses this library to get access to the non-secure
37 * state cpu context pointers.
38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context
39 * which will used for programming an entry into a lower EL. The same context
40 * will used to save state upon exception entry from that EL.
41 ******************************************************************************/
cm_init(void)42 void __init cm_init(void)
43 {
44 /*
45 * The context management library has only global data to intialize, but
46 * that will be done when the BSS is zeroed out
47 */
48 }
49
50 /*******************************************************************************
51 * The following function initializes the cpu_context 'ctx' for
52 * first use, and sets the initial entrypoint state as specified by the
53 * entry_point_info structure.
54 *
55 * The security state to initialize is determined by the SECURE attribute
56 * of the entry_point_info.
57 *
58 * The EE and ST attributes are used to configure the endianness and secure
59 * timer availability for the new execution context.
60 *
61 * To prepare the register state for entry call cm_prepare_el3_exit() and
62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
63 * cm_e1_sysreg_context_restore().
64 ******************************************************************************/
cm_setup_context(cpu_context_t * ctx,const entry_point_info_t * ep)65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
66 {
67 unsigned int security_state;
68 u_register_t scr_el3;
69 el3_state_t *state;
70 gp_regs_t *gp_regs;
71 u_register_t sctlr_elx, actlr_elx;
72
73 assert(ctx != NULL);
74
75 security_state = GET_SECURITY_STATE(ep->h.attr);
76
77 /* Clear any residual register values from the context */
78 zeromem(ctx, sizeof(*ctx));
79
80 /*
81 * SCR_EL3 was initialised during reset sequence in macro
82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
83 * affect the next EL.
84 *
85 * The following fields are initially set to zero and then updated to
86 * the required value depending on the state of the SPSR_EL3 and the
87 * Security state and entrypoint attributes of the next EL.
88 */
89 scr_el3 = read_scr();
90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
91 SCR_ST_BIT | SCR_HCE_BIT);
92 /*
93 * SCR_NS: Set the security state of the next EL.
94 */
95 if (security_state != SECURE)
96 scr_el3 |= SCR_NS_BIT;
97 /*
98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
99 * Exception level as specified by SPSR.
100 */
101 if (GET_RW(ep->spsr) == MODE_RW_64)
102 scr_el3 |= SCR_RW_BIT;
103 /*
104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
105 * Secure timer registers to EL3, from AArch64 state only, if specified
106 * by the entrypoint attributes.
107 */
108 if (EP_GET_ST(ep->h.attr) != 0U)
109 scr_el3 |= SCR_ST_BIT;
110
111 #if RAS_TRAP_LOWER_EL_ERR_ACCESS
112 /*
113 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
114 * and RAS ERX registers from EL1 and EL2 are trapped to EL3.
115 */
116 scr_el3 |= SCR_TERR_BIT;
117 #endif
118
119 #if !HANDLE_EA_EL3_FIRST
120 /*
121 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
122 * to EL3 when executing at a lower EL. When executing at EL3, External
123 * Aborts are taken to EL3.
124 */
125 scr_el3 &= ~SCR_EA_BIT;
126 #endif
127
128 #if FAULT_INJECTION_SUPPORT
129 /* Enable fault injection from lower ELs */
130 scr_el3 |= SCR_FIEN_BIT;
131 #endif
132
133 #if !CTX_INCLUDE_PAUTH_REGS
134 /*
135 * If the pointer authentication registers aren't saved during world
136 * switches the value of the registers can be leaked from the Secure to
137 * the Non-secure world. To prevent this, rather than enabling pointer
138 * authentication everywhere, we only enable it in the Non-secure world.
139 *
140 * If the Secure world wants to use pointer authentication,
141 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
142 */
143 if (security_state == NON_SECURE)
144 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
145 #endif /* !CTX_INCLUDE_PAUTH_REGS */
146
147 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
148 /* Get Memory Tagging Extension support level */
149 unsigned int mte = get_armv8_5_mte_support();
150 #endif
151 /*
152 * Enable MTE support. Support is enabled unilaterally for the normal
153 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
154 * set.
155 */
156 #if CTX_INCLUDE_MTE_REGS
157 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
158 scr_el3 |= SCR_ATA_BIT;
159 #else
160 /*
161 * When MTE is only implemented at EL0, it can be enabled
162 * across both worlds as no MTE registers are used.
163 */
164 if ((mte == MTE_IMPLEMENTED_EL0) ||
165 /*
166 * When MTE is implemented at all ELs, it can be only enabled
167 * in Non-Secure world without register saving.
168 */
169 (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) &&
170 (security_state == NON_SECURE))) {
171 scr_el3 |= SCR_ATA_BIT;
172 }
173 #endif /* CTX_INCLUDE_MTE_REGS */
174
175 #ifdef IMAGE_BL31
176 /*
177 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
178 * indicated by the interrupt routing model for BL31.
179 */
180 scr_el3 |= get_scr_el3_from_routing_model(security_state);
181 #endif
182
183 /*
184 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
185 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
186 * next mode is Hyp.
187 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
188 * same conditions as HVC instructions and when the processor supports
189 * ARMv8.6-FGT.
190 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
191 * CNTPOFF_EL2 register under the same conditions as HVC instructions
192 * and when the processor supports ECV.
193 */
194 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
195 || ((GET_RW(ep->spsr) != MODE_RW_64)
196 && (GET_M32(ep->spsr) == MODE32_hyp))) {
197 scr_el3 |= SCR_HCE_BIT;
198
199 if (is_armv8_6_fgt_present()) {
200 scr_el3 |= SCR_FGTEN_BIT;
201 }
202
203 if (get_armv8_6_ecv_support()
204 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) {
205 scr_el3 |= SCR_ECVEN_BIT;
206 }
207 }
208
209 /* Enable S-EL2 if the next EL is EL2 and security state is secure */
210 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) {
211 if (GET_RW(ep->spsr) != MODE_RW_64) {
212 ERROR("S-EL2 can not be used in AArch32.");
213 panic();
214 }
215
216 scr_el3 |= SCR_EEL2_BIT;
217 }
218
219 /*
220 * Initialise SCTLR_EL1 to the reset value corresponding to the target
221 * execution state setting all fields rather than relying of the hw.
222 * Some fields have architecturally UNKNOWN reset values and these are
223 * set to zero.
224 *
225 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
226 *
227 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
228 * required by PSCI specification)
229 */
230 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
231 if (GET_RW(ep->spsr) == MODE_RW_64)
232 sctlr_elx |= SCTLR_EL1_RES1;
233 else {
234 /*
235 * If the target execution state is AArch32 then the following
236 * fields need to be set.
237 *
238 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
239 * instructions are not trapped to EL1.
240 *
241 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
242 * instructions are not trapped to EL1.
243 *
244 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
245 * CP15DMB, CP15DSB, and CP15ISB instructions.
246 */
247 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
248 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
249 }
250
251 #if ERRATA_A75_764081
252 /*
253 * If workaround of errata 764081 for Cortex-A75 is used then set
254 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
255 */
256 sctlr_elx |= SCTLR_IESB_BIT;
257 #endif
258
259 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
260 if (is_armv8_6_twed_present()) {
261 uint32_t delay = plat_arm_set_twedel_scr_el3();
262
263 if (delay != TWED_DISABLED) {
264 /* Make sure delay value fits */
265 assert((delay & ~SCR_TWEDEL_MASK) == 0U);
266
267 /* Set delay in SCR_EL3 */
268 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
269 scr_el3 |= ((delay & SCR_TWEDEL_MASK)
270 << SCR_TWEDEL_SHIFT);
271
272 /* Enable WFE delay */
273 scr_el3 |= SCR_TWEDEn_BIT;
274 }
275 }
276
277 /*
278 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
279 * and other EL2 registers are set up by cm_prepare_ns_entry() as they
280 * are not part of the stored cpu_context.
281 */
282 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
283
284 /*
285 * Base the context ACTLR_EL1 on the current value, as it is
286 * implementation defined. The context restore process will write
287 * the value from the context to the actual register and can cause
288 * problems for processor cores that don't expect certain bits to
289 * be zero.
290 */
291 actlr_elx = read_actlr_el1();
292 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
293
294 /*
295 * Populate EL3 state so that we've the right context
296 * before doing ERET
297 */
298 state = get_el3state_ctx(ctx);
299 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
300 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
301 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
302
303 /*
304 * Store the X0-X7 value from the entrypoint into the context
305 * Use memcpy as we are in control of the layout of the structures
306 */
307 gp_regs = get_gpregs_ctx(ctx);
308 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
309 }
310
311 /*******************************************************************************
312 * Enable architecture extensions on first entry to Non-secure world.
313 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
314 * it is zero.
315 ******************************************************************************/
enable_extensions_nonsecure(bool el2_unused)316 static void enable_extensions_nonsecure(bool el2_unused)
317 {
318 #if IMAGE_BL31
319 #if ENABLE_SPE_FOR_LOWER_ELS
320 spe_enable(el2_unused);
321 #endif
322
323 #if ENABLE_AMU
324 amu_enable(el2_unused);
325 #endif
326
327 #if ENABLE_SVE_FOR_NS
328 sve_enable(el2_unused);
329 #endif
330
331 #if ENABLE_MPAM_FOR_LOWER_ELS
332 mpam_enable(el2_unused);
333 #endif
334 #endif
335 }
336
337 /*******************************************************************************
338 * The following function initializes the cpu_context for a CPU specified by
339 * its `cpu_idx` for first use, and sets the initial entrypoint state as
340 * specified by the entry_point_info structure.
341 ******************************************************************************/
cm_init_context_by_index(unsigned int cpu_idx,const entry_point_info_t * ep)342 void cm_init_context_by_index(unsigned int cpu_idx,
343 const entry_point_info_t *ep)
344 {
345 cpu_context_t *ctx;
346 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
347 cm_setup_context(ctx, ep);
348 }
349
350 /*******************************************************************************
351 * The following function initializes the cpu_context for the current CPU
352 * for first use, and sets the initial entrypoint state as specified by the
353 * entry_point_info structure.
354 ******************************************************************************/
cm_init_my_context(const entry_point_info_t * ep)355 void cm_init_my_context(const entry_point_info_t *ep)
356 {
357 cpu_context_t *ctx;
358 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
359 cm_setup_context(ctx, ep);
360 }
361
362 /*******************************************************************************
363 * Prepare the CPU system registers for first entry into secure or normal world
364 *
365 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
366 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
367 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
368 * For all entries, the EL1 registers are initialized from the cpu_context
369 ******************************************************************************/
cm_prepare_el3_exit(uint32_t security_state)370 void cm_prepare_el3_exit(uint32_t security_state)
371 {
372 u_register_t sctlr_elx, scr_el3, mdcr_el2;
373 cpu_context_t *ctx = cm_get_context(security_state);
374 bool el2_unused = false;
375 uint64_t hcr_el2 = 0U;
376
377 assert(ctx != NULL);
378
379 if (security_state == NON_SECURE) {
380 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
381 CTX_SCR_EL3);
382 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
383 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
384 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
385 CTX_SCTLR_EL1);
386 sctlr_elx &= SCTLR_EE_BIT;
387 sctlr_elx |= SCTLR_EL2_RES1;
388 #if ERRATA_A75_764081
389 /*
390 * If workaround of errata 764081 for Cortex-A75 is used
391 * then set SCTLR_EL2.IESB to enable Implicit Error
392 * Synchronization Barrier.
393 */
394 sctlr_elx |= SCTLR_IESB_BIT;
395 #endif
396 write_sctlr_el2(sctlr_elx);
397 } else if (el_implemented(2) != EL_IMPL_NONE) {
398 el2_unused = true;
399
400 /*
401 * EL2 present but unused, need to disable safely.
402 * SCTLR_EL2 can be ignored in this case.
403 *
404 * Set EL2 register width appropriately: Set HCR_EL2
405 * field to match SCR_EL3.RW.
406 */
407 if ((scr_el3 & SCR_RW_BIT) != 0U)
408 hcr_el2 |= HCR_RW_BIT;
409
410 /*
411 * For Armv8.3 pointer authentication feature, disable
412 * traps to EL2 when accessing key registers or using
413 * pointer authentication instructions from lower ELs.
414 */
415 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
416
417 write_hcr_el2(hcr_el2);
418
419 /*
420 * Initialise CPTR_EL2 setting all fields rather than
421 * relying on the hw. All fields have architecturally
422 * UNKNOWN reset values.
423 *
424 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
425 * accesses to the CPACR_EL1 or CPACR from both
426 * Execution states do not trap to EL2.
427 *
428 * CPTR_EL2.TTA: Set to zero so that Non-secure System
429 * register accesses to the trace registers from both
430 * Execution states do not trap to EL2.
431 *
432 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
433 * to SIMD and floating-point functionality from both
434 * Execution states do not trap to EL2.
435 */
436 write_cptr_el2(CPTR_EL2_RESET_VAL &
437 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
438 | CPTR_EL2_TFP_BIT));
439
440 /*
441 * Initialise CNTHCTL_EL2. All fields are
442 * architecturally UNKNOWN on reset and are set to zero
443 * except for field(s) listed below.
444 *
445 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to
446 * Hyp mode of Non-secure EL0 and EL1 accesses to the
447 * physical timer registers.
448 *
449 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
450 * Hyp mode of Non-secure EL0 and EL1 accesses to the
451 * physical counter registers.
452 */
453 write_cnthctl_el2(CNTHCTL_RESET_VAL |
454 EL1PCEN_BIT | EL1PCTEN_BIT);
455
456 /*
457 * Initialise CNTVOFF_EL2 to zero as it resets to an
458 * architecturally UNKNOWN value.
459 */
460 write_cntvoff_el2(0);
461
462 /*
463 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
464 * MPIDR_EL1 respectively.
465 */
466 write_vpidr_el2(read_midr_el1());
467 write_vmpidr_el2(read_mpidr_el1());
468
469 /*
470 * Initialise VTTBR_EL2. All fields are architecturally
471 * UNKNOWN on reset.
472 *
473 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
474 * 2 address translation is disabled, cache maintenance
475 * operations depend on the VMID.
476 *
477 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
478 * translation is disabled.
479 */
480 write_vttbr_el2(VTTBR_RESET_VAL &
481 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
482 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
483
484 /*
485 * Initialise MDCR_EL2, setting all fields rather than
486 * relying on hw. Some fields are architecturally
487 * UNKNOWN on reset.
488 *
489 * MDCR_EL2.HLP: Set to one so that event counter
490 * overflow, that is recorded in PMOVSCLR_EL0[0-30],
491 * occurs on the increment that changes
492 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is
493 * implemented. This bit is RES0 in versions of the
494 * architecture earlier than ARMv8.5, setting it to 1
495 * doesn't have any effect on them.
496 *
497 * MDCR_EL2.TTRF: Set to zero so that access to Trace
498 * Filter Control register TRFCR_EL1 at EL1 is not
499 * trapped to EL2. This bit is RES0 in versions of
500 * the architecture earlier than ARMv8.4.
501 *
502 * MDCR_EL2.HPMD: Set to one so that event counting is
503 * prohibited at EL2. This bit is RES0 in versions of
504 * the architecture earlier than ARMv8.1, setting it
505 * to 1 doesn't have any effect on them.
506 *
507 * MDCR_EL2.TPMS: Set to zero so that accesses to
508 * Statistical Profiling control registers from EL1
509 * do not trap to EL2. This bit is RES0 when SPE is
510 * not implemented.
511 *
512 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
513 * EL1 System register accesses to the Debug ROM
514 * registers are not trapped to EL2.
515 *
516 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
517 * System register accesses to the powerdown debug
518 * registers are not trapped to EL2.
519 *
520 * MDCR_EL2.TDA: Set to zero so that System register
521 * accesses to the debug registers do not trap to EL2.
522 *
523 * MDCR_EL2.TDE: Set to zero so that debug exceptions
524 * are not routed to EL2.
525 *
526 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
527 * Monitors.
528 *
529 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
530 * EL1 accesses to all Performance Monitors registers
531 * are not trapped to EL2.
532 *
533 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
534 * and EL1 accesses to the PMCR_EL0 or PMCR are not
535 * trapped to EL2.
536 *
537 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
538 * architecturally-defined reset value.
539 */
540 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
541 MDCR_EL2_HPMD) |
542 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
543 >> PMCR_EL0_N_SHIFT)) &
544 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS |
545 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
546 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
547 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
548 MDCR_EL2_TPMCR_BIT);
549
550 write_mdcr_el2(mdcr_el2);
551
552 /*
553 * Initialise HSTR_EL2. All fields are architecturally
554 * UNKNOWN on reset.
555 *
556 * HSTR_EL2.T<n>: Set all these fields to zero so that
557 * Non-secure EL0 or EL1 accesses to System registers
558 * do not trap to EL2.
559 */
560 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
561 /*
562 * Initialise CNTHP_CTL_EL2. All fields are
563 * architecturally UNKNOWN on reset.
564 *
565 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
566 * physical timer and prevent timer interrupts.
567 */
568 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
569 ~(CNTHP_CTL_ENABLE_BIT));
570 }
571 enable_extensions_nonsecure(el2_unused);
572 }
573
574 cm_el1_sysregs_context_restore(security_state);
575 cm_set_next_eret_context(security_state);
576 }
577
578 #if CTX_INCLUDE_EL2_REGS
579 /*******************************************************************************
580 * Save EL2 sysreg context
581 ******************************************************************************/
cm_el2_sysregs_context_save(uint32_t security_state)582 void cm_el2_sysregs_context_save(uint32_t security_state)
583 {
584 u_register_t scr_el3 = read_scr();
585
586 /*
587 * Always save the non-secure EL2 context, only save the
588 * S-EL2 context if S-EL2 is enabled.
589 */
590 if ((security_state == NON_SECURE) ||
591 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) {
592 cpu_context_t *ctx;
593
594 ctx = cm_get_context(security_state);
595 assert(ctx != NULL);
596
597 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx));
598 }
599 }
600
601 /*******************************************************************************
602 * Restore EL2 sysreg context
603 ******************************************************************************/
cm_el2_sysregs_context_restore(uint32_t security_state)604 void cm_el2_sysregs_context_restore(uint32_t security_state)
605 {
606 u_register_t scr_el3 = read_scr();
607
608 /*
609 * Always restore the non-secure EL2 context, only restore the
610 * S-EL2 context if S-EL2 is enabled.
611 */
612 if ((security_state == NON_SECURE) ||
613 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) {
614 cpu_context_t *ctx;
615
616 ctx = cm_get_context(security_state);
617 assert(ctx != NULL);
618
619 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx));
620 }
621 }
622 #endif /* CTX_INCLUDE_EL2_REGS */
623
624 /*******************************************************************************
625 * The next four functions are used by runtime services to save and restore
626 * EL1 context on the 'cpu_context' structure for the specified security
627 * state.
628 ******************************************************************************/
cm_el1_sysregs_context_save(uint32_t security_state)629 void cm_el1_sysregs_context_save(uint32_t security_state)
630 {
631 cpu_context_t *ctx;
632
633 ctx = cm_get_context(security_state);
634 assert(ctx != NULL);
635
636 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
637
638 #if IMAGE_BL31
639 if (security_state == SECURE)
640 PUBLISH_EVENT(cm_exited_secure_world);
641 else
642 PUBLISH_EVENT(cm_exited_normal_world);
643 #endif
644 }
645
cm_el1_sysregs_context_restore(uint32_t security_state)646 void cm_el1_sysregs_context_restore(uint32_t security_state)
647 {
648 cpu_context_t *ctx;
649
650 ctx = cm_get_context(security_state);
651 assert(ctx != NULL);
652
653 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
654
655 #if IMAGE_BL31
656 if (security_state == SECURE)
657 PUBLISH_EVENT(cm_entering_secure_world);
658 else
659 PUBLISH_EVENT(cm_entering_normal_world);
660 #endif
661 }
662
663 /*******************************************************************************
664 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
665 * given security state with the given entrypoint
666 ******************************************************************************/
cm_set_elr_el3(uint32_t security_state,uintptr_t entrypoint)667 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
668 {
669 cpu_context_t *ctx;
670 el3_state_t *state;
671
672 ctx = cm_get_context(security_state);
673 assert(ctx != NULL);
674
675 /* Populate EL3 state so that ERET jumps to the correct entry */
676 state = get_el3state_ctx(ctx);
677 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
678 }
679
680 /*******************************************************************************
681 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
682 * pertaining to the given security state
683 ******************************************************************************/
cm_set_elr_spsr_el3(uint32_t security_state,uintptr_t entrypoint,uint32_t spsr)684 void cm_set_elr_spsr_el3(uint32_t security_state,
685 uintptr_t entrypoint, uint32_t spsr)
686 {
687 cpu_context_t *ctx;
688 el3_state_t *state;
689
690 ctx = cm_get_context(security_state);
691 assert(ctx != NULL);
692
693 /* Populate EL3 state so that ERET jumps to the correct entry */
694 state = get_el3state_ctx(ctx);
695 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
696 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
697 }
698
699 /*******************************************************************************
700 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
701 * pertaining to the given security state using the value and bit position
702 * specified in the parameters. It preserves all other bits.
703 ******************************************************************************/
cm_write_scr_el3_bit(uint32_t security_state,uint32_t bit_pos,uint32_t value)704 void cm_write_scr_el3_bit(uint32_t security_state,
705 uint32_t bit_pos,
706 uint32_t value)
707 {
708 cpu_context_t *ctx;
709 el3_state_t *state;
710 u_register_t scr_el3;
711
712 ctx = cm_get_context(security_state);
713 assert(ctx != NULL);
714
715 /* Ensure that the bit position is a valid one */
716 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
717
718 /* Ensure that the 'value' is only a bit wide */
719 assert(value <= 1U);
720
721 /*
722 * Get the SCR_EL3 value from the cpu context, clear the desired bit
723 * and set it to its new value.
724 */
725 state = get_el3state_ctx(ctx);
726 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
727 scr_el3 &= ~(1UL << bit_pos);
728 scr_el3 |= (u_register_t)value << bit_pos;
729 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
730 }
731
732 /*******************************************************************************
733 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
734 * given security state.
735 ******************************************************************************/
cm_get_scr_el3(uint32_t security_state)736 u_register_t cm_get_scr_el3(uint32_t security_state)
737 {
738 cpu_context_t *ctx;
739 el3_state_t *state;
740
741 ctx = cm_get_context(security_state);
742 assert(ctx != NULL);
743
744 /* Populate EL3 state so that ERET jumps to the correct entry */
745 state = get_el3state_ctx(ctx);
746 return read_ctx_reg(state, CTX_SCR_EL3);
747 }
748
749 /*******************************************************************************
750 * This function is used to program the context that's used for exception
751 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
752 * the required security state
753 ******************************************************************************/
cm_set_next_eret_context(uint32_t security_state)754 void cm_set_next_eret_context(uint32_t security_state)
755 {
756 cpu_context_t *ctx;
757
758 ctx = cm_get_context(security_state);
759 assert(ctx != NULL);
760
761 cm_set_next_context(ctx);
762 }
763