1/* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpuamu.h> 10 11 .globl cpuamu_cnt_read 12 .globl cpuamu_cnt_write 13 .globl cpuamu_read_cpuamcntenset_el0 14 .globl cpuamu_read_cpuamcntenclr_el0 15 .globl cpuamu_write_cpuamcntenset_el0 16 .globl cpuamu_write_cpuamcntenclr_el0 17 18/* 19 * uint64_t cpuamu_cnt_read(unsigned int idx); 20 * 21 * Given `idx`, read the corresponding AMU counter 22 * and return it in `x0`. 23 */ 24func cpuamu_cnt_read 25 adr x1, 1f 26 add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */ 27#if ENABLE_BTI 28 add x1, x1, x0, lsl #2 /* + "bti j" instruction */ 29#endif 30 br x1 31 321: read CPUAMEVCNTR0_EL0 33 read CPUAMEVCNTR1_EL0 34 read CPUAMEVCNTR2_EL0 35 read CPUAMEVCNTR3_EL0 36 read CPUAMEVCNTR4_EL0 37endfunc cpuamu_cnt_read 38 39/* 40 * void cpuamu_cnt_write(unsigned int idx, uint64_t val); 41 * 42 * Given `idx`, write `val` to the corresponding AMU counter. 43 */ 44func cpuamu_cnt_write 45 adr x2, 1f 46 add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */ 47#if ENABLE_BTI 48 add x2, x2, x0, lsl #2 /* + "bti j" instruction */ 49#endif 50 br x2 51 521: write CPUAMEVCNTR0_EL0 53 write CPUAMEVCNTR1_EL0 54 write CPUAMEVCNTR2_EL0 55 write CPUAMEVCNTR3_EL0 56 write CPUAMEVCNTR4_EL0 57endfunc cpuamu_cnt_write 58 59/* 60 * unsigned int cpuamu_read_cpuamcntenset_el0(void); 61 * 62 * Read the `CPUAMCNTENSET_EL0` CPU register and return 63 * it in `x0`. 64 */ 65func cpuamu_read_cpuamcntenset_el0 66 mrs x0, CPUAMCNTENSET_EL0 67 ret 68endfunc cpuamu_read_cpuamcntenset_el0 69 70/* 71 * unsigned int cpuamu_read_cpuamcntenclr_el0(void); 72 * 73 * Read the `CPUAMCNTENCLR_EL0` CPU register and return 74 * it in `x0`. 75 */ 76func cpuamu_read_cpuamcntenclr_el0 77 mrs x0, CPUAMCNTENCLR_EL0 78 ret 79endfunc cpuamu_read_cpuamcntenclr_el0 80 81/* 82 * void cpuamu_write_cpuamcntenset_el0(unsigned int mask); 83 * 84 * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. 85 */ 86func cpuamu_write_cpuamcntenset_el0 87 msr CPUAMCNTENSET_EL0, x0 88 ret 89endfunc cpuamu_write_cpuamcntenset_el0 90 91/* 92 * void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); 93 * 94 * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. 95 */ 96func cpuamu_write_cpuamcntenclr_el0 97 msr CPUAMCNTENCLR_EL0, x0 98 ret 99endfunc cpuamu_write_cpuamcntenclr_el0 100