1 #include <stdint.h>
2
3 #include <cpuinfo.h>
4 #include <cpuinfo/internal-api.h>
5 #include <cpuinfo/log.h>
6 #include <arm/api.h>
7 #include <arm/midr.h>
8
9
cpuinfo_arm_decode_cache(enum cpuinfo_uarch uarch,uint32_t cluster_cores,uint32_t midr,const struct cpuinfo_arm_chipset chipset[restrict static1],uint32_t cluster_id,uint32_t arch_version,struct cpuinfo_cache l1i[restrict static1],struct cpuinfo_cache l1d[restrict static1],struct cpuinfo_cache l2[restrict static1],struct cpuinfo_cache l3[restrict static1])10 void cpuinfo_arm_decode_cache(
11 enum cpuinfo_uarch uarch,
12 uint32_t cluster_cores,
13 uint32_t midr,
14 const struct cpuinfo_arm_chipset chipset[restrict static 1],
15 uint32_t cluster_id,
16 uint32_t arch_version,
17 struct cpuinfo_cache l1i[restrict static 1],
18 struct cpuinfo_cache l1d[restrict static 1],
19 struct cpuinfo_cache l2[restrict static 1],
20 struct cpuinfo_cache l3[restrict static 1])
21 {
22 switch (uarch) {
23 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__)
24 case cpuinfo_uarch_xscale:
25 switch (midr_get_part(midr) >> 8) {
26 case 2:
27 /*
28 * PXA 210/25X/26X
29 *
30 * See "Computer Organization and Design, Revised Printing: The Hardware/Software Interface"
31 * by David A. Patterson, John L. Hennessy
32 */
33 *l1i = (struct cpuinfo_cache) {
34 .size = 16 * 1024,
35 .associativity = 32,
36 .line_size = 32
37 };
38 *l1d = (struct cpuinfo_cache) {
39 .size = 16 * 1024,
40 .associativity = 4,
41 .line_size = 64
42 };
43 break;
44 case 4:
45 /* PXA 27X */
46 *l1i = (struct cpuinfo_cache) {
47 .size = 32 * 1024,
48 .associativity = 32,
49 .line_size = 32
50 };
51 *l1d = (struct cpuinfo_cache) {
52 .size = 32 * 1024,
53 .associativity = 32,
54 .line_size = 32
55 };
56 break;
57 case 6:
58 /*
59 * PXA 3XX
60 *
61 * See http://download.intel.com/design/intelxscale/31628302.pdf
62 */
63 *l1i = (struct cpuinfo_cache) {
64 .size = 32 * 1024,
65 .associativity = 4,
66 .line_size = 32
67 };
68 *l1d = (struct cpuinfo_cache) {
69 .size = 32 * 1024,
70 .associativity = 4,
71 .line_size = 32
72 };
73 *l2 = (struct cpuinfo_cache) {
74 .size = 256 * 1024,
75 .associativity = 8,
76 .line_size = 32
77 };
78 break;
79 }
80 break;
81 case cpuinfo_uarch_arm11:
82 *l1i = (struct cpuinfo_cache) {
83 .size = 16 * 1024,
84 .associativity = 4,
85 .line_size = 32
86 };
87 *l1d = (struct cpuinfo_cache) {
88 .size = 16 * 1024,
89 .associativity = 4,
90 .line_size = 32
91 };
92 break;
93 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) */
94 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
95 case cpuinfo_uarch_cortex_a5:
96 /*
97 * Cortex-A5 Technical Reference Manual:
98 * 7.1.1. Memory system
99 * The Cortex-A5 processor has separate instruction and data caches.
100 * The caches have the following features:
101 * - Data cache is 4-way set-associative.
102 * - Instruction cache is 2-way set-associative.
103 * - The cache line length is eight words.
104 * - You can configure the instruction and data caches independently during implementation
105 * to sizes of 4KB, 8KB, 16KB, 32KB, or 64KB.
106 * 1.1.3. System design components
107 * PrimeCell Level 2 Cache Controller (PL310)
108 * The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a
109 * recognized method of improving the performance of ARM-based systems when significant memory traffic
110 * is generated by the processor. The PrimeCell Level 2 Cache Controller reduces the number of external
111 * memory accesses and has been optimized for use with the Cortex-A5 processor.
112 * 8.1.7. Exclusive L2 cache
113 * The Cortex-A5 processor can be connected to an L2 cache that supports an exclusive cache mode.
114 * This mode must be activated both in the Cortex-A5 processor and in the L2 cache controller.
115 *
116 * +--------------------+-----------+-----------+----------+-----------+
117 * | Processor model | L1D cache | L1I cache | L2 cache | Reference |
118 * +--------------------+-----------+-----------+----------+-----------+
119 * | Qualcomm MSM7225A | | | | |
120 * | Qualcomm MSM7625A | | | | |
121 * | Qualcomm MSM7227A | | | | |
122 * | Qualcomm MSM7627A | 32K | 32K | 256K | Wiki [1] |
123 * | Qualcomm MSM7225AB | | | | |
124 * | Qualcomm MSM7225AB | | | | |
125 * | Qualcomm QSD8250 | | | | |
126 * | Qualcomm QSD8650 | | | | |
127 * +--------------------+-----------+-----------+----------+-----------+
128 * | Spreadtrum SC6821 | 32K | 32K | ? | |
129 * | Spreadtrum SC6825 | 32K | 32K | 256K | Wiki [2] |
130 * | Spreadtrum SC8810 | ? | ? | ? | |
131 * | Spreadtrum SC8825 | 32K | 32K | ? | |
132 * +--------------------+-----------+-----------+----------+-----------+
133 *
134 * [1] https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1
135 * [2] https://en.wikipedia.org/wiki/Spreadtrum
136 */
137 *l1i = (struct cpuinfo_cache) {
138 .size = 32 * 1024,
139 .associativity = 2,
140 .line_size = 32
141 };
142 *l1d = (struct cpuinfo_cache) {
143 .size = 32 * 1024,
144 .associativity = 4,
145 .line_size = 32
146 };
147 *l2 = (struct cpuinfo_cache) {
148 .size = 256 * 1024,
149 /*
150 * Follow NXP specification: "Eight-way set-associative 512 kB L2 cache with 32B line size"
151 * Reference: http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf
152 */
153 .associativity = 8,
154 .line_size = 32
155 };
156 break;
157 case cpuinfo_uarch_cortex_a7:
158 /*
159 * Cortex-A7 MPCore Technical Reference Manual:
160 * 6.1. About the L1 memory system
161 * The L1 memory system consists of separate instruction and data caches. You can configure the
162 * instruction and data caches independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB.
163 *
164 * The L1 instruction memory system has the following features:
165 * - Instruction side cache line length of 32-bytes.
166 * - 2-way set-associative instruction cache.
167 *
168 * The L1 data memory system has the following features:
169 * - Data side cache line length of 64-bytes.
170 * - 4-way set-associative data cache.
171 *
172 * 7.1. About the L2 Memory system
173 * The L2 memory system consists of an:
174 * - Optional tightly-coupled L2 cache that includes:
175 * - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB.
176 * - Fixed line length of 64 bytes
177 * - 8-way set-associative cache structure
178 *
179 * +--------------------+-------+-----------+-----------+-----------+-----------+
180 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
181 * +--------------------+-------+-----------+-----------+-----------+-----------+
182 * | Allwinner A20 | 2 | 32K | 32K | 256K | [1] |
183 * | Allwinner A23 | 2 | 32K | 32K | 256K | [2] |
184 * | Allwinner A31 | 4 | 32K | 32K | 1M | [3] |
185 * | Allwinner A31s | 4 | 32K | 32K | 1M | [4] |
186 * | Allwinner A33 | 4 | 32K | 32K | 512K | [5] |
187 * | Allwinner A80 Octa | 4(+4) | 32K | 32K | 512K(+2M) | [6] |
188 * | Allwinner A81T | 8 | 32K | 32K | 1M | [7] |
189 * +--------------------+-------+-----------+-----------+-----------+-----------+
190 * | Broadcom BCM2836 | 4 | 32K | 32K | 512K | [8] |
191 * +--------------------+-------+-----------+-----------+-----------+-----------+
192 * | Kirin 920 | 4(+4) | ? | ? | 512K | [9] |
193 * +--------------------+-------+-----------+-----------+-----------+-----------+
194 *
195 * [1] https://linux-sunxi.org/A20
196 * [2] https://linux-sunxi.org/A23
197 * [3] http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf
198 * [4] https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf
199 * [5] http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf
200 * [6] https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf
201 * [7] http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
202 * [8] https://www.raspberrypi.org/forums/viewtopic.php?t=98428
203 * [9] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/
204 */
205 *l1i = (struct cpuinfo_cache) {
206 .size = 32 * 1024,
207 .associativity = 2,
208 .line_size = 32
209 };
210 *l1d = (struct cpuinfo_cache) {
211 .size = 32 * 1024,
212 .associativity = 4,
213 .line_size = 64
214 };
215 *l2 = (struct cpuinfo_cache) {
216 .size = 128 * 1024 * cluster_cores,
217 .associativity = 8,
218 .line_size = 64
219 };
220 break;
221 case cpuinfo_uarch_cortex_a8:
222 /*
223 * Cortex-A8 Technical Reference Manual:
224 * 7.1. About the L1 memory system
225 * The L1 memory system consists of separate instruction and data caches in a Harvard arrangement.
226 * The L1 memory system provides the core with:
227 * - fixed line length of 64 bytes
228 * - support for 16KB or 32KB caches
229 * - 4-way set associative cache structure
230 * 8.1. About the L2 memory system
231 * The L2 memory system is tightly coupled to the L1 data cache and L1 instruction cache.
232 * The key features of the L2 memory system include:
233 * - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB
234 * - fixed line length of 64 bytes
235 * - 8-way set associative cache structure
236 *
237 * +----------------------+-----------+-----------+-----------+-----------+
238 * | Processor model | L1D cache | L1I cache | L2 cache | Reference |
239 * +----------------------+-----------+-----------+-----------+-----------+
240 * | Exynos 3 Single 3110 | 32K | 32K | 512K | [1] |
241 * +----------------------+-----------+-----------+-----------+-----------+
242 * | TI DM 3730 | 32K | 32K | 256K | [2] |
243 * +----------------------+-----------+-----------+-----------+-----------+
244 *
245 * [1] https://en.wikichip.org/w/images/0/04/Exynos_3110.pdf
246 * [2] https://www.ti.com/lit/ds/symlink/dm3725.pdf
247 */
248 *l1i = (struct cpuinfo_cache) {
249 .size = 32 * 1024,
250 .associativity = 4,
251 .line_size = 64
252 };
253 *l1d = (struct cpuinfo_cache) {
254 .size = 32 * 1024,
255 .associativity = 4,
256 .line_size = 64
257 };
258 *l2 = (struct cpuinfo_cache) {
259 .associativity = 8,
260 .line_size = 64
261 };
262 switch (chipset->vendor) {
263 case cpuinfo_arm_chipset_vendor_samsung:
264 l2->size = 512 * 1024;
265 break;
266 default:
267 l2->size = 256 * 1024;
268 break;
269 }
270
271 break;
272 case cpuinfo_uarch_cortex_a9:
273 /*
274 * ARM Cortex‑A9 Technical Reference Manual:
275 * 7.1.1 Memory system
276 * The Cortex‑A9 processor has separate instruction and data caches.
277 * The caches have the following features:
278 * - Both caches are 4-way set-associative.
279 * - The cache line length is eight words.
280 * - You can configure the instruction and data caches independently during implementation
281 * to sizes of 16KB, 32KB, or 64KB.
282 * 8.1.5 Exclusive L2 cache
283 * The Cortex‑A9 processor can be connected to an L2 cache that supports an exclusive cache mode.
284 * This mode must be activated both in the Cortex‑A9 processor and in the L2 cache controller.
285 *
286 * +--------------------+-------+-----------+-----------+-----------+-----------+
287 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
288 * +--------------------+-------+-----------+-----------+-----------+-----------+
289 * | Exynos 4 Dual 4210 | 2 | 32K | 32K | 1M | [1] |
290 * | Exynos 4 Dual 4212 | 2 | 32K | 32K | 1M | [2] |
291 * | Exynos 4 Quad 4412 | 4 | 32K | 32K | 1M | [3] |
292 * | Exynos 4 Quad 4415 | 4 | 32K | 32K | 1M | |
293 * | TI OMAP 4430 | 2 | 32K | 32K | 1M | [4] |
294 * | TI OMAP 4460 | 2 | 32K | 32K | 1M | [5] |
295 * +--------------------+-------+-----------+-----------+-----------+-----------+
296 *
297 * [1] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf
298 * [2] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf
299 * [3] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf
300 * [4] https://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.421.Witt-OMAP4430.pdf
301 * [5] http://www.anandtech.com/show/5310/samsung-galaxy-nexus-ice-cream-sandwich-review/9
302 */
303
304 /* Use Exynos 4 specs */
305 *l1i = (struct cpuinfo_cache) {
306 .size = 32 * 1024,
307 .associativity = 4,
308 .line_size = 32
309 };
310 *l1d = (struct cpuinfo_cache) {
311 .size = 32 * 1024,
312 .associativity = 4,
313 .line_size = 32
314 };
315 *l2 = (struct cpuinfo_cache) {
316 .size = 1024 * 1024,
317 /* OMAP4460 in Pandaboard ES has 16-way set-associative L2 cache */
318 .associativity = 16,
319 .line_size = 32
320 };
321 break;
322 case cpuinfo_uarch_cortex_a15:
323 /*
324 * 6.1. About the L1 memory system
325 * The L1 memory system consists of separate instruction and data caches.
326 * The L1 instruction memory system has the following features:
327 * - 32KB 2-way set-associative instruction cache.
328 * - Fixed line length of 64 bytes.
329 * The L1 data memory system has the following features:
330 * - 32KB 2-way set-associative data cache.
331 * - Fixed line length of 64 bytes.
332 * 7.1. About the L2 memory system
333 * The features of the L2 memory system include:
334 * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
335 * - Fixed line length of 64 bytes.
336 * - 16-way set-associative cache structure.
337 *
338 * +--------------------+-------+-----------+-----------+-----------+-----------+
339 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
340 * +--------------------+-------+-----------+-----------+-----------+-----------+
341 * | Exynos 5 Dual 5250 | 2 | 32K | 32K | 1M | [1] |
342 * | Exynos 5 Hexa 5260 | 2(+4) | 32K | 32K | 1M(+512K) | [2] |
343 * | Exynos 5 Octa 5410 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
344 * | Exynos 5 Octa 5420 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
345 * | Exynos 5 Octa 5422 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
346 * | Exynos 5 Octa 5430 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
347 * | Exynos 5 Octa 5800 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
348 * | Kirin 920 | 4(+4) | ? | ? | 2M(+512K) | [4] |
349 * +--------------------+-------+-----------+-----------+-----------+-----------+
350 *
351 * [1] http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf
352 * [2] http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf
353 * [3] http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13
354 * [4] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/
355 */
356 *l1i = (struct cpuinfo_cache) {
357 .size = 32 * 1024,
358 .associativity = 2,
359 .line_size = 64
360 };
361 *l1d = (struct cpuinfo_cache) {
362 .size = 32 * 1024,
363 .associativity = 2,
364 .line_size = 64
365 };
366 *l2 = (struct cpuinfo_cache) {
367 .size = cluster_cores * 512 * 1024,
368 .associativity = 16,
369 .line_size = 64
370 };
371 break;
372 case cpuinfo_uarch_cortex_a17:
373 /*
374 * ARM Cortex-A17 MPCore Processor Technical Reference Manual:
375 * 6.1. About the L1 memory system
376 * The L1 memory system consists of separate instruction and data caches.
377 * The size of the instruction cache is implemented as either 32KB or 64KB.
378 * The size of the data cache is 32KB.
379 *
380 * The L1 instruction cache has the following features:
381 * - Instruction side cache line length of 64-bytes.
382 * - 4-way set-associative instruction cache.
383 *
384 * The L1 data cache has the following features:
385 * - Data side cache line length of 64-bytes.
386 * - 4-way set-associative data cache.
387 *
388 * 7.1. About the L2 Memory system
389 * An integrated L2 cache:
390 * - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB.
391 * - A fixed line length of 64 bytes.
392 * - 16-way set-associative cache structure.
393 *
394 * +------------------+-------+-----------+-----------+-----------+-----------+
395 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
396 * +------------------+-------+-----------+-----------+-----------+-----------+
397 * | MediaTek MT6595 | 4(+4) | 32K | 32K | 2M(+512K) | [1] |
398 * +------------------+-------+-----------+-----------+-----------+-----------+
399 *
400 * [1] https://blog.osakana.net/archives/5268
401 */
402 *l1i = (struct cpuinfo_cache) {
403 .size = 32 * 1024,
404 .associativity = 4,
405 .line_size = 64
406 };
407 *l1d = (struct cpuinfo_cache) {
408 .size = 32 * 1024,
409 .associativity = 4,
410 .line_size = 64
411 };
412 *l2 = (struct cpuinfo_cache) {
413 .size = cluster_cores * 512 * 1024,
414 .associativity = 16,
415 .line_size = 64
416 };
417 break;
418 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */
419 case cpuinfo_uarch_cortex_a35:
420 /*
421 * ARM Cortex‑A35 Processor Technical Reference Manual:
422 * 6.1. About the L1 memory system
423 * The L1 memory system includes several power-saving and performance-enhancing features.
424 * These include separate instruction and data caches, which can be configured
425 * independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB.
426 *
427 * L1 instruction-side memory system
428 * A dedicated instruction cache that:
429 * - is virtually indexed and physically tagged.
430 * - is 2-way set associative.
431 * - is configurable to be 8KB, 16KB, 32KB, or 64KB.
432 * - uses a cache line length of 64 bytes.
433 *
434 * L1 data-side memory system
435 * A dedicated data cache that:
436 * - is physically indexed and physically tagged.
437 * - is 4-way set associative.
438 * - is configurable to be 8KB, 16KB, 32KB, or 64KB.
439 * - uses a cache line length of 64 bytes.
440 *
441 * 7.1. About the L2 memory system
442 * The L2 cache is 8-way set associative.
443 * Further features of the L2 cache are:
444 * - Configurable size of 128KB, 256KB, 512KB, and 1MB.
445 * - Fixed line length of 64 bytes.
446 * - Physically indexed and tagged.
447 *
448 * +-----------------+---------+-----------+-----------+-----------+-----------+
449 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
450 * +-----------------+---------+-----------+-----------+-----------+-----------+
451 * | MediaTek MT6599 | 4(+4+2) | ? | ? | ? | |
452 * +-----------------+---------+-----------+-----------+-----------+-----------+
453 */
454 *l1i = (struct cpuinfo_cache) {
455 .size = 16 * 1024, /* assumption based on low-end Cortex-A53 */
456 .associativity = 2,
457 .line_size = 64
458 };
459 *l1d = (struct cpuinfo_cache) {
460 .size = 16 * 1024, /* assumption based on low-end Cortex-A53 */
461 .associativity = 4,
462 .line_size = 64
463 };
464 *l2 = (struct cpuinfo_cache) {
465 .size = 256 * 1024, /* assumption based on low-end Cortex-A53 */
466 .associativity = 8,
467 .line_size = 64
468 };
469 break;
470 case cpuinfo_uarch_cortex_a53:
471 /*
472 * ARM Cortex-A53 MPCore Processor Technical Reference Manual:
473 * 6.1. About the L1 memory system
474 * The L1 memory system consists of separate instruction and data caches. The implementer configures the
475 * instruction and data caches independently during implementation, to sizes of 8KB, 16KB, 32KB, or 64KB.
476 *
477 * The L1 Instruction memory system has the following key features:
478 * - Instruction side cache line length of 64 bytes.
479 * - 2-way set associative L1 Instruction cache.
480 *
481 * The L1 Data memory system has the following features:
482 * - Data side cache line length of 64 bytes.
483 * - 4-way set associative L1 Data cache.
484 *
485 * 7.1. About the L2 memory system
486 * The L2 memory system consists of an:
487 * - Optional tightly-coupled L2 cache that includes:
488 * - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB.
489 * - Fixed line length of 64 bytes.
490 * - 16-way set-associative cache structure.
491 *
492 * +--------------------+-------+-----------+-----------+-----------+-----------+
493 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
494 * +--------------------+-------+-----------+-----------+-----------+-----------+
495 * | Broadcom BCM2837 | 4 | 16K | 16K | 512K | [1] |
496 * | Exynos 7420 | 4(+4) | 32K | 32K | 256K | [2, 3] |
497 * | Exynos 8890 | 4(+4) | 32K | 32K | 256K | [4] |
498 * | Rochchip RK3368 | 4+4 | 32K | 32K | 512K+256K | sysfs |
499 * | MediaTek MT8173C | 2(+2) | 32K | 32K | 512K(+1M) | sysfs |
500 * | Snapdragon 410 | 4 | 32K | 32K | 512K | [3] |
501 * | Snapdragon 630 | 4+4 | 32K | 32K | 1M+512K | sysfs |
502 * | Snapdragon 636 | 4(+4) | 32K+64K | 32K+64K | 1M+1M | sysfs |
503 * | Snapdragon 660 | 4(+4) | 32K+64K | 32K+64K | 1M+1M | sysfs |
504 * | Snapdragon 835 | 4(+4) | 32K+64K | 32K+64K | 1M(+2M) | sysfs |
505 * | Kirin 620 | 4+4 | 32K | 32K | 512K | [5] |
506 * +--------------------+-------+-----------+-----------+-----------+-----------+
507 *
508 * [1] https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766
509 * [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2
510 * [3] https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_lipp.pdf
511 * [4] http://www.boardset.com/products/products_v8890.php
512 * [5] http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
513 */
514 if (midr_is_qualcomm_cortex_a53_silver(midr)) {
515 /* Qualcomm-modified Cortex-A53 in Snapdragon 630/660/835 */
516
517 uint32_t l2_size = 512 * 1024;
518 switch (chipset->series) {
519 case cpuinfo_arm_chipset_series_qualcomm_msm:
520 if (chipset->model == 8998) {
521 /* Snapdragon 835 (MSM8998): 1 MB L2 (little cores only) */
522 l2_size = 1024 * 1024;
523 }
524 break;
525 case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
526 switch (chipset->model) {
527 case 630:
528 if (cluster_id == 0) {
529 /* Snapdragon 630: 1 MB L2 for the big cores */
530 l2_size = 1024 * 1024;
531 }
532 break;
533 case 636:
534 /* Snapdragon 636: 1 MB L2 (little cores only) */
535 l2_size = 1024 * 1024;
536 break;
537 case 660:
538 /* Snapdragon 660: 1 MB L2 (little cores only) */
539 l2_size = 1024 * 1024;
540 break;
541 }
542 break;
543 default:
544 break;
545 }
546
547 *l1i = (struct cpuinfo_cache) {
548 .size = 32 * 1024,
549 .associativity = 2,
550 .line_size = 64
551 };
552 *l1d = (struct cpuinfo_cache) {
553 .size = 32 * 1024,
554 .associativity = 4,
555 .line_size = 64
556 };
557 *l2 = (struct cpuinfo_cache) {
558 .size = l2_size,
559 .associativity = 16,
560 .line_size = 64
561 };
562 } else {
563 /* Standard Cortex-A53 */
564
565 /* Use conservative values by default */
566 uint32_t l1_size = 16 * 1024;
567 uint32_t l2_size = 256 * 1024;
568 switch (chipset->series) {
569 case cpuinfo_arm_chipset_series_qualcomm_msm:
570 l1_size = 32 * 1024;
571 l2_size = 512 * 1024;
572 switch (chipset->model) {
573 case 8937: /* Snapdragon 430 */
574 case 8940: /* Snapdragon 435 */
575 case 8953: /* Snapdragon 625 or 626 (8953PRO) */
576 if (cluster_id == 0) {
577 /* 1M L2 for big cluster */
578 l2_size = 1024 * 1024;
579 }
580 break;
581 case 8952: /* Snapdragon 617 */
582 if (cluster_id != 0) {
583 /* 256K L2 for LITTLE cluster */
584 l2_size = 256 * 1024;
585 }
586 break;
587 default:
588 /* Silence compiler warning about unhandled enum values */
589 break;
590 }
591 break;
592 case cpuinfo_arm_chipset_series_qualcomm_apq:
593 l1_size = 32 * 1024;
594 l2_size = 512 * 1024;
595 break;
596 case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
597 l1_size = 32 * 1024;
598 l2_size = 512 * 1024;
599 if (chipset->model == 450 && cluster_id == 0) {
600 /* Snapdragon 450: 1M L2 for big cluster */
601 l2_size = 1024 * 1024;
602 }
603 break;
604 case cpuinfo_arm_chipset_series_hisilicon_hi:
605 l1_size = 32 * 1024;
606 l2_size = 512 * 1024;
607 break;
608 case cpuinfo_arm_chipset_series_hisilicon_kirin:
609 l1_size = 32 * 1024;
610 switch (chipset->model) {
611 case 970: /* Kirin 970 */
612 l2_size = 1024 * 1024;
613 break;
614 default:
615 l2_size = 512 * 1024;
616 break;
617 }
618 break;
619 case cpuinfo_arm_chipset_series_mediatek_mt:
620 switch (chipset->model) {
621 case 8173:
622 l1_size = 32 * 1024;
623 l2_size = 512 * 1024;
624 break;
625 }
626 break;
627 case cpuinfo_arm_chipset_series_rockchip_rk:
628 l1_size = 32 * 1024;
629 switch (chipset->model) {
630 case 3368:
631 if (cluster_id == 0) {
632 /* RK3368: 512 KB L2 for the big cores */
633 l2_size = 512 * 1024;
634 }
635 break;
636 }
637 break;
638 case cpuinfo_arm_chipset_series_broadcom_bcm:
639 switch (chipset->model) {
640 case 2837: /* BCM2837 */
641 l2_size = 512 * 1024;
642 break;
643 }
644 break;
645 case cpuinfo_arm_chipset_series_samsung_exynos:
646 l1_size = 32 * 1024;
647 break;
648 default:
649 /* Silence compiler warning about unhandled enum values */
650 break;
651 }
652 *l1i = (struct cpuinfo_cache) {
653 .size = l1_size,
654 .associativity = 2,
655 .line_size = 64
656 };
657 *l1d = (struct cpuinfo_cache) {
658 .size = l1_size,
659 .associativity = 4,
660 .line_size = 64
661 };
662 *l2 = (struct cpuinfo_cache) {
663 .size = l2_size,
664 .associativity = 16,
665 .line_size = 64
666 };
667 }
668 break;
669 case cpuinfo_uarch_cortex_a55r0:
670 case cpuinfo_uarch_cortex_a55:
671 /*
672 * ARM Cortex-A55 Core Technical Reference Manual
673 * A6.1. About the L1 memory system
674 * The Cortex®-A55 core's L1 memory system enhances core performance and power efficiency.
675 * It consists of separate instruction and data caches. You can configure instruction and data caches
676 * independently during implementation to sizes of 16KB, 32KB, or 64KB.
677 *
678 * L1 instruction-side memory system
679 * The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are:
680 * - 64-byte instruction side cache line length.
681 * - 4-way set associative L1 instruction cache.
682 *
683 * L1 data-side memory system
684 * - 64-byte data side cache line length.
685 * - 4-way set associative L1 data cache.
686 *
687 * A7.1 About the L2 memory system
688 * The Cortex-A55 L2 memory system is required to interface the Cortex-A55 cores to the L3 memory system.
689 * The L2 memory subsystem consists of:
690 * - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB or 256KB. Cache
691 * lines have a fixed length of 64 bytes.
692 *
693 * The main features of the L2 memory system are:
694 * - Strictly exclusive with L1 data cache.
695 * - Pseudo-inclusive with L1 instruction cache.
696 * - Private per-core unified L2 cache.
697 *
698 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
699 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
700 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
701 * | Snapdragon 845 | 4(+4) | 32K | 32K | 128K | 2M | [1], sysfs |
702 * | Exynos 9810 | 4(+4) | ? | ? | None | 512K | [2] |
703 * | Kirin 980 | 4(+4) | 32K | 32K | 128K | 4M | [3] |
704 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
705 *
706 * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
707 * [2] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
708 * [3] https://en.wikichip.org/wiki/hisilicon/kirin/980
709 */
710 if (midr_is_qualcomm_cortex_a55_silver(midr)) {
711 /* Qualcomm-modified Cortex-A55 in Snapdragon 670 / 710 / 845 */
712 uint32_t l3_size = 1024 * 1024;
713 switch (chipset->series) {
714 case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
715 /* Snapdragon 845: 2M L3 cache */
716 if (chipset->model == 845) {
717 l3_size = 2 * 1024 * 1024;
718 }
719 break;
720 default:
721 break;
722 }
723
724 *l1i = (struct cpuinfo_cache) {
725 .size = 32 * 1024,
726 .associativity = 4,
727 .line_size = 64,
728 };
729 *l1d = (struct cpuinfo_cache) {
730 .size = 32 * 1024,
731 .associativity = 4,
732 .line_size = 64,
733 };
734 *l2 = (struct cpuinfo_cache) {
735 .size = 128 * 1024,
736 .associativity = 4,
737 .line_size = 64,
738 };
739 *l3 = (struct cpuinfo_cache) {
740 .size = l3_size,
741 .associativity = 16,
742 .line_size = 64,
743 };
744 } else {
745 /* Standard Cortex-A55 */
746
747 *l1i = (struct cpuinfo_cache) {
748 .size = 32 * 1024,
749 .associativity = 4,
750 .line_size = 64,
751 };
752 *l1d = (struct cpuinfo_cache) {
753 .size = 32 * 1024,
754 .associativity = 4,
755 .line_size = 64,
756 };
757 if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos) {
758 *l2 = (struct cpuinfo_cache) {
759 .size = 512 * 1024,
760 /* DynamIQ */
761 .associativity = 16,
762 .line_size = 64,
763 };
764 } else {
765 uint32_t l3_size = 1024 * 1024;
766 switch (chipset->series) {
767 case cpuinfo_arm_chipset_series_hisilicon_kirin:
768 /* Kirin 980: 4M L3 cache */
769 if (chipset->model == 980) {
770 l3_size = 4 * 1024 * 1024;
771 }
772 break;
773 default:
774 break;
775 }
776 *l2 = (struct cpuinfo_cache) {
777 .size = 128 * 1024,
778 .associativity = 4,
779 .line_size = 64,
780 };
781 *l3 = (struct cpuinfo_cache) {
782 .size = l3_size,
783 /* DynamIQ */
784 .associativity = 16,
785 .line_size = 64,
786 };
787 }
788 }
789 break;
790 case cpuinfo_uarch_cortex_a57:
791 /*
792 * ARM Cortex-A57 MPCore Processor Technical Reference Manual:
793 * 6.1. About the L1 memory system
794 * The L1 memory system consists of separate instruction and data caches.
795 *
796 * The L1 instruction memory system has the following features:
797 * - 48KB 3-way set-associative instruction cache.
798 * - Fixed line length of 64 bytes.
799 *
800 * The L1 data memory system has the following features:
801 * - 32KB 2-way set-associative data cache.
802 * - Fixed line length of 64 bytes.
803 *
804 * 7.1 About the L2 memory system
805 * The features of the L2 memory system include:
806 * - Configurable L2 cache size of 512KB, 1MB, and 2MB.
807 * - Fixed line length of 64 bytes.
808 * - 16-way set-associative cache structure.
809 * - Inclusion property with L1 data caches.
810 *
811 * +--------------------+-------+-----------+-----------+-----------+-----------+
812 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
813 * +--------------------+-------+-----------+-----------+-----------+-----------+
814 * | Snapdragon 810 | 4(+4) | 32K | 48K | 2M | [1] |
815 * | Exynos 7420 | 4(+4) | 32K | 48K | 2M | [2] |
816 * | Jetson TX1 | 4 | 32K | 48K | 2M | [3] |
817 * +--------------------+-------+-----------+-----------+-----------+-----------+
818 *
819 * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview
820 * [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2
821 * [3] https://devblogs.nvidia.com/parallelforall/jetson-tx2-delivers-twice-intelligence-edge/
822 */
823 *l1i = (struct cpuinfo_cache) {
824 .size = 48 * 1024,
825 .associativity = 3,
826 .line_size = 64
827 };
828 *l1d = (struct cpuinfo_cache) {
829 .size = 32 * 1024,
830 .associativity = 2,
831 .line_size = 64
832 };
833 *l2 = (struct cpuinfo_cache) {
834 .size = cluster_cores * 512 * 1024,
835 .associativity = 16,
836 .line_size = 64,
837 .flags = CPUINFO_CACHE_INCLUSIVE
838 };
839 break;
840 case cpuinfo_uarch_cortex_a65:
841 {
842 /*
843 * ARM Cortex‑A65 Core Technical Reference Manual
844 * A6.1. About the L1 memory system
845 * The L1 memory system enhances the performance and power efficiency in the Cortex‑A65 core.
846 * It consists of separate instruction and data caches. You can configure instruction and data caches
847 * independently during implementation to sizes of 32KB or 64KB.
848 *
849 * L1 instruction-side memory system
850 * The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are:
851 * - 64-byte instruction side cache line length.
852 * - 4-way set associative L1 instruction cache.
853 *
854 * L1 data-side memory system
855 * - 64-byte data side cache line length.
856 * - 4-way set associative L1 data cache.
857 *
858 * A7.1 About the L2 memory system
859 * The Cortex‑A65 L2 memory system is required to interface the Cortex‑A65 cores to the L3 memory system.
860 * The L2 memory subsystem consists of:
861 * - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB, or 256KB.
862 * Cache lines have a fixed length of 64 bytes.
863 *
864 * The main features of the L2 memory system are:
865 * - Strictly exclusive with L1 data cache.
866 * - Pseudo-inclusive with L1 instruction cache.
867 * - Private per-core unified L2 cache.
868 */
869 const uint32_t l1_size = 32 * 1024;
870 const uint32_t l2_size = 128 * 1024;
871 const uint32_t l3_size = 512 * 1024;
872 *l1i = (struct cpuinfo_cache) {
873 .size = l1_size,
874 .associativity = 4,
875 .line_size = 64,
876 };
877 *l1d = (struct cpuinfo_cache) {
878 .size = l1_size,
879 .associativity = 4,
880 .line_size = 64,
881 };
882 *l2 = (struct cpuinfo_cache) {
883 .size = l2_size,
884 .associativity = 4,
885 .line_size = 64,
886 .flags = CPUINFO_CACHE_INCLUSIVE
887 };
888 *l3 = (struct cpuinfo_cache) {
889 .size = l3_size,
890 /* DynamIQ */
891 .associativity = 16,
892 .line_size = 64,
893 };
894 break;
895 }
896 case cpuinfo_uarch_cortex_a72:
897 {
898 /*
899 * ARM Cortex-A72 MPCore Processor Technical Reference Manual
900 * 6.1. About the L1 memory system
901 * The L1 memory system consists of separate instruction and data caches.
902 *
903 * The L1 instruction memory system has the following features:
904 * - 48KB 3-way set-associative instruction cache.
905 * - Fixed line length of 64 bytes.
906 *
907 * The L1 data memory system has the following features:
908 * - 32KB 2-way set-associative data cache.
909 * - Fixed cache line length of 64 bytes.
910 *
911 * 7.1 About the L2 memory system
912 * The features of the L2 memory system include:
913 * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
914 * - Fixed line length of 64 bytes.
915 * - Banked pipeline structures.
916 * - Inclusion property with L1 data caches.
917 * - 16-way set-associative cache structure.
918 *
919 * +---------------------+---------+-----------+-----------+------------+-----------+
920 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
921 * +---------------------+---------+-----------+-----------+------------+-----------+
922 * | Snapdragon 650 | 2(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [1] |
923 * | Snapdragon 652 | 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [2] |
924 * | Snapdragon 653 | 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [3] |
925 * | HiSilicon Kirin 950 | 4(+4) | 32K+32K | 48K+32K | ? | |
926 * | HiSilicon Kirin 955 | 4(+4) | 32K+32K | 48K+32K | ? | |
927 * | MediaTek MT8173C | 2(+2) | 32K(+32K) | 48K(+32K) | 1M(+512K) | sysfs |
928 * | MediaTek Helio X20 | 2(+4+4) | ? | ? | ? | |
929 * | MediaTek Helio X23 | 2(+4+4) | ? | ? | ? | |
930 * | MediaTek Helio X25 | 2(+4+4) | ? | ? | ? | |
931 * | MediaTek Helio X27 | 2(+4+4) | ? | ? | ? | |
932 * | Broadcom BCM2711 | 4 | 32K | 48K | 1M | [4] |
933 * +---------------------+---------+-----------+-----------+------------+-----------+
934 *
935 * [1] http://pdadb.net/index.php?m=processor&id=578&c=qualcomm_snapdragon_618_msm8956__snapdragon_650
936 * [2] http://pdadb.net/index.php?m=processor&id=667&c=qualcomm_snapdragon_620_apq8076__snapdragon_652
937 * [3] http://pdadb.net/index.php?m=processor&id=692&c=qualcomm_snapdragon_653_msm8976sg__msm8976_pro
938 * [4] https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
939 */
940 uint32_t l2_size;
941 switch (chipset->series) {
942 case cpuinfo_arm_chipset_series_hisilicon_kirin:
943 l2_size = 2 * 1024 * 1024;
944 break;
945 default:
946 l2_size = 1024 * 1024;
947 break;
948 }
949
950 *l1i = (struct cpuinfo_cache) {
951 .size = 48 * 1024,
952 .associativity = 3,
953 .line_size = 64
954 };
955 *l1d = (struct cpuinfo_cache) {
956 .size = 32 * 1024,
957 .associativity = 2,
958 .line_size = 64
959 };
960 *l2 = (struct cpuinfo_cache) {
961 .size = l2_size,
962 .associativity = 16,
963 .line_size = 64,
964 .flags = CPUINFO_CACHE_INCLUSIVE
965 };
966 break;
967 }
968 case cpuinfo_uarch_cortex_a73:
969 {
970 /*
971 * ARM Cortex‑A73 MPCore Processor Technical Reference Manual
972 * 6.1. About the L1 memory system
973 * The L1 memory system consists of separate instruction and data caches.
974 * The size of the instruction cache is 64KB.
975 * The size of the data cache is configurable to either 32KB or 64KB.
976 *
977 * The L1 instruction memory system has the following key features:
978 * - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache.
979 * - Fixed cache line length of 64 bytes.
980 *
981 * The L1 data memory system has the following features:
982 * - ...the data cache behaves like an eight-way set associative PIPT cache (for 32KB configurations)
983 * and a 16-way set associative PIPT cache (for 64KB configurations).
984 * - Fixed cache line length of 64 bytes.
985 *
986 * 7.1 About the L2 memory system
987 * The L2 memory system consists of:
988 * - A tightly-integrated L2 cache with:
989 * - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB.
990 * - A 16-way, set-associative structure.
991 * - A fixed line length of 64 bytes.
992 *
993 * The ARM Cortex A73 - Artemis Unveiled [1]
994 * "ARM still envisions that most vendors will choose to use configurations of 1 to
995 * 2MB in consumer products. The L2 cache is inclusive of the L1 cache. "
996 *
997 * +---------------------+---------+-----------+-----------+-----------+-----------+
998 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
999 * +---------------------+---------+-----------+-----------+-----------+-----------+
1000 * | HiSilicon Kirin 960 | 4(+4) | 64K+32K | 64K+32K | ? | [2] |
1001 * | MediaTek Helio X30 | 2(+4+4) | ? | 64K+ ? | ? | |
1002 * | Snapdragon 636 | 4(+4) | 64K(+32K) | 64K(+32K) | 1M(+1M) | sysfs |
1003 * | Snapdragon 660 | 4(+4) | 64K+32K | 64K+32K | 1M(+1M) | [3] |
1004 * | Snapdragon 835 | 4(+4) | 64K+32K | 64K+32K | 2M(+1M) | sysfs |
1005 * +---------------------+---------+-----------+-----------+-----------+-----------+
1006 *
1007 * [1] http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2
1008 * [2] http://www.anandtech.com/show/11088/hisilicon-kirin-960-performance-and-power/3
1009 * [3] https://arstechnica.com/gadgets/2017/05/qualcomms-snapdragon-660-and-630-bring-more-high-end-features-to-midrange-chips/
1010 */
1011 uint32_t l1d_size = 32 * 1024;
1012 uint32_t l2_size = 512 * 1024;
1013 switch (chipset->series) {
1014 case cpuinfo_arm_chipset_series_hisilicon_kirin:
1015 l1d_size = 64 * 1024;
1016 l2_size = 2 * 1024 * 1024;
1017 break;
1018 case cpuinfo_arm_chipset_series_mediatek_mt:
1019 l1d_size = 64 * 1024;
1020 l2_size = 1 * 1024 * 1024; /* TODO: verify assumption */
1021 break;
1022 default:
1023 switch (midr) {
1024 case UINT32_C(0x51AF8001): /* Kryo 280 Gold */
1025 l1d_size = 64 * 1024;
1026 l2_size = 2 * 1024 * 1024;
1027 break;
1028 case UINT32_C(0x51AF8002): /* Kryo 260 Gold */
1029 l1d_size = 64 * 1024;
1030 l2_size = 1 * 1024 * 1024;
1031 break;
1032 }
1033 }
1034
1035 *l1i = (struct cpuinfo_cache) {
1036 .size = 64 * 1024,
1037 .associativity = 4,
1038 .line_size = 64
1039 };
1040 *l1d = (struct cpuinfo_cache) {
1041 .size = l1d_size,
1042 .associativity = (l1d_size >> 12),
1043 .line_size = 64
1044 };
1045 *l2 = (struct cpuinfo_cache) {
1046 .size = l2_size,
1047 .associativity = 16,
1048 .line_size = 64,
1049 .flags = CPUINFO_CACHE_INCLUSIVE
1050 };
1051 break;
1052 }
1053 case cpuinfo_uarch_cortex_a75:
1054 {
1055 /*
1056 * ARM Cortex-A75 Core Technical Reference Manual
1057 * A6.1. About the L1 memory system
1058 * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
1059 *
1060 * A6.1.1 L1 instruction-side memory system
1061 * The L1 instruction memory system has the following key features:
1062 * - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache.
1063 * - Fixed cache line length of 64 bytes.
1064 *
1065 * A6.1.2 L1 data-side memory system
1066 * The L1 data memory system has the following features:
1067 * - Physically Indexed, Physically Tagged (PIPT), 16-way set-associative L1 data cache.
1068 * - Fixed cache line length of 64 bytes.
1069 * - Pseudo-random cache replacement policy.
1070 *
1071 * A7.1 About the L2 memory system
1072 * The L2 memory subsystem consist of:
1073 * - An 8-way set associative L2 cache with a configurable size of 256KB or 512KB.
1074 * Cache lines have a fixed length of 64 bytes.
1075 *
1076 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1077 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
1078 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1079 * | Snapdragon 845 | 4(+4) | 64K | 64K | 256K | 2M | [1], sysfs |
1080 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1081 *
1082 * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
1083 */
1084 uint32_t l3_size = 1024 * 1024;
1085 switch (chipset->series) {
1086 case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
1087 /* Snapdragon 845: 2M L3 cache */
1088 if (chipset->model == 845) {
1089 l3_size = 2 * 1024 * 1024;
1090 }
1091 break;
1092 default:
1093 break;
1094 }
1095 *l1i = (struct cpuinfo_cache) {
1096 .size = 64 * 1024,
1097 .associativity = 4,
1098 .line_size = 64
1099 };
1100 *l1d = (struct cpuinfo_cache) {
1101 .size = 64 * 1024,
1102 .associativity = 16,
1103 .line_size = 64
1104 };
1105 *l2 = (struct cpuinfo_cache) {
1106 .size = 256 * 1024,
1107 .associativity = 8,
1108 .line_size = 64
1109 };
1110 *l3 = (struct cpuinfo_cache) {
1111 .size = l3_size,
1112 .associativity = 16,
1113 .line_size = 64
1114 };
1115 break;
1116 }
1117 case cpuinfo_uarch_cortex_a76:
1118 {
1119 /*
1120 * ARM Cortex-A76 Core Technical Reference Manual
1121 * A6.1. About the L1 memory system
1122 * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
1123 *
1124 * A6.1.1 L1 instruction-side memory system
1125 * The L1 instruction memory system has the following key features:
1126 * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1127 * Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1128 * - Fixed cache line length of 64 bytes.
1129 *
1130 * A6.1.2 L1 data-side memory system
1131 * The L1 data memory system has the following features:
1132 * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1133 * Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1134 * - Fixed cache line length of 64 bytes.
1135 * - Pseudo-LRU cache replacement policy.
1136 *
1137 * A7.1 About the L2 memory system
1138 * The L2 memory subsystem consist of:
1139 * - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB.
1140 * Cache lines have a fixed length of 64 bytes.
1141 * - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
1142 * - Dynamic biased replacement policy.
1143 * - Modified Exclusive Shared Invalid (MESI) coherency.
1144 *
1145 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1146 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
1147 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1148 * | Kirin 980 | 4(+4) | 64K | 64K | 512K | 4M | [1], [2] |
1149 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1150 *
1151 * [1] https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm
1152 * [2] https://en.wikichip.org/wiki/hisilicon/kirin/980
1153 */
1154 uint32_t l2_size = 256 * 1024;
1155 uint32_t l3_size = 1024 * 1024;
1156 switch (chipset->series) {
1157 case cpuinfo_arm_chipset_series_hisilicon_kirin:
1158 /* Kirin 980: 512K L2 cache + 4M L3 cache */
1159 if (chipset->model == 980) {
1160 l2_size = 512 * 1024;
1161 l3_size = 4 * 1024 * 1024;
1162 }
1163 break;
1164 default:
1165 break;
1166 }
1167 *l1i = (struct cpuinfo_cache) {
1168 .size = 64 * 1024,
1169 .associativity = 4,
1170 .line_size = 64,
1171 };
1172 *l1d = (struct cpuinfo_cache) {
1173 .size = 64 * 1024,
1174 .associativity = 4,
1175 .line_size = 64,
1176 };
1177 *l2 = (struct cpuinfo_cache) {
1178 .size = l2_size,
1179 .associativity = 8,
1180 .line_size = 64,
1181 .flags = CPUINFO_CACHE_INCLUSIVE,
1182 };
1183 *l3 = (struct cpuinfo_cache) {
1184 .size = l3_size,
1185 .associativity = 16,
1186 .line_size = 64,
1187 };
1188 break;
1189 }
1190 case cpuinfo_uarch_cortex_a77:
1191 {
1192 /*
1193 * ARM Cortex-A77 Core Technical Reference Manual
1194 * A6.1. About the L1 memory system
1195 * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
1196 *
1197 * A6.1.1 L1 instruction-side memory system
1198 * The L1 instruction memory system has the following key features:
1199 * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1200 * Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1201 * - Fixed cache line length of 64 bytes.
1202 *
1203 * A6.1.2 L1 data-side memory system
1204 * The L1 data memory system has the following features:
1205 * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1206 * Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1207 * - Fixed cache line length of 64 bytes.
1208 * - Pseudo-LRU cache replacement policy.
1209 *
1210 * A7.1 About the L2 memory system
1211 * The L2 memory subsystem consist of:
1212 * - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. Cache lines
1213 * have a fixed length of 64 bytes.
1214 * - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
1215 */
1216 const uint32_t l2_size = 256 * 1024;
1217 const uint32_t l3_size = 1024 * 1024;
1218 *l1i = (struct cpuinfo_cache) {
1219 .size = 64 * 1024,
1220 .associativity = 4,
1221 .line_size = 64,
1222 };
1223 *l1d = (struct cpuinfo_cache) {
1224 .size = 64 * 1024,
1225 .associativity = 4,
1226 .line_size = 64,
1227 };
1228 *l2 = (struct cpuinfo_cache) {
1229 .size = l2_size,
1230 .associativity = 8,
1231 .line_size = 64,
1232 .flags = CPUINFO_CACHE_INCLUSIVE,
1233 };
1234 *l3 = (struct cpuinfo_cache) {
1235 .size = l3_size,
1236 .associativity = 16,
1237 .line_size = 64,
1238 };
1239 break;
1240 }
1241 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
1242 case cpuinfo_uarch_scorpion:
1243 /*
1244 * - "The CPU includes 32KB instruction and data caches as
1245 * well as a complete memory-management unit (MMU) suitable
1246 * for high-level operating systems. The CPU also has
1247 * 256KB of SRAM that can be allocated in 64KB increments
1248 * to level-two (L2) cache or tightly coupled memory (TCM)." [1]
1249 * We interpret it as L2 cache being 4-way set-associative on single-core Scorpion.
1250 * - L1 Data Cache = 32 KB. 32 B/line. [2]
1251 * - L2 Cache = 256 KB. 128 B/line. [2]
1252 * - 256 KB (single-core) or 512 KB (dual-core) L2 cache [3]
1253 * - Single or dual-core configuration [3]
1254 * - For L1 cache assume the same associativity as Krait
1255 *
1256 * [1] https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf
1257 * [2] http://www.7-cpu.com/cpu/Snapdragon.html
1258 * [3] https://en.wikipedia.org/wiki/Scorpion_(CPU)
1259 */
1260 *l1i = (struct cpuinfo_cache) {
1261 .size = 32 * 1024,
1262 .associativity = 4,
1263 .line_size = 32
1264 };
1265 *l1d = (struct cpuinfo_cache) {
1266 .size = 32 * 1024,
1267 .associativity = 4,
1268 .line_size = 32
1269 };
1270 *l2 = (struct cpuinfo_cache) {
1271 .size = cluster_cores * 256 * 1024,
1272 .associativity = 4,
1273 .line_size = 128
1274 };
1275 break;
1276 case cpuinfo_uarch_krait:
1277 /*
1278 * - L0 Data cache = 4 KB. 64 B/line, direct mapped [1]
1279 * - L0 Instruction cache = 4 KB. [1]
1280 * - L1 Data cache = 16 KB. 64 B/line, 4-way [1]
1281 * - L1 Instruction cache = 16 KB, 4-way [1]
1282 * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has fast access only to 512 KB of L2 cache. [1]
1283 * - L2 = 1MB (dual core) or 2MB (quad core), 8-way set associative [2]
1284 *
1285 * [1] http://www.7-cpu.com/cpu/Krait.html
1286 * [2] http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2
1287 */
1288 *l1i = (struct cpuinfo_cache) {
1289 .size = 16 * 1024,
1290 .associativity = 4,
1291 .line_size = 64 /* assume same as L1D */
1292 };
1293 *l1d = (struct cpuinfo_cache) {
1294 .size = 16 * 1024,
1295 .associativity = 4,
1296 .line_size = 64
1297 };
1298 *l2 = (struct cpuinfo_cache) {
1299 .size = cluster_cores * 512 * 1024,
1300 .associativity = 8,
1301 .line_size = 128
1302 };
1303 break;
1304 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */
1305 case cpuinfo_uarch_kryo:
1306 /*
1307 * +-----------------+-------+-----------+-----------+-----------+-----------+
1308 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
1309 * +-----------------+-------+-----------+-----------+-----------+-----------+
1310 * | Snapdragon 820 | 2+2 | 24K | 32K | 1M+512K | [1, 2] |
1311 * | Snapdragon 821 | 2+2 | ? | ? | 1M+512K | [1] |
1312 * +-----------------+-------+-----------+-----------+-----------+-----------+
1313 *
1314 * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview/2
1315 * [2] https://www.inforcecomputing.com/public_docs/Inforce6601/Inforce_6601_Micro-SOM_FAQs_04-2016-1.pdf
1316 */
1317 *l1i = (struct cpuinfo_cache) {
1318 .size = 32 * 1024,
1319 .associativity = 4,
1320 .line_size = 64
1321 };
1322 *l1d = (struct cpuinfo_cache) {
1323 .size = 24 * 1024,
1324 .associativity = 3,
1325 .line_size = 64
1326 };
1327 if (midr_is_kryo_silver(midr)) {
1328 /* Kryo "Silver" */
1329 *l2 = (struct cpuinfo_cache) {
1330 .size = 512 * 1024,
1331 .associativity = 8,
1332 .line_size = 128
1333 };
1334 } else {
1335 /* Kryo "Gold" */
1336 *l2 = (struct cpuinfo_cache) {
1337 .size = 1024 * 1024,
1338 .associativity = 8,
1339 .line_size = 128
1340 };
1341 }
1342 break;
1343 case cpuinfo_uarch_denver:
1344 case cpuinfo_uarch_denver2:
1345 /*
1346 * The Denver chip includes a 128KB, 4-way level 1 instruction cache, a 64KB, 4-way level 2 data cache,
1347 * and a 2MB, 16-way level 2 cache, all of which can service both cores. [1]
1348 *
1349 * All the caches have 64-byte lines. [2]
1350 *
1351 * [1] http://www.pcworld.com/article/2463900/nvidia-reveals-pc-like-performance-for-denver-tegra-k1.html
1352 * [2] http://linleygroup.com/newsletters/newsletter_detail.php?num=5205&year=2014
1353 */
1354 *l1i = (struct cpuinfo_cache) {
1355 .size = 128 * 1024,
1356 .associativity = 4,
1357 .line_size = 64
1358 };
1359 *l1d = (struct cpuinfo_cache) {
1360 .size = 64 * 1024,
1361 .associativity = 4,
1362 .line_size = 64
1363 };
1364 *l2 = (struct cpuinfo_cache) {
1365 .size = 2 * 1024 * 1024,
1366 .associativity = 16,
1367 .line_size = 64
1368 };
1369 break;
1370 case cpuinfo_uarch_exynos_m1:
1371 case cpuinfo_uarch_exynos_m2:
1372 /*
1373 * - "Moving past branch prediction we can see some elements of how the cache is set up for the L1 I$,
1374 * namely 64 KB split into four sets with 128-byte line sizes for 128 cache lines per set" [1]
1375 * - "For loads and stores, a 32 KB, 8-way set associative cache with 64 byte line size is used" [1]
1376 * - "The L2 cache here is 2MB shared across all cores split into 16 sets. This memory is also split
1377 * into 4 banks and has a 22 cycle latency" [1]
1378 *
1379 * +--------------------+-------+-----------+-----------+-----------+-----------+
1380 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
1381 * +--------------------+-------+-----------+-----------+-----------+-----------+
1382 * | Exynos 8 Octa 8890 | 4(+4) | 64K | 32K | 2M | [1] |
1383 * | Exynos 8 Octa 8895 | 4(+4) | 64K | 32K | 2M | [2] |
1384 * +--------------------+-------+-----------+-----------+-----------+-----------+
1385 *
1386 * [1] http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed
1387 * [2] https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market
1388 */
1389 *l1i = (struct cpuinfo_cache) {
1390 .size = 64 * 1024,
1391 .associativity = 4,
1392 .line_size = 128
1393 };
1394 *l1d = (struct cpuinfo_cache) {
1395 .size = 32 * 1024,
1396 .associativity = 8,
1397 .line_size = 64
1398 };
1399 *l2 = (struct cpuinfo_cache) {
1400 .size = 2 * 1024 * 1024,
1401 .associativity = 16,
1402 .line_size = 64
1403 };
1404 break;
1405 case cpuinfo_uarch_exynos_m3:
1406 /*
1407 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1408 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
1409 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1410 * | Exynos 9810 | 4(+4) | 64K | ? | 512K | 4M | [1] |
1411 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1412 *
1413 * [1] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
1414 */
1415 *l1i = (struct cpuinfo_cache) {
1416 .size = 64 * 1024 /* assume same as in Exynos M1/M2 cores */,
1417 .associativity = 4 /* assume same as in Exynos M1/M2 cores */,
1418 .line_size = 128 /* assume same as in Exynos M1/M2 cores */
1419 };
1420 *l1d = (struct cpuinfo_cache) {
1421 .size = 64 * 1024,
1422 .associativity = 8 /* assume same as in Exynos M1/M2 cores */,
1423 .line_size = 64 /* assume same as in Exynos M1/M2 cores */,
1424 };
1425 *l2 = (struct cpuinfo_cache) {
1426 .size = 512 * 1024,
1427 .associativity = 16 /* assume same as in Exynos M1/M2 cores */,
1428 .line_size = 64 /* assume same as in Exynos M1/M2 cores */,
1429 };
1430 *l3 = (struct cpuinfo_cache) {
1431 .size = 4 * 1024 * 1024,
1432 .associativity = 16 /* assume DynamIQ cache */,
1433 .line_size = 64 /* assume DynamIQ cache */,
1434 };
1435 break;
1436 #if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__)
1437 case cpuinfo_uarch_thunderx:
1438 /*
1439 * "78K-Icache and 32K-D cache per core, 16 MB shared L2 cache" [1]
1440 *
1441 * [1] https://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf
1442 */
1443 *l1i = (struct cpuinfo_cache) {
1444 .size = 78 * 1024,
1445 .associativity = 4 /* assumption */,
1446 .line_size = 64 /* assumption */
1447 };
1448 *l1d = (struct cpuinfo_cache) {
1449 .size = 32 * 1024,
1450 .associativity = 4 /* assumption */,
1451 .line_size = 64 /* assumption */
1452 };
1453 *l2 = (struct cpuinfo_cache) {
1454 .size = 16 * 1024 * 1024,
1455 .associativity = 8 /* assumption */,
1456 .line_size = 64 /* assumption */
1457 };
1458 break;
1459 case cpuinfo_uarch_taishan_v110:
1460 /*
1461 * It features private 64 KiB L1 instruction and data caches as well as 512 KiB of private L2. [1]
1462 *
1463 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1464 * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
1465 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1466 * | Kunpeng 920-3226 | 32 | 64K | 64K | 512K | 32M | [2] |
1467 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1468 * | Kunpeng 920-4826 | 48 | 64K | 64K | 512K | 48M | [3] |
1469 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1470 * | Kunpeng 920-6426 | 64 | 64K | 64K | 512K | 64M | [4] |
1471 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1472 *
1473 * [1] https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110
1474 * [2] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226
1475 * [3] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826
1476 * [4] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426
1477 */
1478 *l1i = (struct cpuinfo_cache) {
1479 .size = 64 * 1024,
1480 .associativity = 4 /* assumption */,
1481 .line_size = 128 /* assumption */,
1482 };
1483 *l1d = (struct cpuinfo_cache) {
1484 .size = 64 * 1024,
1485 .associativity = 4 /* assumption */,
1486 .line_size = 128 /* assumption */,
1487 };
1488 *l2 = (struct cpuinfo_cache) {
1489 .size = 512 * 1024,
1490 .associativity = 8 /* assumption */,
1491 .line_size = 128 /* assumption */,
1492 .flags = CPUINFO_CACHE_INCLUSIVE /* assumption */,
1493 };
1494 *l3 = (struct cpuinfo_cache) {
1495 .size = cluster_cores * 1024 * 1024,
1496 .associativity = 16 /* assumption */,
1497 .line_size = 128 /* assumption */,
1498 };
1499 break;
1500 #endif
1501 case cpuinfo_uarch_cortex_a12:
1502 case cpuinfo_uarch_cortex_a32:
1503 default:
1504 cpuinfo_log_warning("target uarch not recognized; using generic cache parameters");
1505 /* Follow OpenBLAS */
1506 if (arch_version >= 8) {
1507 *l1i = (struct cpuinfo_cache) {
1508 .size = 32 * 1024,
1509 .associativity = 4,
1510 .line_size = 64
1511 };
1512 *l1d = (struct cpuinfo_cache) {
1513 .size = 32 * 1024,
1514 .associativity = 4,
1515 .line_size = 64
1516 };
1517 *l2 = (struct cpuinfo_cache) {
1518 .size = cluster_cores * 256 * 1024,
1519 .associativity = 8,
1520 .line_size = 64
1521 };
1522 } else {
1523 *l1i = (struct cpuinfo_cache) {
1524 .size = 16 * 1024,
1525 .associativity = 4,
1526 .line_size = 32
1527 };
1528 *l1d = (struct cpuinfo_cache) {
1529 .size = 16 * 1024,
1530 .associativity = 4,
1531 .line_size = 32
1532 };
1533 if (arch_version >= 7) {
1534 *l2 = (struct cpuinfo_cache) {
1535 .size = cluster_cores * 128 * 1024,
1536 .associativity = 8,
1537 .line_size = 32
1538 };
1539 }
1540 }
1541 break;
1542 }
1543 l1i->sets = l1i->size / (l1i->associativity * l1i->line_size);
1544 l1i->partitions = 1;
1545 l1d->sets = l1d->size / (l1d->associativity * l1d->line_size);
1546 l1d->partitions = 1;
1547 if (l2->size != 0) {
1548 l2->sets = l2->size / (l2->associativity * l2->line_size);
1549 l2->partitions = 1;
1550 if (l3->size != 0) {
1551 l3->sets = l3->size / (l3->associativity * l3->line_size);
1552 l3->partitions = 1;
1553 }
1554 }
1555 }
1556
cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor * processor)1557 uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* processor) {
1558 /*
1559 * There is no precise way to detect cache size on ARM/ARM64, and cache size reported by cpuinfo
1560 * may underestimate the actual cache size. Thus, we use microarchitecture-specific maximum.
1561 */
1562 switch (processor->core->uarch) {
1563 case cpuinfo_uarch_xscale:
1564 case cpuinfo_uarch_arm11:
1565 case cpuinfo_uarch_scorpion:
1566 case cpuinfo_uarch_krait:
1567 case cpuinfo_uarch_kryo:
1568 case cpuinfo_uarch_exynos_m1:
1569 case cpuinfo_uarch_exynos_m2:
1570 case cpuinfo_uarch_exynos_m3:
1571 /* cpuinfo-detected cache size always correct */
1572 return cpuinfo_compute_max_cache_size(processor);
1573 case cpuinfo_uarch_cortex_a5:
1574 /* Max observed (NXP Vybrid SoC) */
1575 return 512 * 1024;
1576 case cpuinfo_uarch_cortex_a7:
1577 /*
1578 * Cortex-A7 MPCore Technical Reference Manual:
1579 * 7.1. About the L2 Memory system
1580 * The L2 memory system consists of an:
1581 * - Optional tightly-coupled L2 cache that includes:
1582 * - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB.
1583 */
1584 return 1024 * 1024;
1585 case cpuinfo_uarch_cortex_a8:
1586 /*
1587 * Cortex-A8 Technical Reference Manual:
1588 * 8.1. About the L2 memory system
1589 * The key features of the L2 memory system include:
1590 * - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB
1591 */
1592 return 1024 * 1024;
1593 case cpuinfo_uarch_cortex_a9:
1594 /* Max observed (e.g. Exynos 4212) */
1595 return 1024 * 1024;
1596 case cpuinfo_uarch_cortex_a12:
1597 case cpuinfo_uarch_cortex_a17:
1598 /*
1599 * ARM Cortex-A17 MPCore Processor Technical Reference Manual:
1600 * 7.1. About the L2 Memory system
1601 * The key features of the L2 memory system include:
1602 * - An integrated L2 cache:
1603 * - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB.
1604 */
1605 return 8 * 1024 * 1024;
1606 case cpuinfo_uarch_cortex_a15:
1607 /*
1608 * ARM Cortex-A15 MPCore Processor Technical Reference Manual:
1609 * 7.1. About the L2 memory system
1610 * The features of the L2 memory system include:
1611 * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
1612 */
1613 return 4 * 1024 * 1024;
1614 case cpuinfo_uarch_cortex_a35:
1615 /*
1616 * ARM Cortex‑A35 Processor Technical Reference Manual:
1617 * 7.1 About the L2 memory system
1618 * L2 cache
1619 * - Further features of the L2 cache are:
1620 * - Configurable size of 128KB, 256KB, 512KB, and 1MB.
1621 */
1622 return 1024 * 1024;
1623 case cpuinfo_uarch_cortex_a53:
1624 /*
1625 * ARM Cortex-A53 MPCore Processor Technical Reference Manual:
1626 * 7.1. About the L2 memory system
1627 * The L2 memory system consists of an:
1628 * - Optional tightly-coupled L2 cache that includes:
1629 * - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB.
1630 */
1631 return 2 * 1024 * 1024;
1632 case cpuinfo_uarch_cortex_a57:
1633 /*
1634 * ARM Cortex-A57 MPCore Processor Technical Reference Manual:
1635 * 7.1 About the L2 memory system
1636 * The features of the L2 memory system include:
1637 * - Configurable L2 cache size of 512KB, 1MB, and 2MB.
1638 */
1639 return 2 * 1024 * 1024;
1640 case cpuinfo_uarch_cortex_a72:
1641 /*
1642 * ARM Cortex-A72 MPCore Processor Technical Reference Manual:
1643 * 7.1 About the L2 memory system
1644 * The features of the L2 memory system include:
1645 * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
1646 */
1647 return 4 * 1024 * 1024;
1648 case cpuinfo_uarch_cortex_a73:
1649 /*
1650 * ARM Cortex‑A73 MPCore Processor Technical Reference Manual
1651 * 7.1 About the L2 memory system
1652 * The L2 memory system consists of:
1653 * - A tightly-integrated L2 cache with:
1654 * - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB.
1655 */
1656 return 8 * 1024 * 1024;
1657 case cpuinfo_uarch_cortex_a55:
1658 case cpuinfo_uarch_cortex_a75:
1659 case cpuinfo_uarch_cortex_a76:
1660 case cpuinfo_uarch_exynos_m4:
1661 default:
1662 /*
1663 * ARM DynamIQ Shared Unit Technical Reference Manual
1664 * 1.3 Implementation options
1665 * L3_CACHE_SIZE
1666 * - 256KB
1667 * - 512KB
1668 * - 1024KB
1669 * - 1536KB
1670 * - 2048KB
1671 * - 3072KB
1672 * - 4096KB
1673 */
1674 return 4 * 1024 * 1024;
1675 }
1676 }
1677