1 /* 2 * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <mtk_dcm.h> 8 #include <mtk_dcm_utils.h> 9 dcm_armcore(bool mode)10static void dcm_armcore(bool mode) 11 { 12 dcm_mp_cpusys_top_bus_pll_div_dcm(mode); 13 dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); 14 dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); 15 } 16 dcm_mcusys(bool on)17static void dcm_mcusys(bool on) 18 { 19 dcm_mp_cpusys_top_adb_dcm(on); 20 dcm_mp_cpusys_top_apb_dcm(on); 21 dcm_mp_cpusys_top_cpubiu_dcm(on); 22 dcm_mp_cpusys_top_misc_dcm(on); 23 dcm_mp_cpusys_top_mp0_qdcm(on); 24 dcm_cpccfg_reg_emi_wfifo(on); 25 dcm_mp_cpusys_top_last_cor_idle_dcm(on); 26 } 27 dcm_stall(bool on)28static void dcm_stall(bool on) 29 { 30 dcm_mp_cpusys_top_core_stall_dcm(on); 31 dcm_mp_cpusys_top_fcm_stall_dcm(on); 32 } 33 check_dcm_state(void)34static bool check_dcm_state(void) 35 { 36 bool ret = true; 37 38 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); 39 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); 40 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); 41 42 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); 43 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); 44 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); 45 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); 46 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); 47 ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); 48 ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); 49 50 ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); 51 ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); 52 53 return ret; 54 } 55 dcm_set_default(void)56bool dcm_set_default(void) 57 { 58 dcm_armcore(true); 59 dcm_mcusys(true); 60 dcm_stall(true); 61 62 return check_dcm_state(); 63 } 64