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1/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8#include <assert_macros.S>
9#include <lib/xlat_tables/xlat_tables_v2.h>
10
11	.global	enable_mmu_direct_el1
12	.global	enable_mmu_direct_el2
13	.global	enable_mmu_direct_el3
14
15	/* Macros to read and write to system register for a given EL. */
16	.macro _msr reg_name, el, gp_reg
17	msr	\reg_name\()_el\()\el, \gp_reg
18	.endm
19
20	.macro _mrs gp_reg, reg_name, el
21	mrs	\gp_reg, \reg_name\()_el\()\el
22	.endm
23
24	.macro tlbi_invalidate_all el
25	.if \el == 1
26		TLB_INVALIDATE(vmalle1)
27	.elseif \el == 2
28		TLB_INVALIDATE(alle2)
29	.elseif \el == 3
30		TLB_INVALIDATE(alle3)
31	.else
32		.error "EL must be 1, 2 or 3"
33	.endif
34	.endm
35
36	/* void enable_mmu_direct_el<x>(unsigned int flags) */
37	.macro define_mmu_enable_func el
38	func enable_mmu_direct_\()el\el
39#if ENABLE_ASSERTIONS
40		_mrs	x1, sctlr, \el
41		tst	x1, #SCTLR_M_BIT
42		ASM_ASSERT(eq)
43#endif
44		/* Invalidate all TLB entries */
45		tlbi_invalidate_all \el
46
47		mov	x7, x0
48		adrp	x0, mmu_cfg_params
49		add	x0, x0, :lo12:mmu_cfg_params
50
51		/* MAIR */
52		ldr	x1, [x0, #(MMU_CFG_MAIR << 3)]
53		_msr	mair, \el, x1
54
55		/* TCR */
56		ldr	x2, [x0, #(MMU_CFG_TCR << 3)]
57		_msr	tcr, \el, x2
58
59		/* TTBR */
60		ldr	x3, [x0, #(MMU_CFG_TTBR0 << 3)]
61		_msr	ttbr0, \el, x3
62
63		/*
64		 * Ensure all translation table writes have drained into memory, the TLB
65		 * invalidation is complete, and translation register writes are
66		 * committed before enabling the MMU
67		 */
68		dsb	ish
69		isb
70
71		/* Set and clear required fields of SCTLR */
72		_mrs	x4, sctlr, \el
73		mov_imm	x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
74		orr	x4, x4, x5
75
76		/* Additionally, amend SCTLR fields based on flags */
77		bic	x5, x4, #SCTLR_C_BIT
78		tst	x7, #DISABLE_DCACHE
79		csel	x4, x5, x4, ne
80
81		_msr	sctlr, \el, x4
82		isb
83
84		ret
85	endfunc enable_mmu_direct_\()el\el
86	.endm
87
88	/*
89	 * Define MMU-enabling functions for EL1, EL2 and EL3:
90	 *
91	 *  enable_mmu_direct_el1
92	 *  enable_mmu_direct_el2
93	 *  enable_mmu_direct_el3
94	 */
95	define_mmu_enable_func 1
96	define_mmu_enable_func 2
97	define_mmu_enable_func 3
98