1 /*
2 * Copyright (c) 2012-2013 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_surface.h"
28 #include "etnaviv_screen.h"
29
30 #include "etnaviv_clear_blit.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_translate.h"
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "util/u_inlines.h"
36 #include "util/u_memory.h"
37
38 #include "hw/common.xml.h"
39
40 #include "drm-uapi/drm_fourcc.h"
41
42 static struct etna_resource *
etna_render_handle_incompatible(struct pipe_context * pctx,struct pipe_resource * prsc)43 etna_render_handle_incompatible(struct pipe_context *pctx, struct pipe_resource *prsc)
44 {
45 struct etna_context *ctx = etna_context(pctx);
46 struct etna_screen *screen = ctx->screen;
47 struct etna_resource *res = etna_resource(prsc);
48 bool need_multitiled = screen->specs.pixel_pipes > 1 && !screen->specs.single_buffer;
49 bool want_supertiled = screen->specs.can_supertile;
50
51 /* Resource is compatible if it is tiled and has multi tiling when required
52 * TODO: LINEAR_PE feature means render to linear is possible ?
53 */
54 if (res->layout != ETNA_LAYOUT_LINEAR &&
55 (!need_multitiled || (res->layout & ETNA_LAYOUT_BIT_MULTI)))
56 return res;
57
58 if (!res->render) {
59 struct pipe_resource templat = *prsc;
60 unsigned layout = ETNA_LAYOUT_TILED;
61 if (need_multitiled)
62 layout |= ETNA_LAYOUT_BIT_MULTI;
63 if (want_supertiled)
64 layout |= ETNA_LAYOUT_BIT_SUPER;
65
66 templat.bind &= (PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET |
67 PIPE_BIND_BLENDABLE);
68 res->render =
69 etna_resource_alloc(pctx->screen, layout,
70 DRM_FORMAT_MOD_LINEAR, &templat);
71 assert(res->render);
72 }
73 return etna_resource(res->render);
74 }
75
76 static struct pipe_surface *
etna_create_surface(struct pipe_context * pctx,struct pipe_resource * prsc,const struct pipe_surface * templat)77 etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
78 const struct pipe_surface *templat)
79 {
80 struct etna_context *ctx = etna_context(pctx);
81 struct etna_screen *screen = ctx->screen;
82 struct etna_resource *rsc = etna_render_handle_incompatible(pctx, prsc);
83 struct etna_surface *surf = CALLOC_STRUCT(etna_surface);
84
85 if (!surf)
86 return NULL;
87
88 assert(templat->u.tex.first_layer == templat->u.tex.last_layer);
89 unsigned layer = templat->u.tex.first_layer;
90 unsigned level = templat->u.tex.level;
91 assert(layer < rsc->base.array_size);
92
93 surf->base.context = pctx;
94
95 pipe_reference_init(&surf->base.reference, 1);
96 pipe_resource_reference(&surf->base.texture, &rsc->base);
97 pipe_resource_reference(&surf->prsc, prsc);
98
99 /* Allocate a TS for the resource if there isn't one yet,
100 * and it is allowed by the hw (width is a multiple of 16).
101 * Avoid doing this for GPUs with MC1.0, as kernel sources
102 * indicate the tile status module bypasses the memory
103 * offset and MMU. */
104
105 if (VIV_FEATURE(screen, chipFeatures, FAST_CLEAR) &&
106 VIV_FEATURE(screen, chipMinorFeatures0, MC20) &&
107 !rsc->ts_bo &&
108 /* needs to be RS/BLT compatible for transfer_map/unmap */
109 (rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
110 (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0 &&
111 etna_resource_hw_tileable(screen->specs.use_blt, prsc)) {
112 etna_screen_resource_alloc_ts(pctx->screen, rsc);
113 }
114
115 surf->base.texture = &rsc->base;
116 surf->base.format = templat->format;
117 surf->base.width = rsc->levels[level].width;
118 surf->base.height = rsc->levels[level].height;
119 surf->base.writable = templat->writable; /* what is this for anyway */
120 surf->base.u = templat->u;
121
122 surf->level = &rsc->levels[level]; /* Keep pointer to actual level to set
123 * clear color on underlying resource
124 * instead of surface */
125 surf->surf = rsc->levels [level]; /* Make copy of level to narrow down
126 * address to layer */
127
128 /* XXX we don't really need a copy but it's convenient */
129 surf->surf.offset += layer * surf->surf.layer_stride;
130
131 struct etna_resource_level *lev = &rsc->levels[level];
132
133 /* Setup template relocations for this surface */
134 for (unsigned pipe = 0; pipe < screen->specs.pixel_pipes; ++pipe) {
135 surf->reloc[pipe].bo = rsc->bo;
136 surf->reloc[pipe].offset = surf->surf.offset;
137 surf->reloc[pipe].flags = 0;
138 }
139
140 /* In single buffer mode, both pixel pipes must point to the same address,
141 * for multi-tiled surfaces on the other hand the second pipe is expected to
142 * point halfway the image vertically.
143 */
144 if (rsc->layout & ETNA_LAYOUT_BIT_MULTI)
145 surf->reloc[1].offset = surf->surf.offset + lev->stride * lev->padded_height / 2;
146
147 if (surf->surf.ts_size) {
148 unsigned int layer_offset = layer * surf->surf.ts_layer_stride;
149 assert(layer_offset < surf->surf.ts_size);
150
151 surf->surf.ts_offset += layer_offset;
152 surf->surf.ts_size -= layer_offset;
153 surf->surf.ts_valid = false;
154
155 surf->ts_reloc.bo = rsc->ts_bo;
156 surf->ts_reloc.offset = surf->surf.ts_offset;
157 surf->ts_reloc.flags = 0;
158
159 if (!screen->specs.use_blt) {
160 /* This (ab)uses the RS as a plain buffer memset().
161 * Currently uses a fixed row size of 64 bytes. Some benchmarking with
162 * different sizes may be in order. */
163 struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
164 etna_compile_rs_state(ctx, &surf->clear_command, &(struct rs_state) {
165 .source_format = RS_FORMAT_A8R8G8B8,
166 .dest_format = RS_FORMAT_A8R8G8B8,
167 .dest = ts_bo,
168 .dest_offset = surf->surf.ts_offset,
169 .dest_stride = 0x40,
170 .dest_tiling = ETNA_LAYOUT_TILED,
171 .dither = {0xffffffff, 0xffffffff},
172 .width = 16,
173 .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
174 .clear_value = {screen->specs.ts_clear_value},
175 .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
176 .clear_bits = 0xffff
177 });
178 }
179 } else {
180 if (!screen->specs.use_blt)
181 etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
182 }
183
184 return &surf->base;
185 }
186
187 static void
etna_surface_destroy(struct pipe_context * pctx,struct pipe_surface * psurf)188 etna_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf)
189 {
190 pipe_resource_reference(&psurf->texture, NULL);
191 pipe_resource_reference(&etna_surface(psurf)->prsc, NULL);
192 FREE(psurf);
193 }
194
195 void
etna_surface_init(struct pipe_context * pctx)196 etna_surface_init(struct pipe_context *pctx)
197 {
198 pctx->create_surface = etna_create_surface;
199 pctx->surface_destroy = etna_surface_destroy;
200 }
201