1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_texture_state.h"
28
29 #include "hw/common.xml.h"
30
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_context.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_texture.h"
36 #include "etnaviv_translate.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39
40 #include "drm-uapi/drm_fourcc.h"
41
42 struct etna_sampler_state {
43 struct pipe_sampler_state base;
44
45 /* sampler offset +4*sampler, interleave when committing state */
46 uint32_t TE_SAMPLER_CONFIG0;
47 uint32_t TE_SAMPLER_CONFIG1;
48 uint32_t TE_SAMPLER_LOD_CONFIG;
49 uint32_t TE_SAMPLER_3D_CONFIG;
50 uint32_t NTE_SAMPLER_BASELOD;
51 unsigned min_lod, max_lod, max_lod_min;
52 };
53
54 static inline struct etna_sampler_state *
etna_sampler_state(struct pipe_sampler_state * samp)55 etna_sampler_state(struct pipe_sampler_state *samp)
56 {
57 return (struct etna_sampler_state *)samp;
58 }
59
60 struct etna_sampler_view {
61 struct pipe_sampler_view base;
62
63 /* sampler offset +4*sampler, interleave when committing state */
64 uint32_t TE_SAMPLER_CONFIG0;
65 uint32_t TE_SAMPLER_CONFIG0_MASK;
66 uint32_t TE_SAMPLER_CONFIG1;
67 uint32_t TE_SAMPLER_3D_CONFIG;
68 uint32_t TE_SAMPLER_SIZE;
69 uint32_t TE_SAMPLER_LOG_SIZE;
70 uint32_t TE_SAMPLER_ASTC0;
71 uint32_t TE_SAMPLER_LINEAR_STRIDE; /* only LOD0 */
72 struct etna_reloc TE_SAMPLER_LOD_ADDR[VIVS_TE_SAMPLER_LOD_ADDR__LEN];
73 unsigned min_lod, max_lod; /* 5.5 fixp */
74
75 struct etna_sampler_ts ts;
76 };
77
78 static inline struct etna_sampler_view *
etna_sampler_view(struct pipe_sampler_view * view)79 etna_sampler_view(struct pipe_sampler_view *view)
80 {
81 return (struct etna_sampler_view *)view;
82 }
83
84 static void *
etna_create_sampler_state_state(struct pipe_context * pipe,const struct pipe_sampler_state * ss)85 etna_create_sampler_state_state(struct pipe_context *pipe,
86 const struct pipe_sampler_state *ss)
87 {
88 struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
89 struct etna_context *ctx = etna_context(pipe);
90 struct etna_screen *screen = ctx->screen;
91 const bool ansio = ss->max_anisotropy > 1;
92
93 if (!cs)
94 return NULL;
95
96 cs->base = *ss;
97
98 cs->TE_SAMPLER_CONFIG0 =
99 VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
100 VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
101 VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter)) |
102 VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter)) |
103 VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter)) |
104 VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(COND(ansio, etna_log2_fixp55(ss->max_anisotropy)));
105
106 /* ROUND_UV improves precision - but not compatible with NEAREST filter */
107 if (ss->min_img_filter != PIPE_TEX_FILTER_NEAREST &&
108 ss->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
109 cs->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ROUND_UV;
110 }
111
112 cs->TE_SAMPLER_CONFIG1 = screen->specs.seamless_cube_map ?
113 COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP) : 0;
114
115 cs->TE_SAMPLER_LOD_CONFIG =
116 COND(ss->lod_bias != 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
117 VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss->lod_bias));
118
119 cs->TE_SAMPLER_3D_CONFIG =
120 VIVS_TE_SAMPLER_3D_CONFIG_WRAP(translate_texture_wrapmode(ss->wrap_r));
121
122 if (ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
123 cs->min_lod = etna_float_to_fixp55(ss->min_lod);
124 cs->max_lod = etna_float_to_fixp55(ss->max_lod);
125 } else {
126 /* when not mipmapping, we need to set max/min lod so that always
127 * lowest LOD is selected */
128 cs->min_lod = cs->max_lod = etna_float_to_fixp55(ss->min_lod);
129 }
130
131 /* if max_lod is 0, MIN filter will never be used (GC3000)
132 * when min filter is different from mag filter, we need HW to compute LOD
133 * the workaround is to set max_lod to at least 1
134 */
135 cs->max_lod_min = (ss->min_img_filter != ss->mag_img_filter) ? 1 : 0;
136
137 cs->NTE_SAMPLER_BASELOD =
138 COND(ss->compare_mode, VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE) |
139 VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(translate_texture_compare(ss->compare_func));
140
141 return cs;
142 }
143
144 static void
etna_delete_sampler_state_state(struct pipe_context * pctx,void * ss)145 etna_delete_sampler_state_state(struct pipe_context *pctx, void *ss)
146 {
147 FREE(ss);
148 }
149
150 static struct pipe_sampler_view *
etna_create_sampler_view_state(struct pipe_context * pctx,struct pipe_resource * prsc,const struct pipe_sampler_view * so)151 etna_create_sampler_view_state(struct pipe_context *pctx, struct pipe_resource *prsc,
152 const struct pipe_sampler_view *so)
153 {
154 struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
155 struct etna_context *ctx = etna_context(pctx);
156 struct etna_screen *screen = ctx->screen;
157 const uint32_t format = translate_texture_format(so->format);
158 const bool ext = !!(format & EXT_FORMAT);
159 const bool astc = !!(format & ASTC_FORMAT);
160 const bool srgb = util_format_is_srgb(so->format);
161 const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
162 so->swizzle_g, so->swizzle_b,
163 so->swizzle_a);
164
165 if (!sv)
166 return NULL;
167
168 struct etna_resource *res = etna_texture_handle_incompatible(pctx, prsc);
169 if (!res) {
170 free(sv);
171 return NULL;
172 }
173
174 sv->base = *so;
175 pipe_reference_init(&sv->base.reference, 1);
176 sv->base.texture = NULL;
177 pipe_resource_reference(&sv->base.texture, prsc);
178 sv->base.context = pctx;
179
180 /* merged with sampler state */
181 sv->TE_SAMPLER_CONFIG0 =
182 VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(sv->base.target)) |
183 COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
184 sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
185
186 uint32_t base_height = res->base.height0;
187 uint32_t base_depth = res->base.depth0;
188 bool is_array = false;
189
190 switch (sv->base.target) {
191 case PIPE_TEXTURE_1D:
192 /* use 2D texture with T wrap to repeat for 1D texture
193 * TODO: check if old HW supports 1D texture
194 */
195 sv->TE_SAMPLER_CONFIG0_MASK = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
196 sv->TE_SAMPLER_CONFIG0 &= ~VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK;
197 sv->TE_SAMPLER_CONFIG0 |=
198 VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D) |
199 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
200 break;
201 case PIPE_TEXTURE_1D_ARRAY:
202 is_array = true;
203 base_height = res->base.array_size;
204 break;
205 case PIPE_TEXTURE_2D_ARRAY:
206 is_array = true;
207 base_depth = res->base.array_size;
208 break;
209 default:
210 break;
211 }
212
213 if (res->layout == ETNA_LAYOUT_LINEAR && !util_format_is_compressed(so->format)) {
214 sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR);
215
216 assert(res->base.last_level == 0);
217 sv->TE_SAMPLER_LINEAR_STRIDE = res->levels[0].stride;
218 } else {
219 sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED);
220 sv->TE_SAMPLER_LINEAR_STRIDE = 0;
221 }
222
223 sv->TE_SAMPLER_CONFIG1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
224 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
225 COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) |
226 VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
227 sv->TE_SAMPLER_ASTC0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
228 COND(astc && srgb, VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB) |
229 VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
230 VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
231 VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
232 sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
233 VIVS_TE_SAMPLER_SIZE_HEIGHT(base_height);
234 sv->TE_SAMPLER_LOG_SIZE =
235 VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
236 VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(base_height)) |
237 COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
238 COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
239 sv->TE_SAMPLER_3D_CONFIG =
240 VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(base_depth) |
241 VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(etna_log2_fixp55(base_depth));
242
243 /* Set up levels-of-detail */
244 for (int lod = 0; lod <= res->base.last_level; ++lod) {
245 sv->TE_SAMPLER_LOD_ADDR[lod].bo = res->bo;
246 sv->TE_SAMPLER_LOD_ADDR[lod].offset = res->levels[lod].offset;
247 sv->TE_SAMPLER_LOD_ADDR[lod].flags = ETNA_RELOC_READ;
248 }
249 sv->min_lod = sv->base.u.tex.first_level << 5;
250 sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
251
252 /* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
253 * supported when the appropriate capability is not set. */
254 if (!screen->specs.npot_tex_any_wrap &&
255 (!util_is_power_of_two_or_zero(res->base.width0) ||
256 !util_is_power_of_two_or_zero(res->base.height0))) {
257 sv->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
258 VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
259 sv->TE_SAMPLER_CONFIG0 |=
260 VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
261 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
262 }
263
264 return &sv->base;
265 }
266
267 static void
etna_sampler_view_state_destroy(struct pipe_context * pctx,struct pipe_sampler_view * view)268 etna_sampler_view_state_destroy(struct pipe_context *pctx,
269 struct pipe_sampler_view *view)
270 {
271 pipe_resource_reference(&view->texture, NULL);
272 FREE(view);
273 }
274
275 #define EMIT_STATE(state_name, src_value) \
276 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
277
278 #define EMIT_STATE_FIXP(state_name, src_value) \
279 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
280
281 #define EMIT_STATE_RELOC(state_name, src_value) \
282 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
283
284 /* Emit plain (non-descriptor) texture state */
285 static void
etna_emit_texture_state(struct etna_context * ctx)286 etna_emit_texture_state(struct etna_context *ctx)
287 {
288 struct etna_cmd_stream *stream = ctx->stream;
289 struct etna_screen *screen = ctx->screen;
290 uint32_t active_samplers = active_samplers_bits(ctx);
291 uint32_t dirty = ctx->dirty;
292 struct etna_coalesce coalesce;
293
294 etna_coalesce_start(stream, &coalesce);
295
296 if (unlikely(dirty & ETNA_DIRTY_SAMPLER_VIEWS)) {
297 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
298 if ((1 << x) & active_samplers) {
299 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
300 /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x), sv->ts.TS_SAMPLER_CONFIG);
301 }
302 }
303 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
304 if ((1 << x) & active_samplers) {
305 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
306 /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x), &sv->ts.TS_SAMPLER_STATUS_BASE);
307 }
308 }
309 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
310 if ((1 << x) & active_samplers) {
311 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
312 /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x), sv->ts.TS_SAMPLER_CLEAR_VALUE);
313 }
314 }
315 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
316 if ((1 << x) & active_samplers) {
317 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
318 /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x), sv->ts.TS_SAMPLER_CLEAR_VALUE2);
319 }
320 }
321 }
322 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
323 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
324 uint32_t val = 0; /* 0 == sampler inactive */
325
326 /* set active samplers to their configuration value (determined by both
327 * the sampler state and sampler view) */
328 if ((1 << x) & active_samplers) {
329 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
330 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
331
332 val = (ss->TE_SAMPLER_CONFIG0 & sv->TE_SAMPLER_CONFIG0_MASK) |
333 sv->TE_SAMPLER_CONFIG0;
334 }
335
336 /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
337 }
338 }
339 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
340 struct etna_sampler_state *ss;
341 struct etna_sampler_view *sv;
342
343 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
344 if ((1 << x) & active_samplers) {
345 sv = etna_sampler_view(ctx->sampler_view[x]);
346 /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->TE_SAMPLER_SIZE);
347 }
348 }
349 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
350 if ((1 << x) & active_samplers) {
351 ss = etna_sampler_state(ctx->sampler[x]);
352 sv = etna_sampler_view(ctx->sampler_view[x]);
353 uint32_t TE_SAMPLER_LOG_SIZE = sv->TE_SAMPLER_LOG_SIZE;
354
355 if (texture_use_int_filter(&sv->base, &ss->base, false))
356 TE_SAMPLER_LOG_SIZE |= VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER;
357
358 /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), TE_SAMPLER_LOG_SIZE);
359 }
360 }
361 }
362 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
363 struct etna_sampler_state *ss;
364 struct etna_sampler_view *sv;
365
366 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
367 if ((1 << x) & active_samplers) {
368 ss = etna_sampler_state(ctx->sampler[x]);
369 sv = etna_sampler_view(ctx->sampler_view[x]);
370
371 unsigned max_lod = MAX2(MIN2(ss->max_lod, sv->max_lod), ss->max_lod_min);
372
373 /* min and max lod is determined both by the sampler and the view */
374 /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x),
375 ss->TE_SAMPLER_LOD_CONFIG |
376 VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod) |
377 VIVS_TE_SAMPLER_LOD_CONFIG_MIN(MAX2(ss->min_lod, sv->min_lod)));
378 }
379 }
380 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
381 if ((1 << x) & active_samplers) {
382 ss = etna_sampler_state(ctx->sampler[x]);
383 sv = etna_sampler_view(ctx->sampler_view[x]);
384
385 /*02180*/ EMIT_STATE(TE_SAMPLER_3D_CONFIG(x), ss->TE_SAMPLER_3D_CONFIG |
386 sv->TE_SAMPLER_3D_CONFIG);
387 }
388 }
389 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
390 if ((1 << x) & active_samplers) {
391 ss = etna_sampler_state(ctx->sampler[x]);
392 sv = etna_sampler_view(ctx->sampler_view[x]);
393
394 /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x), ss->TE_SAMPLER_CONFIG1 |
395 sv->TE_SAMPLER_CONFIG1 |
396 COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
397 }
398 }
399 }
400 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
401 for (int y = 0; y < VIVS_TE_SAMPLER_LOD_ADDR__LEN; ++y) {
402 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
403 if ((1 << x) & active_samplers) {
404 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
405 /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x, y),&sv->TE_SAMPLER_LOD_ADDR[y]);
406 }
407 }
408 }
409 }
410 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
411 /* only LOD0 is valid for this register */
412 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
413 if ((1 << x) & active_samplers) {
414 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
415 /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(0, x), sv->TE_SAMPLER_LINEAR_STRIDE);
416 }
417 }
418 }
419 if (unlikely(screen->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
420 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
421 if ((1 << x) & active_samplers) {
422 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
423 /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->TE_SAMPLER_ASTC0);
424 }
425 }
426 }
427 if (unlikely(screen->specs.halti >= 1 && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
428 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
429 if ((1 << x) & active_samplers) {
430 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
431 /*10700*/ EMIT_STATE(NTE_SAMPLER_BASELOD(x), ss->NTE_SAMPLER_BASELOD);
432 }
433 }
434 }
435 etna_coalesce_end(stream, &coalesce);
436 }
437
438 #undef EMIT_STATE
439 #undef EMIT_STATE_FIXP
440 #undef EMIT_STATE_RELOC
441
442 static struct etna_sampler_ts*
etna_ts_for_sampler_view_state(struct pipe_sampler_view * pview)443 etna_ts_for_sampler_view_state(struct pipe_sampler_view *pview)
444 {
445 struct etna_sampler_view *sv = etna_sampler_view(pview);
446 return &sv->ts;
447 }
448
449 void
etna_texture_state_init(struct pipe_context * pctx)450 etna_texture_state_init(struct pipe_context *pctx)
451 {
452 struct etna_context *ctx = etna_context(pctx);
453 DBG("etnaviv: Using state-based texturing");
454 ctx->base.create_sampler_state = etna_create_sampler_state_state;
455 ctx->base.delete_sampler_state = etna_delete_sampler_state_state;
456 ctx->base.create_sampler_view = etna_create_sampler_view_state;
457 ctx->base.sampler_view_destroy = etna_sampler_view_state_destroy;
458 ctx->emit_texture_state = etna_emit_texture_state;
459 ctx->ts_for_sampler_view = etna_ts_for_sampler_view_state;
460 }
461