1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_screen.h"
28 #include "util/format/u_format.h"
29
30 #include "fd5_screen.h"
31 #include "fd5_blitter.h"
32 #include "fd5_context.h"
33 #include "fd5_format.h"
34 #include "fd5_emit.h"
35 #include "fd5_resource.h"
36
37 #include "ir3/ir3_compiler.h"
38
39 static bool
valid_sample_count(unsigned sample_count)40 valid_sample_count(unsigned sample_count)
41 {
42 switch (sample_count) {
43 case 0:
44 case 1:
45 case 2:
46 case 4:
47 return true;
48 default:
49 return false;
50 }
51 }
52
53 static bool
fd5_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)54 fd5_screen_is_format_supported(struct pipe_screen *pscreen,
55 enum pipe_format format,
56 enum pipe_texture_target target,
57 unsigned sample_count,
58 unsigned storage_sample_count,
59 unsigned usage)
60 {
61 unsigned retval = 0;
62
63 if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
64 !valid_sample_count(sample_count)) {
65 DBG("not supported: format=%s, target=%d, sample_count=%d, usage=%x",
66 util_format_name(format), target, sample_count, usage);
67 return false;
68 }
69
70 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
71 return false;
72
73 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
74 (fd5_pipe2vtx(format) != VFMT5_NONE)) {
75 retval |= PIPE_BIND_VERTEX_BUFFER;
76 }
77
78 if ((usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) &&
79 (fd5_pipe2tex(format) != TFMT5_NONE) &&
80 (target == PIPE_BUFFER ||
81 util_format_get_blocksize(format) != 12)) {
82 retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
83 }
84
85 if ((usage & (PIPE_BIND_RENDER_TARGET |
86 PIPE_BIND_DISPLAY_TARGET |
87 PIPE_BIND_SCANOUT |
88 PIPE_BIND_SHARED |
89 PIPE_BIND_COMPUTE_RESOURCE)) &&
90 (fd5_pipe2color(format) != RB5_NONE) &&
91 (fd5_pipe2tex(format) != TFMT5_NONE)) {
92 retval |= usage & (PIPE_BIND_RENDER_TARGET |
93 PIPE_BIND_DISPLAY_TARGET |
94 PIPE_BIND_SCANOUT |
95 PIPE_BIND_SHARED |
96 PIPE_BIND_COMPUTE_RESOURCE);
97 }
98
99 /* For ARB_framebuffer_no_attachments: */
100 if ((usage & PIPE_BIND_RENDER_TARGET) && (format == PIPE_FORMAT_NONE)) {
101 retval |= usage & PIPE_BIND_RENDER_TARGET;
102 }
103
104 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
105 (fd5_pipe2depth(format) != (enum a5xx_depth_format)~0) &&
106 (fd5_pipe2tex(format) != TFMT5_NONE)) {
107 retval |= PIPE_BIND_DEPTH_STENCIL;
108 }
109
110 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
111 (fd_pipe2index(format) != (enum pc_di_index_size)~0)) {
112 retval |= PIPE_BIND_INDEX_BUFFER;
113 }
114
115 if (retval != usage) {
116 DBG("not supported: format=%s, target=%d, sample_count=%d, "
117 "usage=%x, retval=%x", util_format_name(format),
118 target, sample_count, usage, retval);
119 }
120
121 return retval == usage;
122 }
123
124 void
fd5_screen_init(struct pipe_screen * pscreen)125 fd5_screen_init(struct pipe_screen *pscreen)
126 {
127 struct fd_screen *screen = fd_screen(pscreen);
128 screen->max_rts = A5XX_MAX_RENDER_TARGETS;
129 screen->compiler = ir3_compiler_create(screen->dev, screen->gpu_id);
130 pscreen->context_create = fd5_context_create;
131 pscreen->is_format_supported = fd5_screen_is_format_supported;
132
133 screen->setup_slices = fd5_setup_slices;
134 if (fd_mesa_debug & FD_DBG_TTILE)
135 screen->tile_mode = fd5_tile_mode;
136
137 fd5_emit_init_screen(pscreen);
138 ir3_screen_init(pscreen);
139 }
140