| /external/llvm-project/llvm/test/MC/AArch64/SVE/ |
| D | fneg.s | 10 fneg z31.h, p7/m, z31.h label
16 fneg z31.s, p7/m, z31.s label
22 fneg z31.d, p7/m, z31.d label
38 fneg z4.d, p7/m, z31.d label
50 fneg z4.d, p7/m, z31.d label
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| D | fneg-diagnostics.s | 6 fneg z31.h, p8/m, z31.h label
15 fneg z31.b, p7/m, z31.b label
20 fneg z31.h, p7/m, z31.s label
|
| /external/compiler-rt/lib/builtins/ |
| D | negsf2.c | 17 ARM_EABI_FNALIAS(fneg, negsf2) in ARM_EABI_FNALIAS() argument
|
| /external/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 1856 fneg d4, d5 define
|
| D | arm64-fp-encoding.s | 108 fneg d1, d2 define
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 1839 fneg d4, d5 define
|
| D | arm64-fp-encoding.s | 108 fneg d1, d2 define
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 465 __ fneg(z17.VnH(), p1.Merging(), z17.VnH()); in TEST() local
948 __ fneg(z6.VnS(), p2.Merging(), z28.VnS()); in TEST() local
1767 __ fneg(z5.VnH(), p0.Merging(), z1.VnH()); in TEST() local
|
| D | test-trace-aarch64.cc | 547 __ fneg(d15, d0); in GenerateTestSequenceFP() local
548 __ fneg(s14, s15); in GenerateTestSequenceFP() local
2687 __ fneg(v1.V2D(), v25.V2D()); in GenerateTestSequenceNEONFP() local
2688 __ fneg(v14.V2S(), v31.V2S()); in GenerateTestSequenceNEONFP() local
2689 __ fneg(v5.V4S(), v4.V4S()); in GenerateTestSequenceNEONFP() local
|
| D | test-assembler-fp-aarch64.cc | 1878 TEST(fneg) { in TEST() argument
|
| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| D | A55-basic-instructions.s | 601 fneg s4, s5 label
614 fneg d4, d5 define
|
| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 5245 LogicVRegister Simulator::fneg(VectorFormat vform, in fneg() function in vixl::aarch64::Simulator
5258 LogicVRegister Simulator::fneg(VectorFormat vform, in fneg() function in vixl::aarch64::Simulator
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| D | assembler-sve-aarch64.cc | 3412 void Assembler::fneg(const ZRegister& zd, in fneg() function in vixl::aarch64::Assembler
|