1 #include <stdlib.h>
2 #include <sys/ioctl.h>
3 #include <stdio.h>
4 #include <string.h>
5 #include <assert.h>
6 #include <fcntl.h>
7 #include <inttypes.h>
8 #include <errno.h>
9 #include <sys/stat.h>
10 #include <sys/time.h>
11 #include "drm.h"
12 #include "i915_drm.h"
13 #include "drmtest.h"
14 #include "intel_bufmgr.h"
15 #include "intel_batchbuffer.h"
16 #include "intel_io.h"
17
18 #include "i915_reg.h"
19 #include "i915_3d.h"
20 #include "rendercopy.h"
21
gen3_render_copyfunc(struct intel_batchbuffer * batch,drm_intel_context * context,const struct igt_buf * src,unsigned src_x,unsigned src_y,unsigned width,unsigned height,const struct igt_buf * dst,unsigned dst_x,unsigned dst_y)22 void gen3_render_copyfunc(struct intel_batchbuffer *batch,
23 drm_intel_context *context,
24 const struct igt_buf *src, unsigned src_x, unsigned src_y,
25 unsigned width, unsigned height,
26 const struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
27 {
28 igt_assert(src->bpp == dst->bpp);
29
30 /* invariant state */
31 {
32 OUT_BATCH(_3DSTATE_AA_CMD |
33 AA_LINE_ECAAR_WIDTH_ENABLE |
34 AA_LINE_ECAAR_WIDTH_1_0 |
35 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
36 OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
37 IAB_MODIFY_ENABLE |
38 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
39 IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
40 IAB_SRC_FACTOR_SHIFT) |
41 IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
42 IAB_DST_FACTOR_SHIFT));
43 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
44 OUT_BATCH(0);
45 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
46 OUT_BATCH(0);
47 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
48 OUT_BATCH(0);
49 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
50 CSB_TCB(0, 0) |
51 CSB_TCB(1, 1) |
52 CSB_TCB(2, 2) |
53 CSB_TCB(3, 3) |
54 CSB_TCB(4, 4) |
55 CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
56 OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
57 ENABLE_POINT_RASTER_RULE |
58 OGL_POINT_RASTER_RULE |
59 ENABLE_LINE_STRIP_PROVOKE_VRTX |
60 ENABLE_TRI_FAN_PROVOKE_VRTX |
61 LINE_STRIP_PROVOKE_VRTX(1) |
62 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
63 OUT_BATCH(_3DSTATE_MODES_4_CMD |
64 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
65 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
66 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
67 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
68 OUT_BATCH(0x00000000); /* Disable texture coordinate wrap-shortest */
69 OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) |
70 S4_LINE_WIDTH_ONE |
71 S4_CULLMODE_NONE |
72 S4_VFMT_XY);
73 OUT_BATCH(0x00000000); /* Stencil. */
74 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
75 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
76 OUT_BATCH(0);
77 OUT_BATCH(0);
78 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
79 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
80 OUT_BATCH(0);
81 OUT_BATCH(_3DSTATE_STIPPLE);
82 OUT_BATCH(0x00000000);
83 OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
84 }
85
86 /* samler state */
87 {
88 #define TEX_COUNT 1
89 uint32_t format_bits, tiling_bits = 0;
90
91 igt_assert_lte(src->stride, 8192);
92 igt_assert_lte(igt_buf_width(src), 2048);
93 igt_assert_lte(igt_buf_height(src), 2048);
94
95 if (src->tiling != I915_TILING_NONE)
96 tiling_bits = MS3_TILED_SURFACE;
97 if (src->tiling == I915_TILING_Y)
98 tiling_bits |= MS3_TILE_WALK;
99
100 switch (src->bpp) {
101 case 8: format_bits = MAPSURF_8BIT | MT_8BIT_L8; break;
102 case 16: format_bits = MAPSURF_16BIT | MT_16BIT_RGB565; break;
103 case 32: format_bits = MAPSURF_32BIT | MT_32BIT_ARGB8888; break;
104 default: igt_assert(0);
105 }
106
107 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
108 OUT_BATCH((1 << TEX_COUNT) - 1);
109 OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
110 OUT_BATCH(format_bits | tiling_bits |
111 (igt_buf_height(src) - 1) << MS3_HEIGHT_SHIFT |
112 (igt_buf_width(src) - 1) << MS3_WIDTH_SHIFT);
113 OUT_BATCH((src->stride/4-1) << MS4_PITCH_SHIFT);
114
115 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
116 OUT_BATCH((1 << TEX_COUNT) - 1);
117 OUT_BATCH(MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
118 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
119 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
120 OUT_BATCH(TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
121 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
122 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
123 OUT_BATCH(0x00000000);
124 }
125
126 /* render target state */
127 {
128 uint32_t tiling_bits = 0;
129 uint32_t format_bits;
130
131 igt_assert_lte(dst->stride, 8192);
132 igt_assert_lte(igt_buf_width(dst), 2048);
133 igt_assert_lte(igt_buf_height(dst), 2048);
134
135 switch (dst->bpp) {
136 case 8: format_bits = COLR_BUF_8BIT; break;
137 case 16: format_bits = COLR_BUF_RGB565; break;
138 case 32: format_bits = COLR_BUF_ARGB8888; break;
139 default: igt_assert(0);
140 }
141
142 if (dst->tiling != I915_TILING_NONE)
143 tiling_bits = BUF_3D_TILED_SURFACE;
144 if (dst->tiling == I915_TILING_Y)
145 tiling_bits |= BUF_3D_TILE_WALK_Y;
146
147 OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
148 OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
149 BUF_3D_PITCH(dst->stride));
150 OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
151
152 OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
153 OUT_BATCH(format_bits |
154 DSTORG_HORT_BIAS(0x8) |
155 DSTORG_VERT_BIAS(0x8));
156
157 /* draw rect is unconditional */
158 OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
159 OUT_BATCH(0x00000000);
160 OUT_BATCH(0x00000000); /* ymin, xmin */
161 OUT_BATCH(DRAW_YMAX(igt_buf_height(dst) - 1) |
162 DRAW_XMAX(igt_buf_width(dst) - 1));
163 /* yorig, xorig (relate to color buffer?) */
164 OUT_BATCH(0x00000000);
165 }
166
167 /* texfmt */
168 {
169 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
170 I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
171 OUT_BATCH((4 << S1_VERTEX_WIDTH_SHIFT) |
172 (4 << S1_VERTEX_PITCH_SHIFT));
173 OUT_BATCH(~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) | S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
174 OUT_BATCH(S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
175 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
176 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
177 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
178 }
179
180 /* frage shader */
181 {
182 OUT_BATCH(_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
183 /* decl FS_T0 */
184 OUT_BATCH(D0_DCL |
185 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
186 REG_NR(FS_T0) << D0_NR_SHIFT |
187 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
188 OUT_BATCH(0);
189 OUT_BATCH(0);
190 /* decl FS_S0 */
191 OUT_BATCH(D0_DCL |
192 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
193 (REG_NR(FS_S0) << D0_NR_SHIFT) |
194 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
195 OUT_BATCH(0);
196 OUT_BATCH(0);
197 /* texld(FS_OC, FS_S0, FS_T0 */
198 OUT_BATCH(T0_TEXLD |
199 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
200 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
201 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
202 OUT_BATCH((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
203 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
204 OUT_BATCH(0);
205 }
206
207 OUT_BATCH(PRIM3D_RECTLIST | (3*4 - 1));
208 emit_vertex(batch, dst_x + width);
209 emit_vertex(batch, dst_y + height);
210 emit_vertex(batch, src_x + width);
211 emit_vertex(batch, src_y + height);
212
213 emit_vertex(batch, dst_x);
214 emit_vertex(batch, dst_y + height);
215 emit_vertex(batch, src_x);
216 emit_vertex(batch, src_y + height);
217
218 emit_vertex(batch, dst_x);
219 emit_vertex(batch, dst_y);
220 emit_vertex(batch, src_x);
221 emit_vertex(batch, src_y);
222
223 intel_batchbuffer_flush(batch);
224 }
225