1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef GICV3_PRIVATE_H
8 #define GICV3_PRIVATE_H
9
10 #include <assert.h>
11 #include <stdint.h>
12
13 #include <drivers/arm/gic_common.h>
14 #include <drivers/arm/gicv3.h>
15 #include <lib/mmio.h>
16
17 #include "../common/gic_common_private.h"
18
19 /*******************************************************************************
20 * GICv3 private macro definitions
21 ******************************************************************************/
22
23 /* Constants to indicate the status of the RWP bit */
24 #define RWP_TRUE U(1)
25 #define RWP_FALSE U(0)
26
27 /* Calculate GIC register bit number corresponding to its interrupt ID */
28 #define BIT_NUM(REG, id) \
29 ((id) & ((1U << REG##R_SHIFT) - 1U))
30
31 /*
32 * Calculate 8, 32 and 64-bit GICD register offset
33 * corresponding to its interrupt ID
34 */
35 #if GIC_EXT_INTID
36 /* GICv3.1 */
37 #define GICD_OFFSET_8(REG, id) \
38 (((id) <= MAX_SPI_ID) ? \
39 GICD_##REG##R + (uintptr_t)(id) : \
40 GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID)
41
42 #define GICD_OFFSET(REG, id) \
43 (((id) <= MAX_SPI_ID) ? \
44 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
45 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
46 REG##R_SHIFT) << 2))
47
48 #define GICD_OFFSET_64(REG, id) \
49 (((id) <= MAX_SPI_ID) ? \
50 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
51 GICD_##REG##RE + (((uintptr_t)(id) - MIN_ESPI_ID) << 3))
52
53 #else /* GICv3 */
54 #define GICD_OFFSET_8(REG, id) \
55 (GICD_##REG##R + (uintptr_t)(id))
56
57 #define GICD_OFFSET(REG, id) \
58 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
59
60 #define GICD_OFFSET_64(REG, id) \
61 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3))
62 #endif /* GIC_EXT_INTID */
63
64 /*
65 * Read/Write 8, 32 and 64-bit GIC Distributor register
66 * corresponding to its interrupt ID
67 */
68 #define GICD_READ(REG, base, id) \
69 mmio_read_32((base) + GICD_OFFSET(REG, (id)))
70
71 #define GICD_READ_64(REG, base, id) \
72 mmio_read_64((base) + GICD_OFFSET_64(REG, (id)))
73
74 #define GICD_WRITE_8(REG, base, id, val) \
75 mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val))
76
77 #define GICD_WRITE(REG, base, id, val) \
78 mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val))
79
80 #define GICD_WRITE_64(REG, base, id, val) \
81 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
82
83 /*
84 * Bit operations on GIC Distributor register corresponding
85 * to its interrupt ID
86 */
87 /* Get bit in GIC Distributor register */
88 #define GICD_GET_BIT(REG, base, id) \
89 ((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \
90 BIT_NUM(REG, (id))) & 1U)
91
92 /* Set bit in GIC Distributor register */
93 #define GICD_SET_BIT(REG, base, id) \
94 mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \
95 ((uint32_t)1 << BIT_NUM(REG, (id))))
96
97 /* Clear bit in GIC Distributor register */
98 #define GICD_CLR_BIT(REG, base, id) \
99 mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \
100 ((uint32_t)1 << BIT_NUM(REG, (id))))
101
102 /* Write bit in GIC Distributor register */
103 #define GICD_WRITE_BIT(REG, base, id) \
104 mmio_write_32((base) + GICD_OFFSET(REG, (id)), \
105 ((uint32_t)1 << BIT_NUM(REG, (id))))
106
107 /*
108 * Calculate 8 and 32-bit GICR register offset
109 * corresponding to its interrupt ID
110 */
111 #if GIC_EXT_INTID
112 /* GICv3.1 */
113 #define GICR_OFFSET_8(REG, id) \
114 (((id) <= MAX_PPI_ID) ? \
115 GICR_##REG##R + (uintptr_t)(id) : \
116 GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))
117
118 #define GICR_OFFSET(REG, id) \
119 (((id) <= MAX_PPI_ID) ? \
120 GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
121 GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\
122 >> REG##R_SHIFT) << 2))
123 #else /* GICv3 */
124 #define GICR_OFFSET_8(REG, id) \
125 (GICR_##REG##R + (uintptr_t)(id))
126
127 #define GICR_OFFSET(REG, id) \
128 (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
129 #endif /* GIC_EXT_INTID */
130
131 /* Read/Write GIC Redistributor register corresponding to its interrupt ID */
132 #define GICR_READ(REG, base, id) \
133 mmio_read_32((base) + GICR_OFFSET(REG, (id)))
134
135 #define GICR_WRITE_8(REG, base, id, val) \
136 mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val))
137
138 #define GICR_WRITE(REG, base, id, val) \
139 mmio_write_32((base) + GICR_OFFSET(REG, (id)), (val))
140
141 /*
142 * Bit operations on GIC Redistributor register
143 * corresponding to its interrupt ID
144 */
145 /* Get bit in GIC Redistributor register */
146 #define GICR_GET_BIT(REG, base, id) \
147 ((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \
148 BIT_NUM(REG, (id))) & 1U)
149
150 /* Write bit in GIC Redistributor register */
151 #define GICR_WRITE_BIT(REG, base, id) \
152 mmio_write_32((base) + GICR_OFFSET(REG, (id)), \
153 ((uint32_t)1 << BIT_NUM(REG, (id))))
154
155 /* Set bit in GIC Redistributor register */
156 #define GICR_SET_BIT(REG, base, id) \
157 mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \
158 ((uint32_t)1 << BIT_NUM(REG, (id))))
159
160 /* Clear bit in GIC Redistributor register */
161 #define GICR_CLR_BIT(REG, base, id) \
162 mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \
163 ((uint32_t)1 << BIT_NUM(REG, (id))))
164
165 /*
166 * Macro to convert an mpidr to a value suitable for programming into a
167 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
168 * to GICv3.
169 */
gicd_irouter_val_from_mpidr(u_register_t mpidr,unsigned int irm)170 static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr,
171 unsigned int irm)
172 {
173 return (mpidr & ~(U(0xff) << 24)) |
174 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT);
175 }
176
177 /*
178 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
179 * are zeroes.
180 */
181 #ifdef __aarch64__
mpidr_from_gicr_typer(uint64_t typer_val)182 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
183 {
184 return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) |
185 ((typer_val >> 32) & U(0xffffff));
186 }
187 #else
mpidr_from_gicr_typer(uint64_t typer_val)188 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
189 {
190 return (((typer_val) >> 32) & U(0xffffff));
191 }
192 #endif
193
194 /*******************************************************************************
195 * GICv3 private global variables declarations
196 ******************************************************************************/
197 extern const gicv3_driver_data_t *gicv3_driver_data;
198
199 /*******************************************************************************
200 * Private GICv3 function prototypes for accessing entire registers.
201 * Note: The raw register values correspond to multiple interrupt IDs and
202 * the number of interrupt IDs involved depends on the register accessed.
203 ******************************************************************************/
204 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
205 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
206 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
207 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
208
209 /*******************************************************************************
210 * Private GICv3 function prototypes for accessing the GIC registers
211 * corresponding to a single interrupt ID. These functions use bitwise
212 * operations or appropriate register accesses to modify or return
213 * the bit-field corresponding the single interrupt ID.
214 ******************************************************************************/
215 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id);
216 unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id);
217 unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id);
218 unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id);
219 void gicd_set_igrpmodr(uintptr_t base, unsigned int id);
220 void gicr_set_igrpmodr(uintptr_t base, unsigned int id);
221 void gicr_set_isenabler(uintptr_t base, unsigned int id);
222 void gicr_set_icenabler(uintptr_t base, unsigned int id);
223 void gicr_set_ispendr(uintptr_t base, unsigned int id);
224 void gicr_set_icpendr(uintptr_t base, unsigned int id);
225 void gicr_set_igroupr(uintptr_t base, unsigned int id);
226 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id);
227 void gicr_clr_igrpmodr(uintptr_t base, unsigned int id);
228 void gicr_clr_igroupr(uintptr_t base, unsigned int id);
229 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
230 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg);
231
232 /*******************************************************************************
233 * Private GICv3 helper function prototypes
234 ******************************************************************************/
235 void gicv3_spis_config_defaults(uintptr_t gicd_base);
236 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
237 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
238 const interrupt_prop_t *interrupt_props,
239 unsigned int interrupt_props_num);
240 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
241 const interrupt_prop_t *interrupt_props,
242 unsigned int interrupt_props_num);
243 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
244 unsigned int rdistif_num,
245 uintptr_t gicr_base,
246 mpidr_hash_fn mpidr_to_core_pos);
247 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
248 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
249
250 /*******************************************************************************
251 * GIC Distributor interface accessors
252 ******************************************************************************/
253 /*
254 * Wait for updates to:
255 * GICD_CTLR[2:0] - the Group Enables
256 * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit
257 * GICD_ICENABLER<n> - the clearing of enable state for SPIs
258 */
gicd_wait_for_pending_write(uintptr_t gicd_base)259 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
260 {
261 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) {
262 }
263 }
264
gicd_read_pidr2(uintptr_t base)265 static inline uint32_t gicd_read_pidr2(uintptr_t base)
266 {
267 return mmio_read_32(base + GICD_PIDR2_GICV3);
268 }
269
gicd_read_irouter(uintptr_t base,unsigned int id)270 static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id)
271 {
272 assert(id >= MIN_SPI_ID);
273 return GICD_READ_64(IROUTE, base, id);
274 }
275
gicd_write_irouter(uintptr_t base,unsigned int id,uint64_t affinity)276 static inline void gicd_write_irouter(uintptr_t base,
277 unsigned int id,
278 uint64_t affinity)
279 {
280 assert(id >= MIN_SPI_ID);
281 GICD_WRITE_64(IROUTE, base, id, affinity);
282 }
283
gicd_clr_ctlr(uintptr_t base,unsigned int bitmap,unsigned int rwp)284 static inline void gicd_clr_ctlr(uintptr_t base,
285 unsigned int bitmap,
286 unsigned int rwp)
287 {
288 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
289 if (rwp != 0U) {
290 gicd_wait_for_pending_write(base);
291 }
292 }
293
gicd_set_ctlr(uintptr_t base,unsigned int bitmap,unsigned int rwp)294 static inline void gicd_set_ctlr(uintptr_t base,
295 unsigned int bitmap,
296 unsigned int rwp)
297 {
298 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
299 if (rwp != 0U) {
300 gicd_wait_for_pending_write(base);
301 }
302 }
303
304 /*******************************************************************************
305 * GIC Redistributor interface accessors
306 ******************************************************************************/
gicr_read_ctlr(uintptr_t base)307 static inline uint32_t gicr_read_ctlr(uintptr_t base)
308 {
309 return mmio_read_32(base + GICR_CTLR);
310 }
311
gicr_write_ctlr(uintptr_t base,uint32_t val)312 static inline void gicr_write_ctlr(uintptr_t base, uint32_t val)
313 {
314 mmio_write_32(base + GICR_CTLR, val);
315 }
316
gicr_read_typer(uintptr_t base)317 static inline uint64_t gicr_read_typer(uintptr_t base)
318 {
319 return mmio_read_64(base + GICR_TYPER);
320 }
321
gicr_read_waker(uintptr_t base)322 static inline uint32_t gicr_read_waker(uintptr_t base)
323 {
324 return mmio_read_32(base + GICR_WAKER);
325 }
326
gicr_write_waker(uintptr_t base,uint32_t val)327 static inline void gicr_write_waker(uintptr_t base, uint32_t val)
328 {
329 mmio_write_32(base + GICR_WAKER, val);
330 }
331
332 /*
333 * Wait for updates to:
334 * GICR_ICENABLER0
335 * GICR_CTLR.DPG1S
336 * GICR_CTLR.DPG1NS
337 * GICR_CTLR.DPG0
338 * GICR_CTLR, which clears EnableLPIs from 1 to 0
339 */
gicr_wait_for_pending_write(uintptr_t gicr_base)340 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
341 {
342 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) {
343 }
344 }
345
gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)346 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
347 {
348 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) {
349 }
350 }
351
352 /* Private implementation of Distributor power control hooks */
353 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num);
354 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num);
355
356 /*******************************************************************************
357 * GIC Redistributor functions for accessing entire registers.
358 * Note: The raw register values correspond to multiple interrupt IDs and
359 * the number of interrupt IDs involved depends on the register accessed.
360 ******************************************************************************/
361
362 /*
363 * Accessors to read/write GIC Redistributor ICENABLER0 register
364 */
gicr_read_icenabler0(uintptr_t base)365 static inline unsigned int gicr_read_icenabler0(uintptr_t base)
366 {
367 return mmio_read_32(base + GICR_ICENABLER0);
368 }
369
gicr_write_icenabler0(uintptr_t base,unsigned int val)370 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val)
371 {
372 mmio_write_32(base + GICR_ICENABLER0, val);
373 }
374
375 /*
376 * Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE
377 * register corresponding to its number
378 */
gicr_read_icenabler(uintptr_t base,unsigned int reg_num)379 static inline unsigned int gicr_read_icenabler(uintptr_t base,
380 unsigned int reg_num)
381 {
382 return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2));
383 }
384
gicr_write_icenabler(uintptr_t base,unsigned int reg_num,unsigned int val)385 static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num,
386 unsigned int val)
387 {
388 mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val);
389 }
390
391 /*
392 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 registers
393 */
gicr_read_icfgr0(uintptr_t base)394 static inline unsigned int gicr_read_icfgr0(uintptr_t base)
395 {
396 return mmio_read_32(base + GICR_ICFGR0);
397 }
398
gicr_read_icfgr1(uintptr_t base)399 static inline unsigned int gicr_read_icfgr1(uintptr_t base)
400 {
401 return mmio_read_32(base + GICR_ICFGR1);
402 }
403
gicr_write_icfgr0(uintptr_t base,unsigned int val)404 static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val)
405 {
406 mmio_write_32(base + GICR_ICFGR0, val);
407 }
408
gicr_write_icfgr1(uintptr_t base,unsigned int val)409 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
410 {
411 mmio_write_32(base + GICR_ICFGR1, val);
412 }
413
414 /*
415 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE
416 * register corresponding to its number
417 */
gicr_read_icfgr(uintptr_t base,unsigned int reg_num)418 static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num)
419 {
420 return mmio_read_32(base + GICR_ICFGR + (reg_num << 2));
421 }
422
gicr_write_icfgr(uintptr_t base,unsigned int reg_num,unsigned int val)423 static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num,
424 unsigned int val)
425 {
426 mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val);
427 }
428
429 /*
430 * Accessor to write GIC Redistributor ICPENDR0 register
431 */
gicr_write_icpendr0(uintptr_t base,unsigned int val)432 static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val)
433 {
434 mmio_write_32(base + GICR_ICPENDR0, val);
435 }
436
437 /*
438 * Accessor to write GIC Redistributor ICPENDR0 and ICPENDRE
439 * register corresponding to its number
440 */
gicr_write_icpendr(uintptr_t base,unsigned int reg_num,unsigned int val)441 static inline void gicr_write_icpendr(uintptr_t base, unsigned int reg_num,
442 unsigned int val)
443 {
444 mmio_write_32(base + GICR_ICPENDR + (reg_num << 2), val);
445 }
446
447 /*
448 * Accessors to read/write GIC Redistributor IGROUPR0 register
449 */
gicr_read_igroupr0(uintptr_t base)450 static inline unsigned int gicr_read_igroupr0(uintptr_t base)
451 {
452 return mmio_read_32(base + GICR_IGROUPR0);
453 }
454
gicr_write_igroupr0(uintptr_t base,unsigned int val)455 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val)
456 {
457 mmio_write_32(base + GICR_IGROUPR0, val);
458 }
459
460 /*
461 * Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE
462 * register corresponding to its number
463 */
gicr_read_igroupr(uintptr_t base,unsigned int reg_num)464 static inline unsigned int gicr_read_igroupr(uintptr_t base,
465 unsigned int reg_num)
466 {
467 return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2));
468 }
469
gicr_write_igroupr(uintptr_t base,unsigned int reg_num,unsigned int val)470 static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num,
471 unsigned int val)
472 {
473 mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val);
474 }
475
476 /*
477 * Accessors to read/write GIC Redistributor IGRPMODR0 register
478 */
gicr_read_igrpmodr0(uintptr_t base)479 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base)
480 {
481 return mmio_read_32(base + GICR_IGRPMODR0);
482 }
483
gicr_write_igrpmodr0(uintptr_t base,unsigned int val)484 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val)
485 {
486 mmio_write_32(base + GICR_IGRPMODR0, val);
487 }
488
489 /*
490 * Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE
491 * register corresponding to its number
492 */
gicr_read_igrpmodr(uintptr_t base,unsigned int reg_num)493 static inline unsigned int gicr_read_igrpmodr(uintptr_t base,
494 unsigned int reg_num)
495 {
496 return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2));
497 }
498
gicr_write_igrpmodr(uintptr_t base,unsigned int reg_num,unsigned int val)499 static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num,
500 unsigned int val)
501 {
502 mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val);
503 }
504
505 /*
506 * Accessors to read/write the GIC Redistributor IPRIORITYR(E) register
507 * corresponding to its number, 4 interrupts IDs at a time.
508 */
gicr_ipriorityr_read(uintptr_t base,unsigned int reg_num)509 static inline unsigned int gicr_ipriorityr_read(uintptr_t base,
510 unsigned int reg_num)
511 {
512 return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2));
513 }
514
gicr_ipriorityr_write(uintptr_t base,unsigned int reg_num,unsigned int val)515 static inline void gicr_ipriorityr_write(uintptr_t base, unsigned int reg_num,
516 unsigned int val)
517 {
518 mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val);
519 }
520
521 /*
522 * Accessors to read/write GIC Redistributor ISACTIVER0 register
523 */
gicr_read_isactiver0(uintptr_t base)524 static inline unsigned int gicr_read_isactiver0(uintptr_t base)
525 {
526 return mmio_read_32(base + GICR_ISACTIVER0);
527 }
528
gicr_write_isactiver0(uintptr_t base,unsigned int val)529 static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val)
530 {
531 mmio_write_32(base + GICR_ISACTIVER0, val);
532 }
533
534 /*
535 * Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE
536 * register corresponding to its number
537 */
gicr_read_isactiver(uintptr_t base,unsigned int reg_num)538 static inline unsigned int gicr_read_isactiver(uintptr_t base,
539 unsigned int reg_num)
540 {
541 return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2));
542 }
543
gicr_write_isactiver(uintptr_t base,unsigned int reg_num,unsigned int val)544 static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num,
545 unsigned int val)
546 {
547 mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val);
548 }
549
550 /*
551 * Accessors to read/write GIC Redistributor ISENABLER0 register
552 */
gicr_read_isenabler0(uintptr_t base)553 static inline unsigned int gicr_read_isenabler0(uintptr_t base)
554 {
555 return mmio_read_32(base + GICR_ISENABLER0);
556 }
557
gicr_write_isenabler0(uintptr_t base,unsigned int val)558 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val)
559 {
560 mmio_write_32(base + GICR_ISENABLER0, val);
561 }
562
563 /*
564 * Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE
565 * register corresponding to its number
566 */
gicr_read_isenabler(uintptr_t base,unsigned int reg_num)567 static inline unsigned int gicr_read_isenabler(uintptr_t base,
568 unsigned int reg_num)
569 {
570 return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2));
571 }
572
gicr_write_isenabler(uintptr_t base,unsigned int reg_num,unsigned int val)573 static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num,
574 unsigned int val)
575 {
576 mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val);
577 }
578
579 /*
580 * Accessors to read/write GIC Redistributor ISPENDR0 register
581 */
gicr_read_ispendr0(uintptr_t base)582 static inline unsigned int gicr_read_ispendr0(uintptr_t base)
583 {
584 return mmio_read_32(base + GICR_ISPENDR0);
585 }
586
gicr_write_ispendr0(uintptr_t base,unsigned int val)587 static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val)
588 {
589 mmio_write_32(base + GICR_ISPENDR0, val);
590 }
591
592 /*
593 * Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE
594 * register corresponding to its number
595 */
gicr_read_ispendr(uintptr_t base,unsigned int reg_num)596 static inline unsigned int gicr_read_ispendr(uintptr_t base,
597 unsigned int reg_num)
598 {
599 return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2));
600 }
601
gicr_write_ispendr(uintptr_t base,unsigned int reg_num,unsigned int val)602 static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num,
603 unsigned int val)
604 {
605 mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val);
606 }
607
608 /*
609 * Accessors to read/write GIC Redistributor NSACR register
610 */
gicr_read_nsacr(uintptr_t base)611 static inline unsigned int gicr_read_nsacr(uintptr_t base)
612 {
613 return mmio_read_32(base + GICR_NSACR);
614 }
615
gicr_write_nsacr(uintptr_t base,unsigned int val)616 static inline void gicr_write_nsacr(uintptr_t base, unsigned int val)
617 {
618 mmio_write_32(base + GICR_NSACR, val);
619 }
620
621 /*
622 * Accessors to read/write GIC Redistributor PROPBASER register
623 */
gicr_read_propbaser(uintptr_t base)624 static inline uint64_t gicr_read_propbaser(uintptr_t base)
625 {
626 return mmio_read_64(base + GICR_PROPBASER);
627 }
628
gicr_write_propbaser(uintptr_t base,uint64_t val)629 static inline void gicr_write_propbaser(uintptr_t base, uint64_t val)
630 {
631 mmio_write_64(base + GICR_PROPBASER, val);
632 }
633
634 /*
635 * Accessors to read/write GIC Redistributor PENDBASER register
636 */
gicr_read_pendbaser(uintptr_t base)637 static inline uint64_t gicr_read_pendbaser(uintptr_t base)
638 {
639 return mmio_read_64(base + GICR_PENDBASER);
640 }
641
gicr_write_pendbaser(uintptr_t base,uint64_t val)642 static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val)
643 {
644 mmio_write_64(base + GICR_PENDBASER, val);
645 }
646
647 /*******************************************************************************
648 * GIC ITS functions to read and write entire ITS registers.
649 ******************************************************************************/
gits_read_ctlr(uintptr_t base)650 static inline uint32_t gits_read_ctlr(uintptr_t base)
651 {
652 return mmio_read_32(base + GITS_CTLR);
653 }
654
gits_write_ctlr(uintptr_t base,uint32_t val)655 static inline void gits_write_ctlr(uintptr_t base, uint32_t val)
656 {
657 mmio_write_32(base + GITS_CTLR, val);
658 }
659
gits_read_cbaser(uintptr_t base)660 static inline uint64_t gits_read_cbaser(uintptr_t base)
661 {
662 return mmio_read_64(base + GITS_CBASER);
663 }
664
gits_write_cbaser(uintptr_t base,uint64_t val)665 static inline void gits_write_cbaser(uintptr_t base, uint64_t val)
666 {
667 mmio_write_64(base + GITS_CBASER, val);
668 }
669
gits_read_cwriter(uintptr_t base)670 static inline uint64_t gits_read_cwriter(uintptr_t base)
671 {
672 return mmio_read_64(base + GITS_CWRITER);
673 }
674
gits_write_cwriter(uintptr_t base,uint64_t val)675 static inline void gits_write_cwriter(uintptr_t base, uint64_t val)
676 {
677 mmio_write_64(base + GITS_CWRITER, val);
678 }
679
gits_read_baser(uintptr_t base,unsigned int its_table_id)680 static inline uint64_t gits_read_baser(uintptr_t base,
681 unsigned int its_table_id)
682 {
683 assert(its_table_id < 8U);
684 return mmio_read_64(base + GITS_BASER + (8U * its_table_id));
685 }
686
gits_write_baser(uintptr_t base,unsigned int its_table_id,uint64_t val)687 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id,
688 uint64_t val)
689 {
690 assert(its_table_id < 8U);
691 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val);
692 }
693
694 /*
695 * Wait for Quiescent bit when GIC ITS is disabled
696 */
gits_wait_for_quiescent_bit(uintptr_t gits_base)697 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base)
698 {
699 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
700 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) {
701 }
702 }
703
704 #endif /* GICV3_PRIVATE_H */
705