1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <common/debug.h>
11 #include <common/interrupt_props.h>
12 #include <drivers/arm/gic_common.h>
13 #include <drivers/arm/gicv2.h>
14
15 #include "../common/gic_common_private.h"
16 #include "gicv2_private.h"
17
18 /*
19 * Accessor to read the GIC Distributor ITARGETSR corresponding to the
20 * interrupt `id`, 4 interrupt IDs at a time.
21 */
gicd_read_itargetsr(uintptr_t base,unsigned int id)22 unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id)
23 {
24 unsigned n = id >> ITARGETSR_SHIFT;
25 return mmio_read_32(base + GICD_ITARGETSR + (n << 2));
26 }
27
28 /*
29 * Accessor to read the GIC Distributor CPENDSGIR corresponding to the
30 * interrupt `id`, 4 interrupt IDs at a time.
31 */
gicd_read_cpendsgir(uintptr_t base,unsigned int id)32 unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id)
33 {
34 unsigned n = id >> CPENDSGIR_SHIFT;
35 return mmio_read_32(base + GICD_CPENDSGIR + (n << 2));
36 }
37
38 /*
39 * Accessor to read the GIC Distributor SPENDSGIR corresponding to the
40 * interrupt `id`, 4 interrupt IDs at a time.
41 */
gicd_read_spendsgir(uintptr_t base,unsigned int id)42 unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id)
43 {
44 unsigned n = id >> SPENDSGIR_SHIFT;
45 return mmio_read_32(base + GICD_SPENDSGIR + (n << 2));
46 }
47
48 /*
49 * Accessor to write the GIC Distributor ITARGETSR corresponding to the
50 * interrupt `id`, 4 interrupt IDs at a time.
51 */
gicd_write_itargetsr(uintptr_t base,unsigned int id,unsigned int val)52 void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val)
53 {
54 unsigned n = id >> ITARGETSR_SHIFT;
55 mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
56 }
57
58 /*
59 * Accessor to write the GIC Distributor CPENDSGIR corresponding to the
60 * interrupt `id`, 4 interrupt IDs at a time.
61 */
gicd_write_cpendsgir(uintptr_t base,unsigned int id,unsigned int val)62 void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val)
63 {
64 unsigned n = id >> CPENDSGIR_SHIFT;
65 mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val);
66 }
67
68 /*
69 * Accessor to write the GIC Distributor SPENDSGIR corresponding to the
70 * interrupt `id`, 4 interrupt IDs at a time.
71 */
gicd_write_spendsgir(uintptr_t base,unsigned int id,unsigned int val)72 void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val)
73 {
74 unsigned n = id >> SPENDSGIR_SHIFT;
75 mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val);
76 }
77
78 /*******************************************************************************
79 * Get the current CPU bit mask from GICD_ITARGETSR0
80 ******************************************************************************/
gicv2_get_cpuif_id(uintptr_t base)81 unsigned int gicv2_get_cpuif_id(uintptr_t base)
82 {
83 unsigned int val;
84
85 val = gicd_read_itargetsr(base, 0);
86 return val & GIC_TARGET_CPU_MASK;
87 }
88
89 /*******************************************************************************
90 * Helper function to configure the default attributes of SPIs.
91 ******************************************************************************/
gicv2_spis_configure_defaults(uintptr_t gicd_base)92 void gicv2_spis_configure_defaults(uintptr_t gicd_base)
93 {
94 unsigned int index, num_ints;
95
96 num_ints = gicd_read_typer(gicd_base);
97 num_ints &= TYPER_IT_LINES_NO_MASK;
98 num_ints = (num_ints + 1U) << 5;
99
100 /*
101 * Treat all SPIs as G1NS by default. The number of interrupts is
102 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
103 */
104 for (index = MIN_SPI_ID; index < num_ints; index += 32U)
105 gicd_write_igroupr(gicd_base, index, ~0U);
106
107 /* Setup the default SPI priorities doing four at a time */
108 for (index = MIN_SPI_ID; index < num_ints; index += 4U)
109 gicd_write_ipriorityr(gicd_base,
110 index,
111 GICD_IPRIORITYR_DEF_VAL);
112
113 /* Treat all SPIs as level triggered by default, 16 at a time */
114 for (index = MIN_SPI_ID; index < num_ints; index += 16U)
115 gicd_write_icfgr(gicd_base, index, 0U);
116 }
117
118 /*******************************************************************************
119 * Helper function to configure properties of secure G0 SPIs.
120 ******************************************************************************/
gicv2_secure_spis_configure_props(uintptr_t gicd_base,const interrupt_prop_t * interrupt_props,unsigned int interrupt_props_num)121 void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
122 const interrupt_prop_t *interrupt_props,
123 unsigned int interrupt_props_num)
124 {
125 unsigned int i;
126 const interrupt_prop_t *prop_desc;
127
128 /* Make sure there's a valid property array */
129 if (interrupt_props_num != 0U)
130 assert(interrupt_props != NULL);
131
132 for (i = 0; i < interrupt_props_num; i++) {
133 prop_desc = &interrupt_props[i];
134
135 if (prop_desc->intr_num < MIN_SPI_ID)
136 continue;
137
138 /* Configure this interrupt as a secure interrupt */
139 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0);
140 gicd_clr_igroupr(gicd_base, prop_desc->intr_num);
141
142 /* Set the priority of this interrupt */
143 gicd_set_ipriorityr(gicd_base, prop_desc->intr_num,
144 prop_desc->intr_pri);
145
146 /* Target the secure interrupts to primary CPU */
147 gicd_set_itargetsr(gicd_base, prop_desc->intr_num,
148 gicv2_get_cpuif_id(gicd_base));
149
150 /* Set interrupt configuration */
151 gicd_set_icfgr(gicd_base, prop_desc->intr_num,
152 prop_desc->intr_cfg);
153
154 /* Enable this interrupt */
155 gicd_set_isenabler(gicd_base, prop_desc->intr_num);
156 }
157 }
158
159 /*******************************************************************************
160 * Helper function to configure properties of secure G0 SGIs and PPIs.
161 ******************************************************************************/
gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,const interrupt_prop_t * interrupt_props,unsigned int interrupt_props_num)162 void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
163 const interrupt_prop_t *interrupt_props,
164 unsigned int interrupt_props_num)
165 {
166 unsigned int i;
167 uint32_t sec_ppi_sgi_mask = 0;
168 const interrupt_prop_t *prop_desc;
169
170 /* Make sure there's a valid property array */
171 if (interrupt_props_num != 0U)
172 assert(interrupt_props != NULL);
173
174 /*
175 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
176 * more scalable approach as it avoids clearing the enable bits in the
177 * GICD_CTLR.
178 */
179 gicd_write_icenabler(gicd_base, 0U, ~0U);
180
181 /* Setup the default PPI/SGI priorities doing four at a time */
182 for (i = 0U; i < MIN_SPI_ID; i += 4U)
183 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
184
185 for (i = 0U; i < interrupt_props_num; i++) {
186 prop_desc = &interrupt_props[i];
187
188 if (prop_desc->intr_num >= MIN_SPI_ID)
189 continue;
190
191 /* Configure this interrupt as a secure interrupt */
192 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0);
193
194 /*
195 * Set interrupt configuration for PPIs. Configuration for SGIs
196 * are ignored.
197 */
198 if ((prop_desc->intr_num >= MIN_PPI_ID) &&
199 (prop_desc->intr_num < MIN_SPI_ID)) {
200 gicd_set_icfgr(gicd_base, prop_desc->intr_num,
201 prop_desc->intr_cfg);
202 }
203
204 /* We have an SGI or a PPI. They are Group0 at reset */
205 sec_ppi_sgi_mask |= (1u << prop_desc->intr_num);
206
207 /* Set the priority of this interrupt */
208 gicd_set_ipriorityr(gicd_base, prop_desc->intr_num,
209 prop_desc->intr_pri);
210 }
211
212 /*
213 * Invert the bitmask to create a mask for non-secure PPIs and SGIs.
214 * Program the GICD_IGROUPR0 with this bit mask.
215 */
216 gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask);
217
218 /* Enable the Group 0 SGIs and PPIs */
219 gicd_write_isenabler(gicd_base, 0, sec_ppi_sgi_mask);
220 }
221