1 /*
2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * Driver for GIC-500 and GIC-600 specific features. This driver only
10 * overrides APIs that are different to those generic ones in GICv3
11 * driver.
12 *
13 * GIC-600 supports independently power-gating redistributor interface.
14 */
15
16 #include <assert.h>
17
18 #include <arch_helpers.h>
19 #include <drivers/arm/gicv3.h>
20
21 #include "gicv3_private.h"
22
23 /* GIC-600 specific register offsets */
24 #define GICR_PWRR 0x24U
25 #define IIDR_MODEL_ARM_GIC_600 U(0x0200043b)
26 #define IIDR_MODEL_ARM_GIC_600AE U(0x0300043b)
27 #define IIDR_MODEL_ARM_GIC_CLAYTON U(0x0400043b)
28
29 /* GICR_PWRR fields */
30 #define PWRR_RDPD_SHIFT 0
31 #define PWRR_RDAG_SHIFT 1
32 #define PWRR_RDGPD_SHIFT 2
33 #define PWRR_RDGPO_SHIFT 3
34
35 #define PWRR_RDPD (1U << PWRR_RDPD_SHIFT)
36 #define PWRR_RDAG (1U << PWRR_RDAG_SHIFT)
37 #define PWRR_RDGPD (1U << PWRR_RDGPD_SHIFT)
38 #define PWRR_RDGPO (1U << PWRR_RDGPO_SHIFT)
39
40 /*
41 * Values to write to GICR_PWRR register to power redistributor
42 * for operating through the core (GICR_PWRR.RDAG = 0)
43 */
44 #define PWRR_ON (0U << PWRR_RDPD_SHIFT)
45 #define PWRR_OFF (1U << PWRR_RDPD_SHIFT)
46
47 #if GICV3_SUPPORT_GIC600
48
49 /* GIC-600/Clayton specific accessor functions */
gicr_write_pwrr(uintptr_t base,unsigned int val)50 static void gicr_write_pwrr(uintptr_t base, unsigned int val)
51 {
52 mmio_write_32(base + GICR_PWRR, val);
53 }
54
gicr_read_pwrr(uintptr_t base)55 static uint32_t gicr_read_pwrr(uintptr_t base)
56 {
57 return mmio_read_32(base + GICR_PWRR);
58 }
59
gicr_wait_group_not_in_transit(uintptr_t base)60 static void gicr_wait_group_not_in_transit(uintptr_t base)
61 {
62 uint32_t pwrr;
63
64 do {
65 pwrr = gicr_read_pwrr(base);
66
67 /* Check group not transitioning: RDGPD == RDGPO */
68 } while (((pwrr & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) !=
69 ((pwrr & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT));
70 }
71
gic600_pwr_on(uintptr_t base)72 static void gic600_pwr_on(uintptr_t base)
73 {
74 do { /* Wait until group not transitioning */
75 gicr_wait_group_not_in_transit(base);
76
77 /* Power on redistributor */
78 gicr_write_pwrr(base, PWRR_ON);
79
80 /*
81 * Wait until the power on state is reflected.
82 * If RDPD == 0 then powered on.
83 */
84 } while ((gicr_read_pwrr(base) & PWRR_RDPD) != PWRR_ON);
85 }
86
gic600_pwr_off(uintptr_t base)87 static void gic600_pwr_off(uintptr_t base)
88 {
89 /* Wait until group not transitioning */
90 gicr_wait_group_not_in_transit(base);
91
92 /* Power off redistributor */
93 gicr_write_pwrr(base, PWRR_OFF);
94
95 /*
96 * If this is the last man, turning this redistributor frame off will
97 * result in the group itself being powered off and RDGPD = 1.
98 * In that case, wait as long as it's in transition, or has aborted
99 * the transition altogether for any reason.
100 */
101 if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0U) {
102 /* Wait until group not transitioning */
103 gicr_wait_group_not_in_transit(base);
104 }
105 }
106
get_gicr_base(unsigned int proc_num)107 static uintptr_t get_gicr_base(unsigned int proc_num)
108 {
109 uintptr_t gicr_base;
110
111 assert(gicv3_driver_data != NULL);
112 assert(proc_num < gicv3_driver_data->rdistif_num);
113 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
114
115 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
116 assert(gicr_base != 0UL);
117
118 return gicr_base;
119 }
120
gicv3_redists_need_power_mgmt(uintptr_t gicr_base)121 static bool gicv3_redists_need_power_mgmt(uintptr_t gicr_base)
122 {
123 uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR);
124
125 /*
126 * The Arm GIC-600 and GIC-Clayton models have their redistributors
127 * powered down at reset.
128 */
129 return (((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) ||
130 ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600AE) ||
131 ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_CLAYTON));
132 }
133
134 #endif /* GICV3_SUPPORT_GIC600 */
135
gicv3_distif_pre_save(unsigned int proc_num)136 void gicv3_distif_pre_save(unsigned int proc_num)
137 {
138 arm_gicv3_distif_pre_save(proc_num);
139 }
140
gicv3_distif_post_restore(unsigned int proc_num)141 void gicv3_distif_post_restore(unsigned int proc_num)
142 {
143 arm_gicv3_distif_post_restore(proc_num);
144 }
145
146 /*
147 * Power off GIC-600 redistributor (if configured and detected)
148 */
gicv3_rdistif_off(unsigned int proc_num)149 void gicv3_rdistif_off(unsigned int proc_num)
150 {
151 #if GICV3_SUPPORT_GIC600
152 uintptr_t gicr_base = get_gicr_base(proc_num);
153
154 /* Attempt to power redistributor off */
155 if (gicv3_redists_need_power_mgmt(gicr_base)) {
156 gic600_pwr_off(gicr_base);
157 }
158 #endif
159 }
160
161 /*
162 * Power on GIC-600 redistributor (if configured and detected)
163 */
gicv3_rdistif_on(unsigned int proc_num)164 void gicv3_rdistif_on(unsigned int proc_num)
165 {
166 #if GICV3_SUPPORT_GIC600
167 uintptr_t gicr_base = get_gicr_base(proc_num);
168
169 /* Power redistributor on */
170 if (gicv3_redists_need_power_mgmt(gicr_base)) {
171 gic600_pwr_on(gicr_base);
172 }
173 #endif
174 }
175