1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <common/bl_common.h> 12#include <cortex_a53.h> 13#include <cortex_a72.h> 14#include <plat_private.h> 15#include <plat_pmu_macros.S> 16 17 .globl cpuson_entry_point 18 .globl cpuson_flags 19 .globl platform_cpu_warmboot 20 .globl plat_secondary_cold_boot_setup 21 .globl plat_report_exception 22 .globl plat_is_my_cpu_primary 23 .globl plat_my_core_pos 24 .globl plat_reset_handler 25 .globl plat_panic_handler 26 27 /* 28 * void plat_reset_handler(void); 29 * 30 * Determine the SOC type and call the appropriate reset 31 * handler. 32 * 33 */ 34func plat_reset_handler 35 mrs x0, midr_el1 36 ubfx x0, x0, MIDR_PN_SHIFT, #12 37 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 38 b.eq handler_a72 39 b handler_end 40handler_a72: 41 /* 42 * This handler does the following: 43 * Set the L2 Data RAM latency for Cortex-A72. 44 * Set the L2 Tag RAM latency to for Cortex-A72. 45 */ 46 mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 47 (0x1 << 5)) 48 msr CORTEX_A72_L2CTLR_EL1, x0 49 isb 50handler_end: 51 ret 52endfunc plat_reset_handler 53 54func plat_my_core_pos 55 mrs x0, mpidr_el1 56 and x1, x0, #MPIDR_CPU_MASK 57 and x0, x0, #MPIDR_CLUSTER_MASK 58 add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 59 ret 60endfunc plat_my_core_pos 61 62 /* -------------------------------------------------------------------- 63 * void plat_secondary_cold_boot_setup (void); 64 * 65 * This function performs any platform specific actions 66 * needed for a secondary cpu after a cold reset e.g 67 * mark the cpu's presence, mechanism to place it in a 68 * holding pen etc. 69 * -------------------------------------------------------------------- 70 */ 71func plat_secondary_cold_boot_setup 72 /* rk3368 does not do cold boot for secondary CPU */ 73cb_panic: 74 b cb_panic 75endfunc plat_secondary_cold_boot_setup 76 77func plat_is_my_cpu_primary 78 mrs x0, mpidr_el1 79 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 80 cmp x0, #PLAT_RK_PRIMARY_CPU 81 cset x0, eq 82 ret 83endfunc plat_is_my_cpu_primary 84 85 /* -------------------------------------------------------------------- 86 * void plat_panic_handler(void) 87 * Call system reset function on panic. Set up an emergency stack so we 88 * can run C functions (it only needs to last for a few calls until we 89 * reboot anyway). 90 * -------------------------------------------------------------------- 91 */ 92func plat_panic_handler 93 msr spsel, #0 94 bl plat_set_my_stack 95 b rockchip_soc_soft_reset 96endfunc plat_panic_handler 97 98 /* -------------------------------------------------------------------- 99 * void platform_cpu_warmboot (void); 100 * cpus online or resume enterpoint 101 * -------------------------------------------------------------------- 102 */ 103func platform_cpu_warmboot _align=16 104 mrs x0, MPIDR_EL1 105 and x19, x0, #MPIDR_CPU_MASK 106 and x20, x0, #MPIDR_CLUSTER_MASK 107 mov x0, x20 108 func_rockchip_clst_warmboot 109 /* -------------------------------------------------------------------- 110 * big cluster id is 1 111 * big cores id is from 0-3, little cores id 4-7 112 * -------------------------------------------------------------------- 113 */ 114 add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT 115 /* -------------------------------------------------------------------- 116 * get per cpuup flag 117 * -------------------------------------------------------------------- 118 */ 119 adr x4, cpuson_flags 120 add x4, x4, x21, lsl #2 121 ldr w1, [x4] 122 /* -------------------------------------------------------------------- 123 * check cpuon reason 124 * -------------------------------------------------------------------- 125 */ 126 cmp w1, PMU_CPU_AUTO_PWRDN 127 b.eq boot_entry 128 cmp w1, PMU_CPU_HOTPLUG 129 b.eq boot_entry 130 /* -------------------------------------------------------------------- 131 * If the boot core cpuson_flags or cpuson_entry_point is not 132 * expection. force the core into wfe. 133 * -------------------------------------------------------------------- 134 */ 135wfe_loop: 136 wfe 137 b wfe_loop 138boot_entry: 139 str wzr, [x4] 140 /* -------------------------------------------------------------------- 141 * get per cpuup boot addr 142 * -------------------------------------------------------------------- 143 */ 144 adr x5, cpuson_entry_point 145 ldr x2, [x5, x21, lsl #3] 146 br x2 147endfunc platform_cpu_warmboot 148 149 /* -------------------------------------------------------------------- 150 * Per-CPU Secure entry point - resume or power up 151 * -------------------------------------------------------------------- 152 */ 153 .section tzfw_coherent_mem, "a" 154 .align 3 155cpuson_entry_point: 156 .rept PLATFORM_CORE_COUNT 157 .quad 0 158 .endr 159cpuson_flags: 160 .rept PLATFORM_CORE_COUNT 161 .word 0 162 .endr 163rockchip_clst_warmboot_data 164