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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
20 #include "AArch64SelectionDAGInfo.h"
21 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
22 #include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
24 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
38 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
39 public:
40   enum ARMProcFamilyEnum : uint8_t {
41     Others,
42     A64FX,
43     AppleA7,
44     AppleA10,
45     AppleA11,
46     AppleA12,
47     AppleA13,
48     Carmel,
49     CortexA35,
50     CortexA53,
51     CortexA55,
52     CortexA57,
53     CortexA65,
54     CortexA72,
55     CortexA73,
56     CortexA75,
57     CortexA76,
58     CortexA77,
59     CortexA78,
60     CortexR82,
61     CortexX1,
62     ExynosM3,
63     Falkor,
64     Kryo,
65     NeoverseE1,
66     NeoverseN1,
67     NeoverseN2,
68     NeoverseV1,
69     Saphira,
70     ThunderX2T99,
71     ThunderX,
72     ThunderXT81,
73     ThunderXT83,
74     ThunderXT88,
75     ThunderX3T110,
76     TSV110
77   };
78 
79 protected:
80   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
81   ARMProcFamilyEnum ARMProcFamily = Others;
82 
83   bool HasV8_1aOps = false;
84   bool HasV8_2aOps = false;
85   bool HasV8_3aOps = false;
86   bool HasV8_4aOps = false;
87   bool HasV8_5aOps = false;
88   bool HasV8_6aOps = false;
89 
90   bool HasV8_0rOps = false;
91   bool HasCONTEXTIDREL2 = false;
92 
93   bool HasFPARMv8 = false;
94   bool HasNEON = false;
95   bool HasCrypto = false;
96   bool HasDotProd = false;
97   bool HasCRC = false;
98   bool HasLSE = false;
99   bool HasRAS = false;
100   bool HasRDM = false;
101   bool HasPerfMon = false;
102   bool HasFullFP16 = false;
103   bool HasFP16FML = false;
104   bool HasSPE = false;
105 
106   // ARMv8.1 extensions
107   bool HasVH = false;
108   bool HasPAN = false;
109   bool HasLOR = false;
110 
111   // ARMv8.2 extensions
112   bool HasPsUAO = false;
113   bool HasPAN_RWV = false;
114   bool HasCCPP = false;
115 
116   // SVE extensions
117   bool HasSVE = false;
118   bool UseExperimentalZeroingPseudos = false;
119 
120   // Armv8.2 Crypto extensions
121   bool HasSM4 = false;
122   bool HasSHA3 = false;
123   bool HasSHA2 = false;
124   bool HasAES = false;
125 
126   // ARMv8.3 extensions
127   bool HasPA = false;
128   bool HasJS = false;
129   bool HasCCIDX = false;
130   bool HasComplxNum = false;
131 
132   // ARMv8.4 extensions
133   bool HasNV = false;
134   bool HasMPAM = false;
135   bool HasDIT = false;
136   bool HasTRACEV8_4 = false;
137   bool HasAM = false;
138   bool HasSEL2 = false;
139   bool HasPMU = false;
140   bool HasTLB_RMI = false;
141   bool HasFMI = false;
142   bool HasRCPC_IMMO = false;
143 
144   bool HasLSLFast = false;
145   bool HasRCPC = false;
146   bool HasAggressiveFMA = false;
147 
148   // Armv8.5-A Extensions
149   bool HasAlternativeNZCV = false;
150   bool HasFRInt3264 = false;
151   bool HasSpecRestrict = false;
152   bool HasSSBS = false;
153   bool HasSB = false;
154   bool HasPredRes = false;
155   bool HasCCDP = false;
156   bool HasBTI = false;
157   bool HasRandGen = false;
158   bool HasMTE = false;
159   bool HasTME = false;
160 
161   // Armv8.6-A Extensions
162   bool HasBF16 = false;
163   bool HasMatMulInt8 = false;
164   bool HasMatMulFP32 = false;
165   bool HasMatMulFP64 = false;
166   bool HasAMVS = false;
167   bool HasFineGrainedTraps = false;
168   bool HasEnhancedCounterVirtualization = false;
169 
170   // Arm SVE2 extensions
171   bool HasSVE2 = false;
172   bool HasSVE2AES = false;
173   bool HasSVE2SM4 = false;
174   bool HasSVE2SHA3 = false;
175   bool HasSVE2BitPerm = false;
176 
177   // Future architecture extensions.
178   bool HasETE = false;
179   bool HasTRBE = false;
180 
181   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
182   bool HasZeroCycleRegMove = false;
183 
184   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
185   bool HasZeroCycleZeroing = false;
186   bool HasZeroCycleZeroingGP = false;
187   bool HasZeroCycleZeroingFP = false;
188   bool HasZeroCycleZeroingFPWorkaround = false;
189 
190   // StrictAlign - Disallow unaligned memory accesses.
191   bool StrictAlign = false;
192 
193   // NegativeImmediates - transform instructions with negative immediates
194   bool NegativeImmediates = true;
195 
196   // Enable 64-bit vectorization in SLP.
197   unsigned MinVectorRegisterBitWidth = 64;
198 
199   bool OutlineAtomics = false;
200   bool UseAA = false;
201   bool PredictableSelectIsExpensive = false;
202   bool BalanceFPOps = false;
203   bool CustomAsCheapAsMove = false;
204   bool ExynosAsCheapAsMove = false;
205   bool UsePostRAScheduler = false;
206   bool Misaligned128StoreIsSlow = false;
207   bool Paired128IsSlow = false;
208   bool STRQroIsSlow = false;
209   bool UseAlternateSExtLoadCVTF32Pattern = false;
210   bool HasArithmeticBccFusion = false;
211   bool HasArithmeticCbzFusion = false;
212   bool HasFuseAddress = false;
213   bool HasFuseAES = false;
214   bool HasFuseArithmeticLogic = false;
215   bool HasFuseCCSelect = false;
216   bool HasFuseCryptoEOR = false;
217   bool HasFuseLiterals = false;
218   bool DisableLatencySchedHeuristic = false;
219   bool UseRSqrt = false;
220   bool Force32BitJumpTables = false;
221   bool UseEL1ForTP = false;
222   bool UseEL2ForTP = false;
223   bool UseEL3ForTP = false;
224   bool AllowTaggedGlobals = false;
225   bool HardenSlsRetBr = false;
226   bool HardenSlsBlr = false;
227   uint8_t MaxInterleaveFactor = 2;
228   uint8_t VectorInsertExtractBaseCost = 3;
229   uint16_t CacheLineSize = 0;
230   uint16_t PrefetchDistance = 0;
231   uint16_t MinPrefetchStride = 1;
232   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
233   unsigned PrefFunctionLogAlignment = 0;
234   unsigned PrefLoopLogAlignment = 0;
235   unsigned MaxJumpTableSize = 0;
236   unsigned WideningBaseCost = 0;
237 
238   // ReserveXRegister[i] - X#i is not available as a general purpose register.
239   BitVector ReserveXRegister;
240 
241   // CustomCallUsedXRegister[i] - X#i call saved.
242   BitVector CustomCallSavedXRegs;
243 
244   bool IsLittle;
245 
246   /// TargetTriple - What processor and OS we're targeting.
247   Triple TargetTriple;
248 
249   AArch64FrameLowering FrameLowering;
250   AArch64InstrInfo InstrInfo;
251   AArch64SelectionDAGInfo TSInfo;
252   AArch64TargetLowering TLInfo;
253 
254   /// GlobalISel related APIs.
255   std::unique_ptr<CallLowering> CallLoweringInfo;
256   std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
257   std::unique_ptr<InstructionSelector> InstSelector;
258   std::unique_ptr<LegalizerInfo> Legalizer;
259   std::unique_ptr<RegisterBankInfo> RegBankInfo;
260 
261 private:
262   /// initializeSubtargetDependencies - Initializes using CPUString and the
263   /// passed in feature string so that we can use initializer lists for
264   /// subtarget initialization.
265   AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
266                                                     StringRef CPUString);
267 
268   /// Initialize properties based on the selected processor family.
269   void initializeProperties();
270 
271 public:
272   /// This constructor initializes the data members to match that
273   /// of the specified triple.
274   AArch64Subtarget(const Triple &TT, const std::string &CPU,
275                    const std::string &FS, const TargetMachine &TM,
276                    bool LittleEndian);
277 
getSelectionDAGInfo()278   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
279     return &TSInfo;
280   }
getFrameLowering()281   const AArch64FrameLowering *getFrameLowering() const override {
282     return &FrameLowering;
283   }
getTargetLowering()284   const AArch64TargetLowering *getTargetLowering() const override {
285     return &TLInfo;
286   }
getInstrInfo()287   const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
getRegisterInfo()288   const AArch64RegisterInfo *getRegisterInfo() const override {
289     return &getInstrInfo()->getRegisterInfo();
290   }
291   const CallLowering *getCallLowering() const override;
292   const InlineAsmLowering *getInlineAsmLowering() const override;
293   InstructionSelector *getInstructionSelector() const override;
294   const LegalizerInfo *getLegalizerInfo() const override;
295   const RegisterBankInfo *getRegBankInfo() const override;
getTargetTriple()296   const Triple &getTargetTriple() const { return TargetTriple; }
enableMachineScheduler()297   bool enableMachineScheduler() const override { return true; }
enablePostRAScheduler()298   bool enablePostRAScheduler() const override {
299     return UsePostRAScheduler;
300   }
301 
302   /// Returns ARM processor family.
303   /// Avoid this function! CPU specifics should be kept local to this class
304   /// and preferably modeled with SubtargetFeatures or properties in
305   /// initializeProperties().
getProcFamily()306   ARMProcFamilyEnum getProcFamily() const {
307     return ARMProcFamily;
308   }
309 
hasV8_1aOps()310   bool hasV8_1aOps() const { return HasV8_1aOps; }
hasV8_2aOps()311   bool hasV8_2aOps() const { return HasV8_2aOps; }
hasV8_3aOps()312   bool hasV8_3aOps() const { return HasV8_3aOps; }
hasV8_4aOps()313   bool hasV8_4aOps() const { return HasV8_4aOps; }
hasV8_5aOps()314   bool hasV8_5aOps() const { return HasV8_5aOps; }
hasV8_0rOps()315   bool hasV8_0rOps() const { return HasV8_0rOps; }
316 
hasZeroCycleRegMove()317   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
318 
hasZeroCycleZeroingGP()319   bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
320 
hasZeroCycleZeroingFP()321   bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
322 
hasZeroCycleZeroingFPWorkaround()323   bool hasZeroCycleZeroingFPWorkaround() const {
324     return HasZeroCycleZeroingFPWorkaround;
325   }
326 
requiresStrictAlign()327   bool requiresStrictAlign() const { return StrictAlign; }
328 
isXRaySupported()329   bool isXRaySupported() const override { return true; }
330 
getMinVectorRegisterBitWidth()331   unsigned getMinVectorRegisterBitWidth() const {
332     return MinVectorRegisterBitWidth;
333   }
334 
isXRegisterReserved(size_t i)335   bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
getNumXRegisterReserved()336   unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
isXRegCustomCalleeSaved(size_t i)337   bool isXRegCustomCalleeSaved(size_t i) const {
338     return CustomCallSavedXRegs[i];
339   }
hasCustomCallingConv()340   bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
hasFPARMv8()341   bool hasFPARMv8() const { return HasFPARMv8; }
hasNEON()342   bool hasNEON() const { return HasNEON; }
hasCrypto()343   bool hasCrypto() const { return HasCrypto; }
hasDotProd()344   bool hasDotProd() const { return HasDotProd; }
hasCRC()345   bool hasCRC() const { return HasCRC; }
hasLSE()346   bool hasLSE() const { return HasLSE; }
hasRAS()347   bool hasRAS() const { return HasRAS; }
hasRDM()348   bool hasRDM() const { return HasRDM; }
hasSM4()349   bool hasSM4() const { return HasSM4; }
hasSHA3()350   bool hasSHA3() const { return HasSHA3; }
hasSHA2()351   bool hasSHA2() const { return HasSHA2; }
hasAES()352   bool hasAES() const { return HasAES; }
hasCONTEXTIDREL2()353   bool hasCONTEXTIDREL2() const { return HasCONTEXTIDREL2; }
balanceFPOps()354   bool balanceFPOps() const { return BalanceFPOps; }
predictableSelectIsExpensive()355   bool predictableSelectIsExpensive() const {
356     return PredictableSelectIsExpensive;
357   }
hasCustomCheapAsMoveHandling()358   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
hasExynosCheapAsMoveHandling()359   bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
isMisaligned128StoreSlow()360   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
isPaired128Slow()361   bool isPaired128Slow() const { return Paired128IsSlow; }
isSTRQroSlow()362   bool isSTRQroSlow() const { return STRQroIsSlow; }
useAlternateSExtLoadCVTF32Pattern()363   bool useAlternateSExtLoadCVTF32Pattern() const {
364     return UseAlternateSExtLoadCVTF32Pattern;
365   }
hasArithmeticBccFusion()366   bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
hasArithmeticCbzFusion()367   bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
hasFuseAddress()368   bool hasFuseAddress() const { return HasFuseAddress; }
hasFuseAES()369   bool hasFuseAES() const { return HasFuseAES; }
hasFuseArithmeticLogic()370   bool hasFuseArithmeticLogic() const { return HasFuseArithmeticLogic; }
hasFuseCCSelect()371   bool hasFuseCCSelect() const { return HasFuseCCSelect; }
hasFuseCryptoEOR()372   bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
hasFuseLiterals()373   bool hasFuseLiterals() const { return HasFuseLiterals; }
374 
375   /// Return true if the CPU supports any kind of instruction fusion.
hasFusion()376   bool hasFusion() const {
377     return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
378            hasFuseAES() || hasFuseArithmeticLogic() ||
379            hasFuseCCSelect() || hasFuseLiterals();
380   }
381 
hardenSlsRetBr()382   bool hardenSlsRetBr() const { return HardenSlsRetBr; }
hardenSlsBlr()383   bool hardenSlsBlr() const { return HardenSlsBlr; }
384 
useEL1ForTP()385   bool useEL1ForTP() const { return UseEL1ForTP; }
useEL2ForTP()386   bool useEL2ForTP() const { return UseEL2ForTP; }
useEL3ForTP()387   bool useEL3ForTP() const { return UseEL3ForTP; }
388 
useRSqrt()389   bool useRSqrt() const { return UseRSqrt; }
force32BitJumpTables()390   bool force32BitJumpTables() const { return Force32BitJumpTables; }
getMaxInterleaveFactor()391   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
getVectorInsertExtractBaseCost()392   unsigned getVectorInsertExtractBaseCost() const {
393     return VectorInsertExtractBaseCost;
394   }
getCacheLineSize()395   unsigned getCacheLineSize() const override { return CacheLineSize; }
getPrefetchDistance()396   unsigned getPrefetchDistance() const override { return PrefetchDistance; }
getMinPrefetchStride(unsigned NumMemAccesses,unsigned NumStridedMemAccesses,unsigned NumPrefetches,bool HasCall)397   unsigned getMinPrefetchStride(unsigned NumMemAccesses,
398                                 unsigned NumStridedMemAccesses,
399                                 unsigned NumPrefetches,
400                                 bool HasCall) const override {
401     return MinPrefetchStride;
402   }
getMaxPrefetchIterationsAhead()403   unsigned getMaxPrefetchIterationsAhead() const override {
404     return MaxPrefetchIterationsAhead;
405   }
getPrefFunctionLogAlignment()406   unsigned getPrefFunctionLogAlignment() const {
407     return PrefFunctionLogAlignment;
408   }
getPrefLoopLogAlignment()409   unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
410 
getMaximumJumpTableSize()411   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
412 
getWideningBaseCost()413   unsigned getWideningBaseCost() const { return WideningBaseCost; }
414 
useExperimentalZeroingPseudos()415   bool useExperimentalZeroingPseudos() const {
416     return UseExperimentalZeroingPseudos;
417   }
418 
419   /// CPU has TBI (top byte of addresses is ignored during HW address
420   /// translation) and OS enables it.
421   bool supportsAddressTopByteIgnored() const;
422 
hasPerfMon()423   bool hasPerfMon() const { return HasPerfMon; }
hasFullFP16()424   bool hasFullFP16() const { return HasFullFP16; }
hasFP16FML()425   bool hasFP16FML() const { return HasFP16FML; }
hasSPE()426   bool hasSPE() const { return HasSPE; }
hasLSLFast()427   bool hasLSLFast() const { return HasLSLFast; }
hasSVE()428   bool hasSVE() const { return HasSVE; }
hasSVE2()429   bool hasSVE2() const { return HasSVE2; }
hasRCPC()430   bool hasRCPC() const { return HasRCPC; }
hasAggressiveFMA()431   bool hasAggressiveFMA() const { return HasAggressiveFMA; }
hasAlternativeNZCV()432   bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
hasFRInt3264()433   bool hasFRInt3264() const { return HasFRInt3264; }
hasSpecRestrict()434   bool hasSpecRestrict() const { return HasSpecRestrict; }
hasSSBS()435   bool hasSSBS() const { return HasSSBS; }
hasSB()436   bool hasSB() const { return HasSB; }
hasPredRes()437   bool hasPredRes() const { return HasPredRes; }
hasCCDP()438   bool hasCCDP() const { return HasCCDP; }
hasBTI()439   bool hasBTI() const { return HasBTI; }
hasRandGen()440   bool hasRandGen() const { return HasRandGen; }
hasMTE()441   bool hasMTE() const { return HasMTE; }
hasTME()442   bool hasTME() const { return HasTME; }
443   // Arm SVE2 extensions
hasSVE2AES()444   bool hasSVE2AES() const { return HasSVE2AES; }
hasSVE2SM4()445   bool hasSVE2SM4() const { return HasSVE2SM4; }
hasSVE2SHA3()446   bool hasSVE2SHA3() const { return HasSVE2SHA3; }
hasSVE2BitPerm()447   bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
hasMatMulInt8()448   bool hasMatMulInt8() const { return HasMatMulInt8; }
hasMatMulFP32()449   bool hasMatMulFP32() const { return HasMatMulFP32; }
hasMatMulFP64()450   bool hasMatMulFP64() const { return HasMatMulFP64; }
451 
452   // Armv8.6-A Extensions
hasBF16()453   bool hasBF16() const { return HasBF16; }
hasFineGrainedTraps()454   bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
hasEnhancedCounterVirtualization()455   bool hasEnhancedCounterVirtualization() const {
456     return HasEnhancedCounterVirtualization;
457   }
458 
isLittleEndian()459   bool isLittleEndian() const { return IsLittle; }
460 
isTargetDarwin()461   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
isTargetIOS()462   bool isTargetIOS() const { return TargetTriple.isiOS(); }
isTargetLinux()463   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
isTargetWindows()464   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
isTargetAndroid()465   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
isTargetFuchsia()466   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
467 
isTargetCOFF()468   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
isTargetELF()469   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
isTargetMachO()470   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
471 
isTargetILP32()472   bool isTargetILP32() const { return TargetTriple.isArch32Bit(); }
473 
useAA()474   bool useAA() const override { return UseAA; }
475 
outlineAtomics()476   bool outlineAtomics() const { return OutlineAtomics; }
477 
hasVH()478   bool hasVH() const { return HasVH; }
hasPAN()479   bool hasPAN() const { return HasPAN; }
hasLOR()480   bool hasLOR() const { return HasLOR; }
481 
hasPsUAO()482   bool hasPsUAO() const { return HasPsUAO; }
hasPAN_RWV()483   bool hasPAN_RWV() const { return HasPAN_RWV; }
hasCCPP()484   bool hasCCPP() const { return HasCCPP; }
485 
hasPA()486   bool hasPA() const { return HasPA; }
hasJS()487   bool hasJS() const { return HasJS; }
hasCCIDX()488   bool hasCCIDX() const { return HasCCIDX; }
hasComplxNum()489   bool hasComplxNum() const { return HasComplxNum; }
490 
hasNV()491   bool hasNV() const { return HasNV; }
hasMPAM()492   bool hasMPAM() const { return HasMPAM; }
hasDIT()493   bool hasDIT() const { return HasDIT; }
hasTRACEV8_4()494   bool hasTRACEV8_4() const { return HasTRACEV8_4; }
hasAM()495   bool hasAM() const { return HasAM; }
hasAMVS()496   bool hasAMVS() const { return HasAMVS; }
hasSEL2()497   bool hasSEL2() const { return HasSEL2; }
hasPMU()498   bool hasPMU() const { return HasPMU; }
hasTLB_RMI()499   bool hasTLB_RMI() const { return HasTLB_RMI; }
hasFMI()500   bool hasFMI() const { return HasFMI; }
hasRCPC_IMMO()501   bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
502 
addrSinkUsingGEPs()503   bool addrSinkUsingGEPs() const override {
504     // Keeping GEPs inbounds is important for exploiting AArch64
505     // addressing-modes in ILP32 mode.
506     return useAA() || isTargetILP32();
507   }
508 
useSmallAddressing()509   bool useSmallAddressing() const {
510     switch (TLInfo.getTargetMachine().getCodeModel()) {
511       case CodeModel::Kernel:
512         // Kernel is currently allowed only for Fuchsia targets,
513         // where it is the same as Small for almost all purposes.
514       case CodeModel::Small:
515         return true;
516       default:
517         return false;
518     }
519   }
520 
521   /// ParseSubtargetFeatures - Parses features string setting specified
522   /// subtarget options.  Definition of function is auto generated by tblgen.
523   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
524 
525   /// ClassifyGlobalReference - Find the target operand flags that describe
526   /// how a global value should be referenced for the current subtarget.
527   unsigned ClassifyGlobalReference(const GlobalValue *GV,
528                                    const TargetMachine &TM) const;
529 
530   unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
531                                            const TargetMachine &TM) const;
532 
533   void overrideSchedPolicy(MachineSchedPolicy &Policy,
534                            unsigned NumRegionInstrs) const override;
535 
536   bool enableEarlyIfConversion() const override;
537 
enableAdvancedRASplitCost()538   bool enableAdvancedRASplitCost() const override { return true; }
539 
540   std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
541 
isCallingConvWin64(CallingConv::ID CC)542   bool isCallingConvWin64(CallingConv::ID CC) const {
543     switch (CC) {
544     case CallingConv::C:
545     case CallingConv::Fast:
546     case CallingConv::Swift:
547       return isTargetWindows();
548     case CallingConv::Win64:
549       return true;
550     default:
551       return false;
552     }
553   }
554 
555   void mirFileLoaded(MachineFunction &MF) const override;
556 
557   // Return the known range for the bit length of SVE data registers. A value
558   // of 0 means nothing is known about that particular limit beyong what's
559   // implied by the architecture.
560   unsigned getMaxSVEVectorSizeInBits() const;
561   unsigned getMinSVEVectorSizeInBits() const;
562   bool useSVEForFixedLengthVectors() const;
563 };
564 } // End llvm namespace
565 
566 #endif
567