1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_SHADER_H
29 #define RADV_SHADER_H
30
31 #include "ac_binary.h"
32 #include "ac_shader_util.h"
33
34 #include "amd_family.h"
35 #include "radv_constants.h"
36
37 #include "nir/nir.h"
38 #include "vulkan/vulkan.h"
39 #include "vulkan/util/vk_object.h"
40
41 #include "aco_interface.h"
42
43 #define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
44
45 struct radv_device;
46
47 struct radv_shader_module {
48 struct vk_object_base base;
49 struct nir_shader *nir;
50 unsigned char sha1[20];
51 uint32_t size;
52 char data[0];
53 };
54
55 struct radv_vs_out_key {
56 uint32_t as_es:1;
57 uint32_t as_ls:1;
58 uint32_t as_ngg:1;
59 uint32_t as_ngg_passthrough:1;
60 uint32_t export_prim_id:1;
61 uint32_t export_layer_id:1;
62 uint32_t export_clip_dists:1;
63 uint32_t export_viewport_index:1;
64 };
65
66 struct radv_vs_variant_key {
67 struct radv_vs_out_key out;
68
69 uint32_t instance_rate_inputs;
70 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
71 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
72 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
73 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
74 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
75
76 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
77 * so we may need to fix it up. */
78 enum ac_fetch_format alpha_adjust[MAX_VERTEX_ATTRIBS];
79
80 /* For some formats the channels have to be shuffled. */
81 uint32_t post_shuffle;
82
83 /* Output primitive type. */
84 uint8_t outprim;
85 };
86
87 struct radv_tes_variant_key {
88 struct radv_vs_out_key out;
89
90 uint8_t num_patches;
91 };
92
93 struct radv_tcs_variant_key {
94 struct radv_vs_variant_key vs_key;
95 unsigned primitive_mode;
96 unsigned input_vertices;
97 uint32_t tes_reads_tess_factors:1;
98 };
99
100 struct radv_fs_variant_key {
101 uint32_t col_format;
102 uint8_t log2_ps_iter_samples;
103 uint8_t num_samples;
104 uint32_t is_int8;
105 uint32_t is_int10;
106 bool is_dual_src;
107 };
108
109 struct radv_cs_variant_key {
110 uint8_t subgroup_size;
111 };
112
113 struct radv_shader_variant_key {
114 union {
115 struct radv_vs_variant_key vs;
116 struct radv_fs_variant_key fs;
117 struct radv_tes_variant_key tes;
118 struct radv_tcs_variant_key tcs;
119 struct radv_cs_variant_key cs;
120
121 /* A common prefix of the vs and tes keys. */
122 struct radv_vs_out_key vs_common_out;
123 };
124 bool has_multiview_view_index;
125 };
126
127 enum radv_compiler_debug_level {
128 RADV_COMPILER_DEBUG_LEVEL_PERFWARN,
129 RADV_COMPILER_DEBUG_LEVEL_ERROR,
130 };
131
132 struct radv_nir_compiler_options {
133 struct radv_pipeline_layout *layout;
134 struct radv_shader_variant_key key;
135 bool explicit_scratch_args;
136 bool clamp_shadow_reference;
137 bool robust_buffer_access;
138 bool dump_shader;
139 bool dump_preoptir;
140 bool record_ir;
141 bool record_stats;
142 bool check_ir;
143 bool has_ls_vgpr_init_bug;
144 bool use_ngg_streamout;
145 bool enable_mrt_output_nan_fixup;
146 bool disable_optimizations; /* only used by ACO */
147 enum radeon_family family;
148 enum chip_class chip_class;
149 uint32_t tess_offchip_block_dw_size;
150 uint32_t address32_hi;
151
152 struct {
153 void (*func)(void *private_data,
154 enum radv_compiler_debug_level level,
155 const char *message);
156 void *private_data;
157 } debug;
158 };
159
160 enum radv_ud_index {
161 AC_UD_SCRATCH_RING_OFFSETS = 0,
162 AC_UD_PUSH_CONSTANTS = 1,
163 AC_UD_INLINE_PUSH_CONSTANTS = 2,
164 AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
165 AC_UD_VIEW_INDEX = 4,
166 AC_UD_STREAMOUT_BUFFERS = 5,
167 AC_UD_NGG_GS_STATE = 6,
168 AC_UD_SHADER_START = 7,
169 AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
170 AC_UD_VS_BASE_VERTEX_START_INSTANCE,
171 AC_UD_VS_MAX_UD,
172 AC_UD_PS_MAX_UD,
173 AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
174 AC_UD_CS_MAX_UD,
175 AC_UD_GS_MAX_UD,
176 AC_UD_TCS_MAX_UD,
177 AC_UD_TES_MAX_UD,
178 AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
179 };
180
181 struct radv_stream_output {
182 uint8_t location;
183 uint8_t buffer;
184 uint16_t offset;
185 uint8_t component_mask;
186 uint8_t stream;
187 };
188
189 struct radv_streamout_info {
190 uint16_t num_outputs;
191 struct radv_stream_output outputs[MAX_SO_OUTPUTS];
192 uint16_t strides[MAX_SO_BUFFERS];
193 uint32_t enabled_stream_buffers_mask;
194 };
195
196 struct radv_userdata_info {
197 int8_t sgpr_idx;
198 uint8_t num_sgprs;
199 };
200
201 struct radv_userdata_locations {
202 struct radv_userdata_info descriptor_sets[MAX_SETS];
203 struct radv_userdata_info shader_data[AC_UD_MAX_UD];
204 uint32_t descriptor_sets_enabled;
205 };
206
207 struct radv_vs_output_info {
208 uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
209 uint8_t clip_dist_mask;
210 uint8_t cull_dist_mask;
211 uint8_t param_exports;
212 bool writes_pointsize;
213 bool writes_layer;
214 bool writes_viewport_index;
215 bool export_prim_id;
216 unsigned pos_exports;
217 };
218
219 struct radv_es_output_info {
220 uint32_t esgs_itemsize;
221 };
222
223 struct gfx9_gs_info {
224 uint32_t vgt_gs_onchip_cntl;
225 uint32_t vgt_gs_max_prims_per_subgroup;
226 uint32_t vgt_esgs_ring_itemsize;
227 uint32_t lds_size;
228 };
229
230 struct gfx10_ngg_info {
231 uint16_t ngg_emit_size; /* in dwords */
232 uint32_t hw_max_esverts;
233 uint32_t max_gsprims;
234 uint32_t max_out_verts;
235 uint32_t prim_amp_factor;
236 uint32_t vgt_esgs_ring_itemsize;
237 uint32_t esgs_ring_size;
238 bool max_vert_out_per_gs_instance;
239 };
240
241 struct radv_shader_info {
242 bool loads_push_constants;
243 bool loads_dynamic_offsets;
244 uint8_t min_push_constant_used;
245 uint8_t max_push_constant_used;
246 bool has_only_32bit_push_constants;
247 bool has_indirect_push_constants;
248 uint8_t num_inline_push_consts;
249 uint8_t base_inline_push_consts;
250 uint32_t desc_set_used_mask;
251 bool needs_multiview_view_index;
252 bool uses_invocation_id;
253 bool uses_prim_id;
254 uint8_t wave_size;
255 uint8_t ballot_bit_size;
256 struct radv_userdata_locations user_sgprs_locs;
257 unsigned num_user_sgprs;
258 unsigned num_input_sgprs;
259 unsigned num_input_vgprs;
260 unsigned private_mem_vgprs;
261 bool need_indirect_descriptor_sets;
262 bool is_ngg;
263 bool is_ngg_passthrough;
264 struct {
265 uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX];
266 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
267 bool has_vertex_buffers; /* needs vertex buffers and base/start */
268 bool needs_draw_id;
269 bool needs_instance_id;
270 struct radv_vs_output_info outinfo;
271 struct radv_es_output_info es_info;
272 bool as_es;
273 bool as_ls;
274 bool export_prim_id;
275 uint8_t num_linked_outputs;
276 } vs;
277 struct {
278 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
279 uint8_t num_stream_output_components[4];
280 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
281 uint8_t max_stream;
282 unsigned gsvs_vertex_size;
283 unsigned max_gsvs_emit_size;
284 unsigned vertices_in;
285 unsigned vertices_out;
286 unsigned output_prim;
287 unsigned invocations;
288 unsigned es_type; /* GFX9: VS or TES */
289 uint8_t num_linked_inputs;
290 } gs;
291 struct {
292 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
293 struct radv_vs_output_info outinfo;
294 struct radv_es_output_info es_info;
295 bool as_es;
296 unsigned primitive_mode;
297 enum gl_tess_spacing spacing;
298 bool ccw;
299 bool point_mode;
300 bool export_prim_id;
301 uint8_t num_linked_inputs;
302 uint8_t num_linked_patch_inputs;
303 uint8_t num_linked_outputs;
304 } tes;
305 struct {
306 bool force_persample;
307 bool needs_sample_positions;
308 bool writes_memory;
309 bool writes_z;
310 bool writes_stencil;
311 bool writes_sample_mask;
312 bool has_pcoord;
313 bool prim_id_input;
314 bool layer_input;
315 bool viewport_index_input;
316 uint8_t num_input_clips_culls;
317 uint32_t input_mask;
318 uint32_t flat_shaded_mask;
319 uint32_t explicit_shaded_mask;
320 uint32_t float16_shaded_mask;
321 uint32_t num_interp;
322 uint32_t cb_shader_mask;
323 bool can_discard;
324 bool early_fragment_test;
325 bool post_depth_coverage;
326 uint8_t depth_layout;
327 } ps;
328 struct {
329 bool uses_grid_size;
330 bool uses_block_id[3];
331 bool uses_thread_id[3];
332 bool uses_local_invocation_idx;
333 unsigned block_size[3];
334 } cs;
335 struct {
336 uint64_t tes_inputs_read;
337 uint64_t tes_patch_inputs_read;
338 unsigned tcs_vertices_out;
339 uint32_t num_patches;
340 uint32_t num_lds_blocks;
341 uint8_t num_linked_inputs;
342 uint8_t num_linked_outputs;
343 uint8_t num_linked_patch_outputs;
344 } tcs;
345
346 struct radv_streamout_info so;
347
348 struct gfx9_gs_info gs_ring_info;
349 struct gfx10_ngg_info ngg_info;
350
351 unsigned float_controls_mode;
352 };
353
354 enum radv_shader_binary_type {
355 RADV_BINARY_TYPE_LEGACY,
356 RADV_BINARY_TYPE_RTLD
357 };
358
359 struct radv_shader_binary {
360 enum radv_shader_binary_type type;
361 gl_shader_stage stage;
362 bool is_gs_copy_shader;
363
364 struct radv_shader_info info;
365
366 /* Self-referential size so we avoid consistency issues. */
367 uint32_t total_size;
368 };
369
370 struct radv_shader_binary_legacy {
371 struct radv_shader_binary base;
372 struct ac_shader_config config;
373 unsigned code_size;
374 unsigned exec_size;
375 unsigned ir_size;
376 unsigned disasm_size;
377 unsigned stats_size;
378
379 /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
380 * where the +2 is for 0 of the ir strings. */
381 uint8_t data[0];
382 };
383
384 struct radv_shader_binary_rtld {
385 struct radv_shader_binary base;
386 unsigned elf_size;
387 unsigned llvm_ir_size;
388 uint8_t data[0];
389 };
390
391 struct radv_shader_variant {
392 uint32_t ref_count;
393
394 struct radeon_winsys_bo *bo;
395 uint64_t bo_offset;
396 struct ac_shader_config config;
397 uint32_t code_size;
398 uint32_t exec_size;
399 struct radv_shader_info info;
400
401 /* debug only */
402 char *spirv;
403 uint32_t spirv_size;
404 char *nir_string;
405 char *disasm_string;
406 char *ir_string;
407 struct aco_compiler_statistics *statistics;
408
409 struct list_head slab_list;
410 };
411
412 struct radv_shader_slab {
413 struct list_head slabs;
414 struct list_head shaders;
415 struct radeon_winsys_bo *bo;
416 uint64_t size;
417 char *ptr;
418 };
419
420 void
421 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
422 bool allow_copies);
423 bool
424 radv_nir_lower_ycbcr_textures(nir_shader *shader,
425 const struct radv_pipeline_layout *layout);
426
427 nir_shader *
428 radv_shader_compile_to_nir(struct radv_device *device,
429 struct radv_shader_module *module,
430 const char *entrypoint_name,
431 gl_shader_stage stage,
432 const VkSpecializationInfo *spec_info,
433 const VkPipelineCreateFlags flags,
434 const struct radv_pipeline_layout *layout,
435 unsigned subgroup_size, unsigned ballot_bit_size);
436
437 void
438 radv_destroy_shader_slabs(struct radv_device *device);
439
440 VkResult
441 radv_create_shaders(struct radv_pipeline *pipeline,
442 struct radv_device *device,
443 struct radv_pipeline_cache *cache,
444 const struct radv_pipeline_key *key,
445 const VkPipelineShaderStageCreateInfo **pStages,
446 const VkPipelineCreateFlags flags,
447 VkPipelineCreationFeedbackEXT *pipeline_feedback,
448 VkPipelineCreationFeedbackEXT **stage_feedbacks);
449
450 struct radv_shader_variant *
451 radv_shader_variant_create(struct radv_device *device,
452 const struct radv_shader_binary *binary,
453 bool keep_shader_info);
454 struct radv_shader_variant *
455 radv_shader_variant_compile(struct radv_device *device,
456 struct radv_shader_module *module,
457 struct nir_shader *const *shaders,
458 int shader_count,
459 struct radv_pipeline_layout *layout,
460 const struct radv_shader_variant_key *key,
461 struct radv_shader_info *info,
462 bool keep_shader_info, bool keep_statistic_info,
463 bool disable_optimizations,
464 struct radv_shader_binary **binary_out);
465
466 struct radv_shader_variant *
467 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
468 struct radv_shader_info *info,
469 struct radv_shader_binary **binary_out,
470 bool multiview, bool keep_shader_info,
471 bool keep_statistic_info,
472 bool disable_optimizations);
473
474 struct radv_shader_variant *
475 radv_create_trap_handler_shader(struct radv_device *device);
476
477 void
478 radv_shader_variant_destroy(struct radv_device *device,
479 struct radv_shader_variant *variant);
480
481
482 unsigned
483 radv_get_max_waves(struct radv_device *device,
484 struct radv_shader_variant *variant,
485 gl_shader_stage stage);
486
487 unsigned
488 radv_get_max_workgroup_size(enum chip_class chip_class,
489 gl_shader_stage stage,
490 const unsigned *sizes);
491
492 const char *
493 radv_get_shader_name(struct radv_shader_info *info,
494 gl_shader_stage stage);
495
496 bool
497 radv_can_dump_shader(struct radv_device *device,
498 struct radv_shader_module *module,
499 bool is_gs_copy_shader);
500
501 bool
502 radv_can_dump_shader_stats(struct radv_device *device,
503 struct radv_shader_module *module);
504
505 VkResult
506 radv_dump_shader_stats(struct radv_device *device,
507 struct radv_pipeline *pipeline,
508 gl_shader_stage stage, FILE *output);
509
510 static inline unsigned
calculate_tess_lds_size(enum chip_class chip_class,unsigned tcs_num_input_vertices,unsigned tcs_num_output_vertices,unsigned tcs_num_inputs,unsigned tcs_num_patches,unsigned tcs_num_outputs,unsigned tcs_num_patch_outputs)511 calculate_tess_lds_size(enum chip_class chip_class,
512 unsigned tcs_num_input_vertices,
513 unsigned tcs_num_output_vertices,
514 unsigned tcs_num_inputs,
515 unsigned tcs_num_patches,
516 unsigned tcs_num_outputs,
517 unsigned tcs_num_patch_outputs)
518 {
519 unsigned input_vertex_size = tcs_num_inputs * 16;
520 unsigned output_vertex_size = tcs_num_outputs * 16;
521
522 unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size;
523
524 unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
525 unsigned output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
526
527 unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
528
529 unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches;
530
531 if (chip_class >= GFX7) {
532 assert(lds_size <= 65536);
533 lds_size = align(lds_size, 512) / 512;
534 } else {
535 assert(lds_size <= 32768);
536 lds_size = align(lds_size, 256) / 256;
537 }
538
539 return lds_size;
540 }
541
542 static inline unsigned
get_tcs_num_patches(unsigned tcs_num_input_vertices,unsigned tcs_num_output_vertices,unsigned tcs_num_inputs,unsigned tcs_num_outputs,unsigned tcs_num_patch_outputs,unsigned tess_offchip_block_dw_size,enum chip_class chip_class,enum radeon_family family)543 get_tcs_num_patches(unsigned tcs_num_input_vertices,
544 unsigned tcs_num_output_vertices,
545 unsigned tcs_num_inputs,
546 unsigned tcs_num_outputs,
547 unsigned tcs_num_patch_outputs,
548 unsigned tess_offchip_block_dw_size,
549 enum chip_class chip_class,
550 enum radeon_family family)
551 {
552 uint32_t input_vertex_size = tcs_num_inputs * 16;
553 uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size;
554 uint32_t output_vertex_size = tcs_num_outputs * 16;
555 uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
556 uint32_t output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
557
558 /* Ensure that we only need one wave per SIMD so we don't need to check
559 * resource usage. Also ensures that the number of tcs in and out
560 * vertices per threadgroup are at most 256.
561 */
562 unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4;
563 /* Make sure that the data fits in LDS. This assumes the shaders only
564 * use LDS for the inputs and outputs.
565 */
566 unsigned hardware_lds_size = 32768;
567
568 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
569 * threadgroup, even though there is more than 32 KiB LDS.
570 *
571 * Test: dEQP-VK.tessellation.shader_input_output.barrier
572 */
573 if (chip_class >= GFX7 && family != CHIP_STONEY)
574 hardware_lds_size = 65536;
575
576 if (input_patch_size + output_patch_size)
577 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
578 /* Make sure the output data fits in the offchip buffer */
579 if (output_patch_size)
580 num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
581 /* Not necessary for correctness, but improves performance. The
582 * specific value is taken from the proprietary driver.
583 */
584 num_patches = MIN2(num_patches, 40);
585
586 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
587 if (chip_class == GFX6) {
588 unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices);
589 num_patches = MIN2(num_patches, one_wave);
590 }
591 return num_patches;
592 }
593
594 void
595 radv_lower_io(struct radv_device *device, nir_shader *nir);
596
597 #endif
598