1 /*
2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9 #include <stdint.h>
10
11 #include <arch.h>
12 #include <arch_features.h>
13 #include <arch_helpers.h>
14 #include <lib/cassert.h>
15 #include <lib/utils_def.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17
18 #include "../xlat_tables_private.h"
19
20 /*
21 * Returns true if the provided granule size is supported, false otherwise.
22 */
xlat_arch_is_granule_size_supported(size_t size)23 bool xlat_arch_is_granule_size_supported(size_t size)
24 {
25 u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
26
27 if (size == PAGE_SIZE_4KB) {
28 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) &
29 ID_AA64MMFR0_EL1_TGRAN4_MASK) ==
30 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED;
31 } else if (size == PAGE_SIZE_16KB) {
32 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) &
33 ID_AA64MMFR0_EL1_TGRAN16_MASK) ==
34 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED;
35 } else if (size == PAGE_SIZE_64KB) {
36 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) &
37 ID_AA64MMFR0_EL1_TGRAN64_MASK) ==
38 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED;
39 } else {
40 return 0;
41 }
42 }
43
xlat_arch_get_max_supported_granule_size(void)44 size_t xlat_arch_get_max_supported_granule_size(void)
45 {
46 if (xlat_arch_is_granule_size_supported(PAGE_SIZE_64KB)) {
47 return PAGE_SIZE_64KB;
48 } else if (xlat_arch_is_granule_size_supported(PAGE_SIZE_16KB)) {
49 return PAGE_SIZE_16KB;
50 } else {
51 assert(xlat_arch_is_granule_size_supported(PAGE_SIZE_4KB));
52 return PAGE_SIZE_4KB;
53 }
54 }
55
tcr_physical_addr_size_bits(unsigned long long max_addr)56 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr)
57 {
58 /* Physical address can't exceed 48 bits */
59 assert((max_addr & ADDR_MASK_48_TO_63) == 0U);
60
61 /* 48 bits address */
62 if ((max_addr & ADDR_MASK_44_TO_47) != 0U)
63 return TCR_PS_BITS_256TB;
64
65 /* 44 bits address */
66 if ((max_addr & ADDR_MASK_42_TO_43) != 0U)
67 return TCR_PS_BITS_16TB;
68
69 /* 42 bits address */
70 if ((max_addr & ADDR_MASK_40_TO_41) != 0U)
71 return TCR_PS_BITS_4TB;
72
73 /* 40 bits address */
74 if ((max_addr & ADDR_MASK_36_TO_39) != 0U)
75 return TCR_PS_BITS_1TB;
76
77 /* 36 bits address */
78 if ((max_addr & ADDR_MASK_32_TO_35) != 0U)
79 return TCR_PS_BITS_64GB;
80
81 return TCR_PS_BITS_4GB;
82 }
83
84 #if ENABLE_ASSERTIONS
85 /*
86 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is
87 * supported in ARMv8.2 onwards.
88 */
89 static const unsigned int pa_range_bits_arr[] = {
90 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
91 PARANGE_0101, PARANGE_0110
92 };
93
xlat_arch_get_max_supported_pa(void)94 unsigned long long xlat_arch_get_max_supported_pa(void)
95 {
96 u_register_t pa_range = read_id_aa64mmfr0_el1() &
97 ID_AA64MMFR0_EL1_PARANGE_MASK;
98
99 /* All other values are reserved */
100 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr));
101
102 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL;
103 }
104
105 /*
106 * Return minimum virtual address space size supported by the architecture
107 */
xlat_get_min_virt_addr_space_size(void)108 uintptr_t xlat_get_min_virt_addr_space_size(void)
109 {
110 uintptr_t ret;
111
112 if (is_armv8_4_ttst_present())
113 ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
114 else
115 ret = MIN_VIRT_ADDR_SPACE_SIZE;
116
117 return ret;
118 }
119 #endif /* ENABLE_ASSERTIONS*/
120
is_mmu_enabled_ctx(const xlat_ctx_t * ctx)121 bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx)
122 {
123 if (ctx->xlat_regime == EL1_EL0_REGIME) {
124 assert(xlat_arch_current_el() >= 1U);
125 return (read_sctlr_el1() & SCTLR_M_BIT) != 0U;
126 } else if (ctx->xlat_regime == EL2_REGIME) {
127 assert(xlat_arch_current_el() >= 2U);
128 return (read_sctlr_el2() & SCTLR_M_BIT) != 0U;
129 } else {
130 assert(ctx->xlat_regime == EL3_REGIME);
131 assert(xlat_arch_current_el() >= 3U);
132 return (read_sctlr_el3() & SCTLR_M_BIT) != 0U;
133 }
134 }
135
is_dcache_enabled(void)136 bool is_dcache_enabled(void)
137 {
138 unsigned int el = get_current_el_maybe_constant();
139
140 if (el == 1U) {
141 return (read_sctlr_el1() & SCTLR_C_BIT) != 0U;
142 } else if (el == 2U) {
143 return (read_sctlr_el2() & SCTLR_C_BIT) != 0U;
144 } else {
145 return (read_sctlr_el3() & SCTLR_C_BIT) != 0U;
146 }
147 }
148
xlat_arch_regime_get_xn_desc(int xlat_regime)149 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime)
150 {
151 if (xlat_regime == EL1_EL0_REGIME) {
152 return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN);
153 } else {
154 assert((xlat_regime == EL2_REGIME) ||
155 (xlat_regime == EL3_REGIME));
156 return UPPER_ATTRS(XN);
157 }
158 }
159
xlat_arch_tlbi_va(uintptr_t va,int xlat_regime)160 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime)
161 {
162 /*
163 * Ensure the translation table write has drained into memory before
164 * invalidating the TLB entry.
165 */
166 dsbishst();
167
168 /*
169 * This function only supports invalidation of TLB entries for the EL3
170 * and EL1&0 translation regimes.
171 *
172 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher
173 * exception level (see section D4.9.2 of the ARM ARM rev B.a).
174 */
175 if (xlat_regime == EL1_EL0_REGIME) {
176 assert(xlat_arch_current_el() >= 1U);
177 tlbivaae1is(TLBI_ADDR(va));
178 } else if (xlat_regime == EL2_REGIME) {
179 assert(xlat_arch_current_el() >= 2U);
180 tlbivae2is(TLBI_ADDR(va));
181 } else {
182 assert(xlat_regime == EL3_REGIME);
183 assert(xlat_arch_current_el() >= 3U);
184 tlbivae3is(TLBI_ADDR(va));
185 }
186 }
187
xlat_arch_tlbi_va_sync(void)188 void xlat_arch_tlbi_va_sync(void)
189 {
190 /*
191 * A TLB maintenance instruction can complete at any time after
192 * it is issued, but is only guaranteed to be complete after the
193 * execution of DSB by the PE that executed the TLB maintenance
194 * instruction. After the TLB invalidate instruction is
195 * complete, no new memory accesses using the invalidated TLB
196 * entries will be observed by any observer of the system
197 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph
198 * "Ordering and completion of TLB maintenance instructions".
199 */
200 dsbish();
201
202 /*
203 * The effects of a completed TLB maintenance instruction are
204 * only guaranteed to be visible on the PE that executed the
205 * instruction after the execution of an ISB instruction by the
206 * PE that executed the TLB maintenance instruction.
207 */
208 isb();
209 }
210
xlat_arch_current_el(void)211 unsigned int xlat_arch_current_el(void)
212 {
213 unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
214
215 assert(el > 0U);
216
217 return el;
218 }
219
setup_mmu_cfg(uint64_t * params,unsigned int flags,const uint64_t * base_table,unsigned long long max_pa,uintptr_t max_va,int xlat_regime)220 void setup_mmu_cfg(uint64_t *params, unsigned int flags,
221 const uint64_t *base_table, unsigned long long max_pa,
222 uintptr_t max_va, int xlat_regime)
223 {
224 uint64_t mair, ttbr0, tcr;
225 uintptr_t virtual_addr_space_size;
226
227 /* Set attributes in the right indices of the MAIR. */
228 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
229 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX);
230 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX);
231
232 /*
233 * Limit the input address ranges and memory region sizes translated
234 * using TTBR0 to the given virtual address space size.
235 */
236 assert(max_va < ((uint64_t)UINTPTR_MAX));
237
238 virtual_addr_space_size = (uintptr_t)max_va + 1U;
239
240 assert(virtual_addr_space_size >=
241 xlat_get_min_virt_addr_space_size());
242 assert(virtual_addr_space_size <= MAX_VIRT_ADDR_SPACE_SIZE);
243 assert(IS_POWER_OF_TWO(virtual_addr_space_size));
244
245 /*
246 * __builtin_ctzll(0) is undefined but here we are guaranteed that
247 * virtual_addr_space_size is in the range [1,UINTPTR_MAX].
248 */
249 int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size);
250
251 tcr = (uint64_t)t0sz << TCR_T0SZ_SHIFT;
252
253 /*
254 * Set the cacheability and shareability attributes for memory
255 * associated with translation table walks.
256 */
257 if ((flags & XLAT_TABLE_NC) != 0U) {
258 /* Inner & outer non-cacheable non-shareable. */
259 tcr |= TCR_SH_NON_SHAREABLE |
260 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC;
261 } else {
262 /* Inner & outer WBWA & shareable. */
263 tcr |= TCR_SH_INNER_SHAREABLE |
264 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA;
265 }
266
267 /*
268 * It is safer to restrict the max physical address accessible by the
269 * hardware as much as possible.
270 */
271 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa);
272
273 if (xlat_regime == EL1_EL0_REGIME) {
274 /*
275 * TCR_EL1.EPD1: Disable translation table walk for addresses
276 * that are translated using TTBR1_EL1.
277 */
278 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
279 } else if (xlat_regime == EL2_REGIME) {
280 tcr |= TCR_EL2_RES1 | (tcr_ps_bits << TCR_EL2_PS_SHIFT);
281 } else {
282 assert(xlat_regime == EL3_REGIME);
283 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT);
284 }
285
286 /* Set TTBR bits as well */
287 ttbr0 = (uint64_t) base_table;
288
289 if (is_armv8_2_ttcnp_present()) {
290 /* Enable CnP bit so as to share page tables with all PEs. */
291 ttbr0 |= TTBR_CNP_BIT;
292 }
293
294 params[MMU_CFG_MAIR] = mair;
295 params[MMU_CFG_TCR] = tcr;
296 params[MMU_CFG_TTBR0] = ttbr0;
297 }
298