1 #include "intel_chipset.h"
2 #include "i915_pciids.h"
3
4 #include <strings.h> /* ffs() */
5
6 static const struct intel_device_info intel_generic_info = {
7 .gen = 0,
8 };
9
10 static const struct intel_device_info intel_i810_info = {
11 .gen = BIT(0),
12 .is_whitney = true,
13 .codename = "solano" /* 815 == "whitney" ? or vice versa? */
14 };
15
16 static const struct intel_device_info intel_i815_info = {
17 .gen = BIT(0),
18 .is_whitney = true,
19 .codename = "whitney"
20 };
21
22 static const struct intel_device_info intel_i830_info = {
23 .gen = BIT(1),
24 .is_almador = true,
25 .codename = "almador"
26 };
27 static const struct intel_device_info intel_i845_info = {
28 .gen = BIT(1),
29 .is_brookdale = true,
30 .codename = "brookdale"
31 };
32 static const struct intel_device_info intel_i855_info = {
33 .gen = BIT(1),
34 .is_mobile = true,
35 .is_montara = true,
36 .codename = "montara"
37 };
38 static const struct intel_device_info intel_i865_info = {
39 .gen = BIT(1),
40 .is_springdale = true,
41 .codename = "spingdale"
42 };
43
44 static const struct intel_device_info intel_i915_info = {
45 .gen = BIT(2),
46 .is_grantsdale = true,
47 .codename = "grantsdale"
48 };
49 static const struct intel_device_info intel_i915m_info = {
50 .gen = BIT(2),
51 .is_mobile = true,
52 .is_alviso = true,
53 .codename = "alviso"
54 };
55 static const struct intel_device_info intel_i945_info = {
56 .gen = BIT(2),
57 .is_lakeport = true,
58 .codename = "lakeport"
59 };
60 static const struct intel_device_info intel_i945m_info = {
61 .gen = BIT(2),
62 .is_mobile = true,
63 .is_calistoga = true,
64 .codename = "calistoga"
65 };
66
67 static const struct intel_device_info intel_g33_info = {
68 .gen = BIT(2),
69 .is_bearlake = true,
70 .codename = "bearlake"
71 };
72
73 static const struct intel_device_info intel_pineview_g_info = {
74 .gen = BIT(2),
75 .is_pineview = true,
76 .codename = "pineview"
77 };
78
79 static const struct intel_device_info intel_pineview_m_info = {
80 .gen = BIT(2),
81 .is_mobile = true,
82 .is_pineview = true,
83 .codename = "pineview"
84 };
85
86 static const struct intel_device_info intel_i965_info = {
87 .gen = BIT(3),
88 .is_broadwater = true,
89 .codename = "broadwater"
90 };
91
92 static const struct intel_device_info intel_i965m_info = {
93 .gen = BIT(3),
94 .is_mobile = true,
95 .is_crestline = true,
96 .codename = "crestline"
97 };
98
99 static const struct intel_device_info intel_g45_info = {
100 .gen = BIT(3),
101 .is_eaglelake = true,
102 .codename = "eaglelake"
103 };
104 static const struct intel_device_info intel_gm45_info = {
105 .gen = BIT(3),
106 .is_mobile = true,
107 .is_cantiga = true,
108 .codename = "cantiga"
109 };
110
111 static const struct intel_device_info intel_ironlake_info = {
112 .gen = BIT(4),
113 .is_ironlake = true,
114 .codename = "ironlake" /* clarkdale? */
115 };
116 static const struct intel_device_info intel_ironlake_m_info = {
117 .gen = BIT(4),
118 .is_mobile = true,
119 .is_arrandale = true,
120 .codename = "arrandale"
121 };
122
123 static const struct intel_device_info intel_sandybridge_info = {
124 .gen = BIT(5),
125 .is_sandybridge = true,
126 .codename = "sandybridge"
127 };
128 static const struct intel_device_info intel_sandybridge_m_info = {
129 .gen = BIT(5),
130 .is_mobile = true,
131 .is_sandybridge = true,
132 .codename = "sandybridge"
133 };
134
135 static const struct intel_device_info intel_ivybridge_info = {
136 .gen = BIT(6),
137 .is_ivybridge = true,
138 .codename = "ivybridge"
139 };
140 static const struct intel_device_info intel_ivybridge_m_info = {
141 .gen = BIT(6),
142 .is_mobile = true,
143 .is_ivybridge = true,
144 .codename = "ivybridge"
145 };
146
147 static const struct intel_device_info intel_valleyview_info = {
148 .gen = BIT(6),
149 .is_valleyview = true,
150 .codename = "valleyview"
151 };
152
153 #define HASWELL_FIELDS \
154 .gen = BIT(6), \
155 .is_haswell = true, \
156 .codename = "haswell"
157
158 static const struct intel_device_info intel_haswell_gt1_info = {
159 HASWELL_FIELDS,
160 .gt = 1,
161 };
162
163 static const struct intel_device_info intel_haswell_gt2_info = {
164 HASWELL_FIELDS,
165 .gt = 2,
166 };
167
168 static const struct intel_device_info intel_haswell_gt3_info = {
169 HASWELL_FIELDS,
170 .gt = 3,
171 };
172
173 #define BROADWELL_FIELDS \
174 .gen = BIT(7), \
175 .is_broadwell = true, \
176 .codename = "broadwell"
177
178 static const struct intel_device_info intel_broadwell_gt1_info = {
179 BROADWELL_FIELDS,
180 .gt = 1,
181 };
182
183 static const struct intel_device_info intel_broadwell_gt2_info = {
184 BROADWELL_FIELDS,
185 .gt = 2,
186 };
187
188 static const struct intel_device_info intel_broadwell_gt3_info = {
189 BROADWELL_FIELDS,
190 .gt = 3,
191 };
192
193 static const struct intel_device_info intel_broadwell_unknown_info = {
194 BROADWELL_FIELDS,
195 };
196
197 static const struct intel_device_info intel_cherryview_info = {
198 .gen = BIT(7),
199 .is_cherryview = true,
200 .codename = "cherryview"
201 };
202
203 #define SKYLAKE_FIELDS \
204 .gen = BIT(8), \
205 .codename = "skylake", \
206 .is_skylake = true
207
208 static const struct intel_device_info intel_skylake_gt1_info = {
209 SKYLAKE_FIELDS,
210 .gt = 1,
211 };
212
213 static const struct intel_device_info intel_skylake_gt2_info = {
214 SKYLAKE_FIELDS,
215 .gt = 2,
216 };
217
218 static const struct intel_device_info intel_skylake_gt3_info = {
219 SKYLAKE_FIELDS,
220 .gt = 3,
221 };
222
223 static const struct intel_device_info intel_skylake_gt4_info = {
224 SKYLAKE_FIELDS,
225 .gt = 4,
226 };
227
228 static const struct intel_device_info intel_broxton_info = {
229 .gen = BIT(8),
230 .is_broxton = true,
231 .codename = "broxton"
232 };
233
234 #define KABYLAKE_FIELDS \
235 .gen = BIT(8), \
236 .is_kabylake = true, \
237 .codename = "kabylake"
238
239 static const struct intel_device_info intel_kabylake_gt1_info = {
240 KABYLAKE_FIELDS,
241 .gt = 1,
242 };
243
244 static const struct intel_device_info intel_kabylake_gt2_info = {
245 KABYLAKE_FIELDS,
246 .gt = 2,
247 };
248
249 static const struct intel_device_info intel_kabylake_gt3_info = {
250 KABYLAKE_FIELDS,
251 .gt = 3,
252 };
253
254 static const struct intel_device_info intel_kabylake_gt4_info = {
255 KABYLAKE_FIELDS,
256 .gt = 4,
257 };
258
259 static const struct intel_device_info intel_geminilake_info = {
260 .gen = BIT(8),
261 .is_geminilake = true,
262 .codename = "geminilake"
263 };
264
265 #define COFFEELAKE_FIELDS \
266 .gen = BIT(8), \
267 .is_coffeelake = true, \
268 .codename = "coffeelake"
269
270 static const struct intel_device_info intel_coffeelake_gt1_info = {
271 COFFEELAKE_FIELDS,
272 .gt = 1,
273 };
274
275 static const struct intel_device_info intel_coffeelake_gt2_info = {
276 COFFEELAKE_FIELDS,
277 .gt = 2,
278 };
279
280 static const struct intel_device_info intel_coffeelake_gt3_info = {
281 COFFEELAKE_FIELDS,
282 .gt = 3,
283 };
284
285 #define COMETLAKE_FIELDS \
286 .gen = BIT(8), \
287 .is_cometlake = true, \
288 .codename = "cometlake"
289
290 static const struct intel_device_info intel_cometlake_gt1_info = {
291 COMETLAKE_FIELDS,
292 .gt = 1,
293 };
294
295 static const struct intel_device_info intel_cometlake_gt2_info = {
296 COMETLAKE_FIELDS,
297 .gt = 2,
298 };
299
300 static const struct intel_device_info intel_cannonlake_info = {
301 .gen = BIT(9),
302 .is_cannonlake = true,
303 .codename = "cannonlake"
304 };
305
306 static const struct intel_device_info intel_icelake_info = {
307 .gen = BIT(10),
308 .is_icelake = true,
309 .codename = "icelake"
310 };
311
312 static const struct intel_device_info intel_tigerlake_info = {
313 .gen = BIT(11),
314 .is_tigerlake = true,
315 .codename = "tigerlake"
316 };
317
318 static const struct pci_id_match intel_device_match[] = {
319 INTEL_I810_IDS(&intel_i810_info),
320 INTEL_I815_IDS(&intel_i815_info),
321
322 INTEL_I830_IDS(&intel_i830_info),
323 INTEL_I845G_IDS(&intel_i845_info),
324 INTEL_I85X_IDS(&intel_i855_info),
325 INTEL_I865G_IDS(&intel_i865_info),
326
327 INTEL_I915G_IDS(&intel_i915_info),
328 INTEL_I915GM_IDS(&intel_i915m_info),
329 INTEL_I945G_IDS(&intel_i945_info),
330 INTEL_I945GM_IDS(&intel_i945m_info),
331
332 INTEL_G33_IDS(&intel_g33_info),
333 INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
334 INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
335
336 INTEL_I965G_IDS(&intel_i965_info),
337 INTEL_I965GM_IDS(&intel_i965m_info),
338
339 INTEL_G45_IDS(&intel_g45_info),
340 INTEL_GM45_IDS(&intel_gm45_info),
341
342 INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
343 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
344
345 INTEL_SNB_D_IDS(&intel_sandybridge_info),
346 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
347
348 INTEL_IVB_D_IDS(&intel_ivybridge_info),
349 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
350
351 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
352 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
353 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
354
355 INTEL_VLV_IDS(&intel_valleyview_info),
356
357 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
358 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
359 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
360 INTEL_BDW_RSVD_IDS(&intel_broadwell_unknown_info),
361
362 INTEL_CHV_IDS(&intel_cherryview_info),
363
364 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
365 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
366 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
367 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
368
369 INTEL_BXT_IDS(&intel_broxton_info),
370
371 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
372 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
373 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
374 INTEL_KBL_GT4_IDS(&intel_kabylake_gt4_info),
375 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
376
377 INTEL_GLK_IDS(&intel_geminilake_info),
378
379 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
380 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
381 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
382 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
383 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
384 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
385 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
386 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
387 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
388 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
389
390 INTEL_CML_GT1_IDS(&intel_cometlake_gt1_info),
391 INTEL_CML_GT2_IDS(&intel_cometlake_gt2_info),
392
393 INTEL_CNL_IDS(&intel_cannonlake_info),
394
395 INTEL_ICL_11_IDS(&intel_icelake_info),
396
397 INTEL_EHL_IDS(&intel_icelake_info),
398
399 INTEL_TGL_12_IDS(&intel_tigerlake_info),
400
401 INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
402 };
403
404 /**
405 * intel_get_device_info:
406 * @devid: pci device id
407 *
408 * Looks up the Intel GFX device info for the given device id.
409 *
410 * Returns:
411 * The associated intel_get_device_info
412 */
intel_get_device_info(uint16_t devid)413 const struct intel_device_info *intel_get_device_info(uint16_t devid)
414 {
415 static const struct intel_device_info *cache = &intel_generic_info;
416 static uint16_t cached_devid;
417 int i;
418
419 if (cached_devid == devid)
420 goto out;
421
422 /* XXX Presort table and bsearch! */
423 for (i = 0; intel_device_match[i].device_id != PCI_MATCH_ANY; i++) {
424 if (devid == intel_device_match[i].device_id)
425 break;
426 }
427
428 cached_devid = devid;
429 cache = (void *)intel_device_match[i].match_data;
430
431 out:
432 return cache;
433 }
434
435 /**
436 * intel_gen:
437 * @devid: pci device id
438 *
439 * Computes the Intel GFX generation for the given device id.
440 *
441 * Returns:
442 * The GFX generation on successful lookup, 0 on failure.
443 */
intel_gen(uint16_t devid)444 unsigned intel_gen(uint16_t devid)
445 {
446 return ffs(intel_get_device_info(devid)->gen);
447 }
448
449 /**
450 * intel_gt:
451 * @devid: pci device id
452 *
453 * Computes the Intel GFX GT size for the given device id.
454 *
455 * Returns:
456 * The GT size.
457 */
intel_gt(uint16_t devid)458 unsigned intel_gt(uint16_t devid)
459 {
460 unsigned mask = intel_gen(devid);
461
462 if (mask >= 8)
463 mask = 0xf;
464 else if (mask >= 6)
465 mask = 0x3;
466 else
467 mask = 0;
468
469 return (devid >> 4) & mask;
470 }
471