1 /*
2 * Copyright 2003 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "main/mtypes.h"
27 #include "main/blit.h"
28 #include "main/context.h"
29 #include "main/enums.h"
30 #include "main/fbobject.h"
31
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_fbo.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_mipmap_tree.h"
39
40 #define FILE_DEBUG_FLAG DEBUG_BLIT
41
42 static void
43 intel_miptree_set_alpha_to_one(struct brw_context *brw,
44 struct intel_mipmap_tree *mt,
45 int x, int y, int width, int height);
46
translate_raster_op(enum gl_logicop_mode logicop)47 static GLuint translate_raster_op(enum gl_logicop_mode logicop)
48 {
49 return logicop | (logicop << 4);
50 }
51
52 static uint32_t
br13_for_cpp(int cpp)53 br13_for_cpp(int cpp)
54 {
55 switch (cpp) {
56 case 16:
57 return BR13_32323232;
58 case 8:
59 return BR13_16161616;
60 case 4:
61 return BR13_8888;
62 case 2:
63 return BR13_565;
64 case 1:
65 return BR13_8;
66 default:
67 unreachable("not reached");
68 }
69 }
70
71 /**
72 * Emits the packet for switching the blitter from X to Y tiled or back.
73 *
74 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
75 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
76 * part of the power context, not a render context, and if the batchbuffer was
77 * to get flushed between setting and blitting, or blitting and restoring, our
78 * tiling state would leak into other unsuspecting applications (like the X
79 * server).
80 */
81 static uint32_t *
set_blitter_tiling(struct brw_context * brw,bool dst_y_tiled,bool src_y_tiled,uint32_t * __map)82 set_blitter_tiling(struct brw_context *brw,
83 bool dst_y_tiled, bool src_y_tiled,
84 uint32_t *__map)
85 {
86 const struct gen_device_info *devinfo = &brw->screen->devinfo;
87 const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
88 assert(devinfo->gen >= 6);
89
90 /* Idle the blitter before we update how tiling is interpreted. */
91 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
92 OUT_BATCH(0);
93 OUT_BATCH(0);
94 OUT_BATCH(0);
95 if (n_dwords == 5)
96 OUT_BATCH(0);
97
98 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
99 OUT_BATCH(BCS_SWCTRL);
100 OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
101 (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
102 (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
103 return __map;
104 }
105 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
106
107 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
108 unsigned set_tiling_batch_size = 0; \
109 if (dst_y_tiled || src_y_tiled) { \
110 if (devinfo->gen >= 8) \
111 set_tiling_batch_size = 16; \
112 else \
113 set_tiling_batch_size = 14; \
114 } \
115 BEGIN_BATCH_BLT(n + set_tiling_batch_size); \
116 if (dst_y_tiled || src_y_tiled) \
117 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
118
119 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
120 if (dst_y_tiled || src_y_tiled) \
121 SET_BLITTER_TILING(brw, false, false); \
122 ADVANCE_BATCH()
123
124 bool
intel_miptree_blit_compatible_formats(mesa_format src,mesa_format dst)125 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
126 {
127 /* The BLT doesn't handle sRGB conversion */
128 assert(src == _mesa_get_srgb_format_linear(src));
129 assert(dst == _mesa_get_srgb_format_linear(dst));
130
131 /* No swizzle or format conversions possible, except... */
132 if (src == dst)
133 return true;
134
135 /* ...we can either discard the alpha channel when going from A->X,
136 * or we can fill the alpha channel with 0xff when going from X->A
137 */
138 if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
139 return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
140 dst == MESA_FORMAT_B8G8R8X8_UNORM);
141
142 if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
143 return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
144 dst == MESA_FORMAT_R8G8B8X8_UNORM);
145
146 /* We can also discard alpha when going from A2->X2 for 2 bit alpha,
147 * however we can't fill the alpha channel with two 1 bits when going
148 * from X2->A2, because intel_miptree_set_alpha_to_one() is not yet
149 * ready for this / can only handle 8 bit alpha.
150 */
151 if (src == MESA_FORMAT_B10G10R10A2_UNORM)
152 return (dst == MESA_FORMAT_B10G10R10A2_UNORM ||
153 dst == MESA_FORMAT_B10G10R10X2_UNORM);
154
155 if (src == MESA_FORMAT_R10G10B10A2_UNORM)
156 return (dst == MESA_FORMAT_R10G10B10A2_UNORM ||
157 dst == MESA_FORMAT_R10G10B10X2_UNORM);
158
159 return false;
160 }
161
162 static void
get_blit_intratile_offset_el(const struct brw_context * brw,struct intel_mipmap_tree * mt,uint32_t total_x_offset_el,uint32_t total_y_offset_el,uint32_t * base_address_offset,uint32_t * x_offset_el,uint32_t * y_offset_el)163 get_blit_intratile_offset_el(const struct brw_context *brw,
164 struct intel_mipmap_tree *mt,
165 uint32_t total_x_offset_el,
166 uint32_t total_y_offset_el,
167 uint32_t *base_address_offset,
168 uint32_t *x_offset_el,
169 uint32_t *y_offset_el)
170 {
171 isl_tiling_get_intratile_offset_el(mt->surf.tiling,
172 mt->cpp * 8, mt->surf.row_pitch_B,
173 total_x_offset_el, total_y_offset_el,
174 base_address_offset,
175 x_offset_el, y_offset_el);
176 if (mt->surf.tiling == ISL_TILING_LINEAR) {
177 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
178 *
179 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
180 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
181 * enabled), this address must be 4KB-aligned. When Tiling is not
182 * enabled, this address should be CL (64byte) aligned."
183 *
184 * The offsets we get from ISL in the tiled case are already aligned.
185 * In the linear case, we need to do some of our own aligning.
186 */
187 uint32_t delta = *base_address_offset & 63;
188 assert(delta % mt->cpp == 0);
189 *base_address_offset -= delta;
190 *x_offset_el += delta / mt->cpp;
191 } else {
192 assert(*base_address_offset % 4096 == 0);
193 }
194 }
195
196 static bool
alignment_valid(struct brw_context * brw,unsigned offset,enum isl_tiling tiling)197 alignment_valid(struct brw_context *brw, unsigned offset,
198 enum isl_tiling tiling)
199 {
200 const struct gen_device_info *devinfo = &brw->screen->devinfo;
201
202 /* Tiled buffers must be page-aligned (4K). */
203 if (tiling != ISL_TILING_LINEAR)
204 return (offset & 4095) == 0;
205
206 /* On Gen8+, linear buffers must be cacheline-aligned. */
207 if (devinfo->gen >= 8)
208 return (offset & 63) == 0;
209
210 return true;
211 }
212
213 static uint32_t
xy_blit_cmd(enum isl_tiling src_tiling,enum isl_tiling dst_tiling,uint32_t cpp)214 xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling,
215 uint32_t cpp)
216 {
217 uint32_t CMD = 0;
218
219 assert(cpp <= 4);
220 switch (cpp) {
221 case 1:
222 case 2:
223 CMD = XY_SRC_COPY_BLT_CMD;
224 break;
225 case 4:
226 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
227 break;
228 default:
229 unreachable("not reached");
230 }
231
232 if (dst_tiling != ISL_TILING_LINEAR)
233 CMD |= XY_DST_TILED;
234
235 if (src_tiling != ISL_TILING_LINEAR)
236 CMD |= XY_SRC_TILED;
237
238 return CMD;
239 }
240
241 /* Copy BitBlt
242 */
243 static bool
emit_copy_blit(struct brw_context * brw,GLuint cpp,int32_t src_pitch,struct brw_bo * src_buffer,GLuint src_offset,enum isl_tiling src_tiling,int32_t dst_pitch,struct brw_bo * dst_buffer,GLuint dst_offset,enum isl_tiling dst_tiling,GLshort src_x,GLshort src_y,GLshort dst_x,GLshort dst_y,GLshort w,GLshort h,enum gl_logicop_mode logic_op)244 emit_copy_blit(struct brw_context *brw,
245 GLuint cpp,
246 int32_t src_pitch,
247 struct brw_bo *src_buffer,
248 GLuint src_offset,
249 enum isl_tiling src_tiling,
250 int32_t dst_pitch,
251 struct brw_bo *dst_buffer,
252 GLuint dst_offset,
253 enum isl_tiling dst_tiling,
254 GLshort src_x, GLshort src_y,
255 GLshort dst_x, GLshort dst_y,
256 GLshort w, GLshort h,
257 enum gl_logicop_mode logic_op)
258 {
259 const struct gen_device_info *devinfo = &brw->screen->devinfo;
260 GLuint CMD, BR13;
261 int dst_y2 = dst_y + h;
262 int dst_x2 = dst_x + w;
263 bool dst_y_tiled = dst_tiling == ISL_TILING_Y0;
264 bool src_y_tiled = src_tiling == ISL_TILING_Y0;
265 uint32_t src_tile_w, src_tile_h;
266 uint32_t dst_tile_w, dst_tile_h;
267
268 if ((dst_y_tiled || src_y_tiled) && devinfo->gen < 6)
269 return false;
270
271 const unsigned bo_sizes = dst_buffer->size + src_buffer->size;
272
273 /* do space check before going any further */
274 if (!brw_batch_has_aperture_space(brw, bo_sizes))
275 intel_batchbuffer_flush(brw);
276
277 if (!brw_batch_has_aperture_space(brw, bo_sizes))
278 return false;
279
280 unsigned length = devinfo->gen >= 8 ? 10 : 8;
281
282 intel_batchbuffer_require_space(brw, length * 4);
283 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
284 __func__,
285 src_buffer, src_pitch, src_offset, src_x, src_y,
286 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
287
288 intel_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h);
289 intel_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h);
290
291 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
292 * (X direction width of the Tile). This is ensured while allocating the
293 * buffer object.
294 */
295 assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0);
296 assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0);
297
298 /* For big formats (such as floating point), do the copy using 16 or
299 * 32bpp and multiply the coordinates.
300 */
301 if (cpp > 4) {
302 if (cpp % 4 == 2) {
303 dst_x *= cpp / 2;
304 dst_x2 *= cpp / 2;
305 src_x *= cpp / 2;
306 cpp = 2;
307 } else {
308 assert(cpp % 4 == 0);
309 dst_x *= cpp / 4;
310 dst_x2 *= cpp / 4;
311 src_x *= cpp / 4;
312 cpp = 4;
313 }
314 }
315
316 if (!alignment_valid(brw, dst_offset, dst_tiling))
317 return false;
318 if (!alignment_valid(brw, src_offset, src_tiling))
319 return false;
320
321 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
322 * the low bits. Offsets must be naturally aligned.
323 */
324 if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
325 dst_pitch % 4 != 0 || dst_offset % cpp != 0)
326 return false;
327
328 assert(cpp <= 4);
329 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
330
331 CMD = xy_blit_cmd(src_tiling, dst_tiling, cpp);
332
333 /* For tiled source and destination, pitch value should be specified
334 * as a number of Dwords.
335 */
336 if (dst_tiling != ISL_TILING_LINEAR)
337 dst_pitch /= 4;
338
339 if (src_tiling != ISL_TILING_LINEAR)
340 src_pitch /= 4;
341
342 if (dst_y2 <= dst_y || dst_x2 <= dst_x)
343 return true;
344
345 assert(dst_x < dst_x2);
346 assert(dst_y < dst_y2);
347
348 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
349 OUT_BATCH(CMD | (length - 2));
350 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
351 OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
352 OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
353 if (devinfo->gen >= 8) {
354 OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
355 } else {
356 OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
357 }
358 OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
359 OUT_BATCH((uint16_t)src_pitch);
360 if (devinfo->gen >= 8) {
361 OUT_RELOC64(src_buffer, 0, src_offset);
362 } else {
363 OUT_RELOC(src_buffer, 0, src_offset);
364 }
365
366 ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
367
368 brw_emit_mi_flush(brw);
369
370 return true;
371 }
372
373 static bool
emit_miptree_blit(struct brw_context * brw,struct intel_mipmap_tree * src_mt,uint32_t src_x,uint32_t src_y,struct intel_mipmap_tree * dst_mt,uint32_t dst_x,uint32_t dst_y,uint32_t width,uint32_t height,bool reverse,enum gl_logicop_mode logicop)374 emit_miptree_blit(struct brw_context *brw,
375 struct intel_mipmap_tree *src_mt,
376 uint32_t src_x, uint32_t src_y,
377 struct intel_mipmap_tree *dst_mt,
378 uint32_t dst_x, uint32_t dst_y,
379 uint32_t width, uint32_t height,
380 bool reverse, enum gl_logicop_mode logicop)
381 {
382 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
383 * Data Size Limitations):
384 *
385 * The BLT engine is capable of transferring very large quantities of
386 * graphics data. Any graphics data read from and written to the
387 * destination is permitted to represent a number of pixels that
388 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
389 * at the destination. The maximum number of pixels that may be
390 * represented per scan line’s worth of graphics data depends on the
391 * color depth.
392 *
393 * The blitter's pitch is a signed 16-bit integer, but measured in bytes
394 * for linear surfaces and DWords for tiled surfaces. So the maximum
395 * pitch is 32k linear and 128k tiled.
396 */
397 if (intel_miptree_blt_pitch(src_mt) >= 32768 ||
398 intel_miptree_blt_pitch(dst_mt) >= 32768) {
399 perf_debug("Falling back due to >= 32k/128k pitch\n");
400 return false;
401 }
402
403 /* We need to split the blit into chunks that each fit within the blitter's
404 * restrictions. We can't use a chunk size of 32768 because we need to
405 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
406 * a nice round power of two, big enough that performance won't suffer, and
407 * small enough to guarantee everything fits.
408 */
409 const uint32_t max_chunk_size = 16384;
410
411 for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
412 for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
413 const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
414 const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
415
416 uint32_t src_offset, src_tile_x, src_tile_y;
417 get_blit_intratile_offset_el(brw, src_mt,
418 src_x + chunk_x, src_y + chunk_y,
419 &src_offset, &src_tile_x, &src_tile_y);
420
421 uint32_t dst_offset, dst_tile_x, dst_tile_y;
422 get_blit_intratile_offset_el(brw, dst_mt,
423 dst_x + chunk_x, dst_y + chunk_y,
424 &dst_offset, &dst_tile_x, &dst_tile_y);
425
426 if (!emit_copy_blit(brw,
427 src_mt->cpp,
428 reverse ? -src_mt->surf.row_pitch_B :
429 src_mt->surf.row_pitch_B,
430 src_mt->bo, src_mt->offset + src_offset,
431 src_mt->surf.tiling,
432 dst_mt->surf.row_pitch_B,
433 dst_mt->bo, dst_mt->offset + dst_offset,
434 dst_mt->surf.tiling,
435 src_tile_x, src_tile_y,
436 dst_tile_x, dst_tile_y,
437 chunk_w, chunk_h,
438 logicop)) {
439 /* If this is ever going to fail, it will fail on the first chunk */
440 assert(chunk_x == 0 && chunk_y == 0);
441 return false;
442 }
443 }
444 }
445
446 return true;
447 }
448
449 /**
450 * Implements a rectangular block transfer (blit) of pixels between two
451 * miptrees.
452 *
453 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
454 * but limited, pitches and sizes allowed.
455 *
456 * The src/dst coordinates are relative to the given level/slice of the
457 * miptree.
458 *
459 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
460 * will be inverted (including scanline order) when copying. This is common
461 * in GL when copying between window system and user-created
462 * renderbuffers/textures.
463 */
464 bool
intel_miptree_blit(struct brw_context * brw,struct intel_mipmap_tree * src_mt,int src_level,int src_slice,uint32_t src_x,uint32_t src_y,bool src_flip,struct intel_mipmap_tree * dst_mt,int dst_level,int dst_slice,uint32_t dst_x,uint32_t dst_y,bool dst_flip,uint32_t width,uint32_t height,enum gl_logicop_mode logicop)465 intel_miptree_blit(struct brw_context *brw,
466 struct intel_mipmap_tree *src_mt,
467 int src_level, int src_slice,
468 uint32_t src_x, uint32_t src_y, bool src_flip,
469 struct intel_mipmap_tree *dst_mt,
470 int dst_level, int dst_slice,
471 uint32_t dst_x, uint32_t dst_y, bool dst_flip,
472 uint32_t width, uint32_t height,
473 enum gl_logicop_mode logicop)
474 {
475 /* The blitter doesn't understand multisampling at all. */
476 if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
477 return false;
478
479 /* No sRGB decode or encode is done by the hardware blitter, which is
480 * consistent with what we want in many callers (glCopyTexSubImage(),
481 * texture validation, etc.).
482 */
483 mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
484 mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
485
486 /* The blitter doesn't support doing any format conversions. We do also
487 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
488 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
489 * channel to 1.0 at the end. Also trivially ARGB2101010 to XRGB2101010,
490 * but not XRGB2101010 to ARGB2101010 yet.
491 */
492 if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
493 perf_debug("%s: Can't use hardware blitter from %s to %s, "
494 "falling back.\n", __func__,
495 _mesa_get_format_name(src_format),
496 _mesa_get_format_name(dst_format));
497 return false;
498 }
499
500 /* The blitter has no idea about HiZ or fast color clears, so we need to
501 * resolve the miptrees before we do anything.
502 */
503 intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
504 intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
505
506 if (src_flip) {
507 const unsigned h0 = src_mt->surf.phys_level0_sa.height;
508 src_y = minify(h0, src_level - src_mt->first_level) - src_y - height;
509 }
510
511 if (dst_flip) {
512 const unsigned h0 = dst_mt->surf.phys_level0_sa.height;
513 dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height;
514 }
515
516 uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
517 intel_miptree_get_image_offset(src_mt, src_level, src_slice,
518 &src_image_x, &src_image_y);
519 intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
520 &dst_image_x, &dst_image_y);
521 src_x += src_image_x;
522 src_y += src_image_y;
523 dst_x += dst_image_x;
524 dst_y += dst_image_y;
525
526 if (!emit_miptree_blit(brw, src_mt, src_x, src_y,
527 dst_mt, dst_x, dst_y, width, height,
528 src_flip != dst_flip, logicop)) {
529 return false;
530 }
531
532 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
533 if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
534 _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
535 intel_miptree_set_alpha_to_one(brw, dst_mt,
536 dst_x, dst_y,
537 width, height);
538 }
539
540 return true;
541 }
542
543 bool
intel_miptree_copy(struct brw_context * brw,struct intel_mipmap_tree * src_mt,int src_level,int src_slice,uint32_t src_x,uint32_t src_y,struct intel_mipmap_tree * dst_mt,int dst_level,int dst_slice,uint32_t dst_x,uint32_t dst_y,uint32_t src_width,uint32_t src_height)544 intel_miptree_copy(struct brw_context *brw,
545 struct intel_mipmap_tree *src_mt,
546 int src_level, int src_slice,
547 uint32_t src_x, uint32_t src_y,
548 struct intel_mipmap_tree *dst_mt,
549 int dst_level, int dst_slice,
550 uint32_t dst_x, uint32_t dst_y,
551 uint32_t src_width, uint32_t src_height)
552 {
553 /* The blitter doesn't understand multisampling at all. */
554 if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
555 return false;
556
557 if (src_mt->format == MESA_FORMAT_S_UINT8)
558 return false;
559
560 /* The blitter has no idea about HiZ or fast color clears, so we need to
561 * resolve the miptrees before we do anything.
562 */
563 intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
564 intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
565
566 uint32_t src_image_x, src_image_y;
567 intel_miptree_get_image_offset(src_mt, src_level, src_slice,
568 &src_image_x, &src_image_y);
569
570 if (_mesa_is_format_compressed(src_mt->format)) {
571 GLuint bw, bh;
572 _mesa_get_format_block_size(src_mt->format, &bw, &bh);
573
574 /* Compressed textures need not have dimensions that are a multiple of
575 * the block size. Rectangles in compressed textures do need to be a
576 * multiple of the block size. The one exception is that the right and
577 * bottom edges may be at the right or bottom edge of the miplevel even
578 * if it's not aligned.
579 */
580 assert(src_x % bw == 0);
581 assert(src_y % bh == 0);
582
583 assert(src_width % bw == 0 ||
584 src_x + src_width ==
585 minify(src_mt->surf.logical_level0_px.width, src_level));
586 assert(src_height % bh == 0 ||
587 src_y + src_height ==
588 minify(src_mt->surf.logical_level0_px.height, src_level));
589
590 src_x /= (int)bw;
591 src_y /= (int)bh;
592 src_width = DIV_ROUND_UP(src_width, (int)bw);
593 src_height = DIV_ROUND_UP(src_height, (int)bh);
594 }
595 src_x += src_image_x;
596 src_y += src_image_y;
597
598 uint32_t dst_image_x, dst_image_y;
599 intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
600 &dst_image_x, &dst_image_y);
601
602 if (_mesa_is_format_compressed(dst_mt->format)) {
603 GLuint bw, bh;
604 _mesa_get_format_block_size(dst_mt->format, &bw, &bh);
605
606 assert(dst_x % bw == 0);
607 assert(dst_y % bh == 0);
608
609 dst_x /= (int)bw;
610 dst_y /= (int)bh;
611 }
612 dst_x += dst_image_x;
613 dst_y += dst_image_y;
614
615 return emit_miptree_blit(brw, src_mt, src_x, src_y,
616 dst_mt, dst_x, dst_y,
617 src_width, src_height, false, COLOR_LOGICOP_COPY);
618 }
619
620 bool
intelEmitImmediateColorExpandBlit(struct brw_context * brw,GLuint cpp,GLubyte * src_bits,GLuint src_size,GLuint fg_color,GLshort dst_pitch,struct brw_bo * dst_buffer,GLuint dst_offset,enum isl_tiling dst_tiling,GLshort x,GLshort y,GLshort w,GLshort h,enum gl_logicop_mode logic_op)621 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
622 GLuint cpp,
623 GLubyte *src_bits, GLuint src_size,
624 GLuint fg_color,
625 GLshort dst_pitch,
626 struct brw_bo *dst_buffer,
627 GLuint dst_offset,
628 enum isl_tiling dst_tiling,
629 GLshort x, GLshort y,
630 GLshort w, GLshort h,
631 enum gl_logicop_mode logic_op)
632 {
633 const struct gen_device_info *devinfo = &brw->screen->devinfo;
634 int dwords = ALIGN(src_size, 8) / 4;
635 uint32_t opcode, br13, blit_cmd;
636
637 if (dst_tiling != ISL_TILING_LINEAR) {
638 if (dst_offset & 4095)
639 return false;
640 if (dst_tiling == ISL_TILING_Y0)
641 return false;
642 }
643
644 assert((unsigned) logic_op <= 0x0f);
645 assert(dst_pitch > 0);
646
647 if (w < 0 || h < 0)
648 return true;
649
650 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
651 __func__,
652 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
653
654 unsigned xy_setup_blt_length = devinfo->gen >= 8 ? 10 : 8;
655 intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
656 (3 * 4) + dwords * 4);
657
658 opcode = XY_SETUP_BLT_CMD;
659 if (cpp == 4)
660 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
661 if (dst_tiling != ISL_TILING_LINEAR) {
662 opcode |= XY_DST_TILED;
663 dst_pitch /= 4;
664 }
665
666 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
667 br13 |= br13_for_cpp(cpp);
668
669 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
670 if (dst_tiling != ISL_TILING_LINEAR)
671 blit_cmd |= XY_DST_TILED;
672
673 BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
674 OUT_BATCH(opcode | (xy_setup_blt_length - 2));
675 OUT_BATCH(br13);
676 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
677 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
678 if (devinfo->gen >= 8) {
679 OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
680 } else {
681 OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
682 }
683 OUT_BATCH(0); /* bg */
684 OUT_BATCH(fg_color); /* fg */
685 OUT_BATCH(0); /* pattern base addr */
686 if (devinfo->gen >= 8)
687 OUT_BATCH(0);
688
689 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
690 OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
691 OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
692 ADVANCE_BATCH();
693
694 intel_batchbuffer_data(brw, src_bits, dwords * 4);
695
696 brw_emit_mi_flush(brw);
697
698 return true;
699 }
700
701 /**
702 * Used to initialize the alpha value of an ARGB8888 miptree after copying
703 * into it from an XRGB8888 source.
704 *
705 * This is very common with glCopyTexImage2D(). Note that the coordinates are
706 * relative to the start of the miptree, not relative to a slice within the
707 * miptree.
708 */
709 static void
intel_miptree_set_alpha_to_one(struct brw_context * brw,struct intel_mipmap_tree * mt,int x,int y,int width,int height)710 intel_miptree_set_alpha_to_one(struct brw_context *brw,
711 struct intel_mipmap_tree *mt,
712 int x, int y, int width, int height)
713 {
714 const struct gen_device_info *devinfo = &brw->screen->devinfo;
715 uint32_t BR13, CMD;
716 int pitch, cpp;
717
718 pitch = mt->surf.row_pitch_B;
719 cpp = mt->cpp;
720
721 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
722 __func__, mt->bo, pitch, x, y, width, height);
723
724 /* Note: Currently only handles 8 bit alpha channel. Extension to < 8 Bit
725 * alpha channel would be likely possible via ROP code 0xfa instead of 0xf0
726 * and writing a suitable bit-mask instead of 0xffffffff.
727 */
728 BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
729 CMD = XY_COLOR_BLT_CMD;
730 CMD |= XY_BLT_WRITE_ALPHA;
731
732 if (mt->surf.tiling != ISL_TILING_LINEAR) {
733 CMD |= XY_DST_TILED;
734 pitch /= 4;
735 }
736 BR13 |= pitch;
737
738 /* do space check before going any further */
739 if (!brw_batch_has_aperture_space(brw, mt->bo->size))
740 intel_batchbuffer_flush(brw);
741
742 unsigned length = devinfo->gen >= 8 ? 7 : 6;
743 const bool dst_y_tiled = mt->surf.tiling == ISL_TILING_Y0;
744
745 /* We need to split the blit into chunks that each fit within the blitter's
746 * restrictions. We can't use a chunk size of 32768 because we need to
747 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
748 * a nice round power of two, big enough that performance won't suffer, and
749 * small enough to guarantee everything fits.
750 */
751 const uint32_t max_chunk_size = 16384;
752
753 for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
754 for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
755 const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
756 const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
757
758 uint32_t offset, tile_x, tile_y;
759 get_blit_intratile_offset_el(brw, mt,
760 x + chunk_x, y + chunk_y,
761 &offset, &tile_x, &tile_y);
762
763 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
764 OUT_BATCH(CMD | (length - 2));
765 OUT_BATCH(BR13);
766 OUT_BATCH(SET_FIELD(y + chunk_y, BLT_Y) |
767 SET_FIELD(x + chunk_x, BLT_X));
768 OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
769 SET_FIELD(x + chunk_x + chunk_w, BLT_X));
770 if (devinfo->gen >= 8) {
771 OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset);
772 } else {
773 OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset);
774 }
775 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
776 ADVANCE_BATCH_TILED(dst_y_tiled, false);
777 }
778 }
779
780 brw_emit_mi_flush(brw);
781 }
782