1 /*
2 * Copyright (C) 2016 - 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 /* IOW unit device driver for Marvell CP110 and CP115 SoCs */
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/marvell/iob.h>
13 #include <lib/mmio.h>
14
15 #include <armada_common.h>
16 #include <mvebu.h>
17 #include <mvebu_def.h>
18
19 #if LOG_LEVEL >= LOG_LEVEL_INFO
20 #define DEBUG_ADDR_MAP
21 #endif
22
23 #define MVEBU_IOB_OFFSET (0x190000)
24 #define MVEBU_IOB_MAX_WINS 16
25
26 /* common defines */
27 #define WIN_ENABLE_BIT (0x1)
28 /* Physical address of the base of the window = {AddrLow[19:0],20`h0} */
29 #define ADDRESS_SHIFT (20 - 4)
30 #define ADDRESS_MASK (0xFFFFFFF0)
31 #define IOB_WIN_ALIGNMENT (0x100000)
32
33 /* IOB registers */
34 #define IOB_WIN_CR_OFFSET(win) (iob_base + 0x0 + (0x20 * win))
35 #define IOB_TARGET_ID_OFFSET (8)
36 #define IOB_TARGET_ID_MASK (0xF)
37
38 #define IOB_WIN_SCR_OFFSET(win) (iob_base + 0x4 + (0x20 * win))
39 #define IOB_WIN_ENA_CTRL_WRITE_SECURE (0x1)
40 #define IOB_WIN_ENA_CTRL_READ_SECURE (0x2)
41 #define IOB_WIN_ENA_WRITE_SECURE (0x4)
42 #define IOB_WIN_ENA_READ_SECURE (0x8)
43
44 #define IOB_WIN_ALR_OFFSET(win) (iob_base + 0x8 + (0x20 * win))
45 #define IOB_WIN_AHR_OFFSET(win) (iob_base + 0xC + (0x20 * win))
46
47 uintptr_t iob_base;
48
iob_win_check(struct addr_map_win * win,uint32_t win_num)49 static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
50 {
51 /* check if address is aligned to the size */
52 if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) {
53 win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT);
54 ERROR("Window %d: base address unaligned to 0x%x\n",
55 win_num, IOB_WIN_ALIGNMENT);
56 printf("Align up the base address to 0x%llx\n",
57 win->base_addr);
58 }
59
60 /* size parameter validity check */
61 if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) {
62 win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT);
63 ERROR("Window %d: window size unaligned to 0x%x\n", win_num,
64 IOB_WIN_ALIGNMENT);
65 printf("Aligning size to 0x%llx\n", win->win_size);
66 }
67 }
68
iob_enable_win(struct addr_map_win * win,uint32_t win_id)69 static void iob_enable_win(struct addr_map_win *win, uint32_t win_id)
70 {
71 uint32_t iob_win_reg;
72 uint32_t alr, ahr;
73 uint64_t end_addr;
74
75 end_addr = (win->base_addr + win->win_size - 1);
76 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
77 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
78
79 mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr);
80 mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr);
81
82 iob_win_reg = WIN_ENABLE_BIT;
83 iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK)
84 << IOB_TARGET_ID_OFFSET;
85 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg);
86
87 }
88
89 #ifdef DEBUG_ADDR_MAP
dump_iob(void)90 static void dump_iob(void)
91 {
92 uint32_t win_id, win_cr, alr, ahr;
93 uint8_t target_id;
94 uint64_t start, end;
95 char *iob_target_name[IOB_MAX_TID] = {
96 "CFG ", "MCI0 ", "PEX1 ", "PEX2 ",
97 "PEX0 ", "NAND ", "RUNIT", "MCI1 " };
98
99 /* Dump all IOB windows */
100 printf("bank id target start end\n");
101 printf("----------------------------------------------------\n");
102 for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
103 win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
104 if (win_cr & WIN_ENABLE_BIT) {
105 target_id = (win_cr >> IOB_TARGET_ID_OFFSET) &
106 IOB_TARGET_ID_MASK;
107 alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id));
108 start = ((uint64_t)alr << ADDRESS_SHIFT);
109 if (win_id != 0) {
110 ahr = mmio_read_32(IOB_WIN_AHR_OFFSET(win_id));
111 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
112 } else {
113 /* Window #0 size is hardcoded to 16MB, as it's
114 * reserved for CP configuration space.
115 */
116 end = start + (16 << 20);
117 }
118 printf("iob %02d %s 0x%016llx 0x%016llx\n",
119 win_id, iob_target_name[target_id],
120 start, end);
121 }
122 }
123 }
124 #endif
125
iob_cfg_space_update(int ap_idx,int cp_idx,uintptr_t base,uintptr_t new_base)126 void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base,
127 uintptr_t new_base)
128 {
129 debug_enter();
130
131 iob_base = base + MVEBU_IOB_OFFSET;
132
133 NOTICE("Change the base address of AP%d-CP%d to %lx\n",
134 ap_idx, cp_idx, new_base);
135 mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT);
136
137 iob_base = new_base + MVEBU_IOB_OFFSET;
138
139 /* Make sure the address was configured by the CPU before
140 * any possible access to the CP.
141 */
142 dsb();
143
144 debug_exit();
145 }
146
init_iob(uintptr_t base)147 int init_iob(uintptr_t base)
148 {
149 struct addr_map_win *win;
150 uint32_t win_id, win_reg;
151 uint32_t win_count;
152
153 INFO("Initializing IOB Address decoding\n");
154
155 /* Get the base address of the address decoding MBUS */
156 iob_base = base + MVEBU_IOB_OFFSET;
157
158 /* Get the array of the windows and fill the map data */
159 marvell_get_iob_memory_map(&win, &win_count, base);
160 if (win_count <= 0) {
161 INFO("no windows configurations found\n");
162 return 0;
163 } else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) {
164 ERROR("IOB mem map array > than max available windows (%d)\n",
165 MVEBU_IOB_MAX_WINS);
166 win_count = MVEBU_IOB_MAX_WINS;
167 }
168
169 /* disable all IOB windows, start from win_id = 1
170 * because can't disable internal register window
171 */
172 for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
173 win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
174 win_reg &= ~WIN_ENABLE_BIT;
175 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), win_reg);
176
177 win_reg = ~IOB_WIN_ENA_CTRL_WRITE_SECURE;
178 win_reg &= ~IOB_WIN_ENA_CTRL_READ_SECURE;
179 win_reg &= ~IOB_WIN_ENA_WRITE_SECURE;
180 win_reg &= ~IOB_WIN_ENA_READ_SECURE;
181 mmio_write_32(IOB_WIN_SCR_OFFSET(win_id), win_reg);
182 }
183
184 for (win_id = 1; win_id < win_count + 1; win_id++, win++) {
185 iob_win_check(win, win_id);
186 iob_enable_win(win, win_id);
187 }
188
189 #ifdef DEBUG_ADDR_MAP
190 dump_iob();
191 #endif
192
193 INFO("Done IOB Address decoding Initializing\n");
194
195 return 0;
196 }
197