1 /*
2 * Copyright © 2020 Google, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <stdlib.h>
25
26 #include "util/ralloc.h"
27
28 #include "ir3.h"
29
30 struct ir3_validate_ctx {
31 struct ir3 *ir;
32
33 /* Current instruction being validated: */
34 struct ir3_instruction *current_instr;
35
36 /* Set of instructions found so far, used to validate that we
37 * don't have SSA uses that occure before def's
38 */
39 struct set *defs;
40 };
41
42 static void
validate_error(struct ir3_validate_ctx * ctx,const char * condstr)43 validate_error(struct ir3_validate_ctx *ctx, const char *condstr)
44 {
45 fprintf(stderr, "validation fail: %s\n", condstr);
46 fprintf(stderr, " -> for instruction: ");
47 ir3_print_instr(ctx->current_instr);
48 abort();
49 }
50
51 #define validate_assert(ctx, cond) do { \
52 if (!(cond)) { \
53 validate_error(ctx, #cond); \
54 } } while (0)
55
56 static unsigned
reg_class_flags(struct ir3_register * reg)57 reg_class_flags(struct ir3_register *reg)
58 {
59 return reg->flags & (IR3_REG_HALF | IR3_REG_HIGH);
60 }
61
62 static void
validate_src(struct ir3_validate_ctx * ctx,struct ir3_register * reg)63 validate_src(struct ir3_validate_ctx *ctx, struct ir3_register *reg)
64 {
65 struct ir3_instruction *src = ssa(reg);
66
67 if (!src)
68 return;
69
70 validate_assert(ctx, _mesa_set_search(ctx->defs, src));
71 validate_assert(ctx, src->regs[0]->wrmask == reg->wrmask);
72 validate_assert(ctx, reg_class_flags(src->regs[0]) == reg_class_flags(reg));
73 }
74
75 static void
validate_instr(struct ir3_validate_ctx * ctx,struct ir3_instruction * instr)76 validate_instr(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr)
77 {
78 struct ir3_register *last_reg = NULL;
79
80 if (writes_gpr(instr)) {
81 if (instr->regs[0]->flags & IR3_REG_RELATIV) {
82 validate_assert(ctx, instr->address);
83 }
84 }
85
86 foreach_src_n (reg, n, instr) {
87 if (reg->flags & IR3_REG_RELATIV)
88 validate_assert(ctx, instr->address);
89
90 validate_src(ctx, reg);
91
92 /* Validate that all src's are either half of full.
93 *
94 * Note: tex instructions w/ .s2en are a bit special in that the
95 * tex/samp src reg is half-reg for non-bindless and full for
96 * bindless, irrespective of the precision of other srcs. The
97 * tex/samp src is the first src reg when .s2en is set
98 */
99 if ((instr->flags & IR3_INSTR_S2EN) && (n < 2)) {
100 if (n == 0) {
101 if (instr->flags & IR3_INSTR_B)
102 validate_assert(ctx, !(reg->flags & IR3_REG_HALF));
103 else
104 validate_assert(ctx, reg->flags & IR3_REG_HALF);
105 }
106 } else if (n > 0) {
107 validate_assert(ctx, (last_reg->flags & IR3_REG_HALF) == (reg->flags & IR3_REG_HALF));
108 }
109
110 last_reg = reg;
111 }
112
113 _mesa_set_add(ctx->defs, instr);
114
115 /* Check that src/dst types match the register types, and for
116 * instructions that have different opcodes depending on type,
117 * that the opcodes are correct.
118 */
119 switch (opc_cat(instr->opc)) {
120 case 1: /* move instructions */
121 if (instr->regs[0]->flags & IR3_REG_HALF) {
122 validate_assert(ctx, instr->cat1.dst_type == half_type(instr->cat1.dst_type));
123 } else {
124 validate_assert(ctx, instr->cat1.dst_type == full_type(instr->cat1.dst_type));
125 }
126 if (instr->regs[1]->flags & IR3_REG_HALF) {
127 validate_assert(ctx, instr->cat1.src_type == half_type(instr->cat1.src_type));
128 } else {
129 validate_assert(ctx, instr->cat1.src_type == full_type(instr->cat1.src_type));
130 }
131 break;
132 case 3:
133 /* Validate that cat3 opc matches the src type. We've already checked that all
134 * the src regs are same type
135 */
136 if (instr->regs[1]->flags & IR3_REG_HALF) {
137 validate_assert(ctx, instr->opc == cat3_half_opc(instr->opc));
138 } else {
139 validate_assert(ctx, instr->opc == cat3_full_opc(instr->opc));
140 }
141 break;
142 case 4:
143 /* Validate that cat4 opc matches the dst type: */
144 if (instr->regs[0]->flags & IR3_REG_HALF) {
145 validate_assert(ctx, instr->opc == cat4_half_opc(instr->opc));
146 } else {
147 validate_assert(ctx, instr->opc == cat4_full_opc(instr->opc));
148 }
149 break;
150 case 5:
151 if (instr->regs[0]->flags & IR3_REG_HALF) {
152 validate_assert(ctx, instr->cat5.type == half_type(instr->cat5.type));
153 } else {
154 validate_assert(ctx, instr->cat5.type == full_type(instr->cat5.type));
155 }
156 break;
157 }
158 }
159
160 void
ir3_validate(struct ir3 * ir)161 ir3_validate(struct ir3 *ir)
162 {
163 #ifdef NDEBUG
164 # define VALIDATE 0
165 #else
166 # define VALIDATE 1
167 #endif
168
169 if (!VALIDATE)
170 return;
171
172 struct ir3_validate_ctx *ctx = ralloc_size(NULL, sizeof(*ctx));
173
174 ctx->ir = ir;
175 ctx->defs = _mesa_pointer_set_create(ctx);
176
177 foreach_block (block, &ir->block_list) {
178 foreach_instr (instr, &block->instr_list) {
179 ctx->current_instr = instr;
180 validate_instr(ctx, instr);
181 }
182 }
183
184 ralloc_free(ctx);
185 }
186