1 //===- MIPS.cpp -----------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "InputFiles.h"
10 #include "OutputSections.h"
11 #include "Symbols.h"
12 #include "SyntheticSections.h"
13 #include "Target.h"
14 #include "Thunks.h"
15 #include "lld/Common/ErrorHandler.h"
16 #include "llvm/Object/ELF.h"
17
18 using namespace llvm;
19 using namespace llvm::object;
20 using namespace llvm::ELF;
21 using namespace lld;
22 using namespace lld::elf;
23
24 namespace {
25 template <class ELFT> class MIPS final : public TargetInfo {
26 public:
27 MIPS();
28 uint32_t calcEFlags() const override;
29 RelExpr getRelExpr(RelType type, const Symbol &s,
30 const uint8_t *loc) const override;
31 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
32 RelType getDynRel(RelType type) const override;
33 void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
34 void writePltHeader(uint8_t *buf) const override;
35 void writePlt(uint8_t *buf, const Symbol &sym,
36 uint64_t pltEntryAddr) const override;
37 bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
38 uint64_t branchAddr, const Symbol &s,
39 int64_t a) const override;
40 void relocate(uint8_t *loc, const Relocation &rel,
41 uint64_t val) const override;
42 bool usesOnlyLowPageBits(RelType type) const override;
43 };
44 } // namespace
45
MIPS()46 template <class ELFT> MIPS<ELFT>::MIPS() {
47 gotPltHeaderEntriesNum = 2;
48 defaultMaxPageSize = 65536;
49 gotBaseSymInGotPlt = false;
50 pltEntrySize = 16;
51 pltHeaderSize = 32;
52 copyRel = R_MIPS_COPY;
53 noneRel = R_MIPS_NONE;
54 pltRel = R_MIPS_JUMP_SLOT;
55 needsThunks = true;
56
57 // Set `sigrie 1` as a trap instruction.
58 write32(trapInstr.data(), 0x04170001);
59
60 if (ELFT::Is64Bits) {
61 relativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62 symbolicRel = R_MIPS_64;
63 tlsGotRel = R_MIPS_TLS_TPREL64;
64 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
65 tlsOffsetRel = R_MIPS_TLS_DTPREL64;
66 } else {
67 relativeRel = R_MIPS_REL32;
68 symbolicRel = R_MIPS_32;
69 tlsGotRel = R_MIPS_TLS_TPREL32;
70 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
71 tlsOffsetRel = R_MIPS_TLS_DTPREL32;
72 }
73 }
74
calcEFlags() const75 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
76 return calcMipsEFlags<ELFT>();
77 }
78
79 template <class ELFT>
getRelExpr(RelType type,const Symbol & s,const uint8_t * loc) const80 RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s,
81 const uint8_t *loc) const {
82 // See comment in the calculateMipsRelChain.
83 if (ELFT::Is64Bits || config->mipsN32Abi)
84 type &= 0xff;
85
86 switch (type) {
87 case R_MIPS_JALR:
88 // Older versions of clang would erroneously emit this relocation not only
89 // against functions (loaded from the GOT) but also against data symbols
90 // (e.g. a table of function pointers). When we encounter this, ignore the
91 // relocation and emit a warning instead.
92 if (!s.isFunc() && s.type != STT_NOTYPE) {
93 warn(getErrorLocation(loc) +
94 "found R_MIPS_JALR relocation against non-function symbol " +
95 toString(s) + ". This is invalid and most likely a compiler bug.");
96 return R_NONE;
97 }
98
99 // If the target symbol is not preemptible and is not microMIPS,
100 // it might be possible to replace jalr/jr instruction by bal/b.
101 // It depends on the target symbol's offset.
102 if (!s.isPreemptible && !(s.getVA() & 0x1))
103 return R_PC;
104 return R_NONE;
105 case R_MICROMIPS_JALR:
106 return R_NONE;
107 case R_MIPS_GPREL16:
108 case R_MIPS_GPREL32:
109 case R_MICROMIPS_GPREL16:
110 case R_MICROMIPS_GPREL7_S2:
111 return R_MIPS_GOTREL;
112 case R_MIPS_26:
113 case R_MICROMIPS_26_S1:
114 return R_PLT;
115 case R_MICROMIPS_PC26_S1:
116 return R_PLT_PC;
117 case R_MIPS_HI16:
118 case R_MIPS_LO16:
119 case R_MIPS_HIGHER:
120 case R_MIPS_HIGHEST:
121 case R_MICROMIPS_HI16:
122 case R_MICROMIPS_LO16:
123 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
124 // offset between start of function and 'gp' value which by default
125 // equal to the start of .got section. In that case we consider these
126 // relocations as relative.
127 if (&s == ElfSym::mipsGpDisp)
128 return R_MIPS_GOT_GP_PC;
129 if (&s == ElfSym::mipsLocalGp)
130 return R_MIPS_GOT_GP;
131 LLVM_FALLTHROUGH;
132 case R_MIPS_32:
133 case R_MIPS_64:
134 case R_MIPS_GOT_OFST:
135 case R_MIPS_SUB:
136 case R_MIPS_TLS_DTPREL_HI16:
137 case R_MIPS_TLS_DTPREL_LO16:
138 case R_MIPS_TLS_DTPREL32:
139 case R_MIPS_TLS_DTPREL64:
140 case R_MICROMIPS_TLS_DTPREL_HI16:
141 case R_MICROMIPS_TLS_DTPREL_LO16:
142 return R_ABS;
143 case R_MIPS_TLS_TPREL_HI16:
144 case R_MIPS_TLS_TPREL_LO16:
145 case R_MIPS_TLS_TPREL32:
146 case R_MIPS_TLS_TPREL64:
147 case R_MICROMIPS_TLS_TPREL_HI16:
148 case R_MICROMIPS_TLS_TPREL_LO16:
149 return R_TLS;
150 case R_MIPS_PC32:
151 case R_MIPS_PC16:
152 case R_MIPS_PC19_S2:
153 case R_MIPS_PC21_S2:
154 case R_MIPS_PC26_S2:
155 case R_MIPS_PCHI16:
156 case R_MIPS_PCLO16:
157 case R_MICROMIPS_PC7_S1:
158 case R_MICROMIPS_PC10_S1:
159 case R_MICROMIPS_PC16_S1:
160 case R_MICROMIPS_PC18_S3:
161 case R_MICROMIPS_PC19_S2:
162 case R_MICROMIPS_PC23_S2:
163 case R_MICROMIPS_PC21_S1:
164 return R_PC;
165 case R_MIPS_GOT16:
166 case R_MICROMIPS_GOT16:
167 if (s.isLocal())
168 return R_MIPS_GOT_LOCAL_PAGE;
169 LLVM_FALLTHROUGH;
170 case R_MIPS_CALL16:
171 case R_MIPS_GOT_DISP:
172 case R_MIPS_TLS_GOTTPREL:
173 case R_MICROMIPS_CALL16:
174 case R_MICROMIPS_TLS_GOTTPREL:
175 return R_MIPS_GOT_OFF;
176 case R_MIPS_CALL_HI16:
177 case R_MIPS_CALL_LO16:
178 case R_MIPS_GOT_HI16:
179 case R_MIPS_GOT_LO16:
180 case R_MICROMIPS_CALL_HI16:
181 case R_MICROMIPS_CALL_LO16:
182 case R_MICROMIPS_GOT_HI16:
183 case R_MICROMIPS_GOT_LO16:
184 return R_MIPS_GOT_OFF32;
185 case R_MIPS_GOT_PAGE:
186 return R_MIPS_GOT_LOCAL_PAGE;
187 case R_MIPS_TLS_GD:
188 case R_MICROMIPS_TLS_GD:
189 return R_MIPS_TLSGD;
190 case R_MIPS_TLS_LDM:
191 case R_MICROMIPS_TLS_LDM:
192 return R_MIPS_TLSLD;
193 case R_MIPS_NONE:
194 return R_NONE;
195 default:
196 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
197 ") against symbol " + toString(s));
198 return R_NONE;
199 }
200 }
201
getDynRel(RelType type) const202 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType type) const {
203 if (type == symbolicRel)
204 return type;
205 return R_MIPS_NONE;
206 }
207
208 template <class ELFT>
writeGotPlt(uint8_t * buf,const Symbol &) const209 void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const {
210 uint64_t va = in.plt->getVA();
211 if (isMicroMips())
212 va |= 1;
213 write32(buf, va);
214 }
215
readShuffle(const uint8_t * loc)216 template <endianness E> static uint32_t readShuffle(const uint8_t *loc) {
217 // The major opcode of a microMIPS instruction needs to appear
218 // in the first 16-bit word (lowest address) for efficient hardware
219 // decode so that it knows if the instruction is 16-bit or 32-bit
220 // as early as possible. To do so, little-endian binaries keep 16-bit
221 // words in a big-endian order. That is why we have to swap these
222 // words to get a correct value.
223 uint32_t v = read32(loc);
224 if (E == support::little)
225 return (v << 16) | (v >> 16);
226 return v;
227 }
228
writeValue(uint8_t * loc,uint64_t v,uint8_t bitsSize,uint8_t shift)229 static void writeValue(uint8_t *loc, uint64_t v, uint8_t bitsSize,
230 uint8_t shift) {
231 uint32_t instr = read32(loc);
232 uint32_t mask = 0xffffffff >> (32 - bitsSize);
233 uint32_t data = (instr & ~mask) | ((v >> shift) & mask);
234 write32(loc, data);
235 }
236
237 template <endianness E>
writeShuffleValue(uint8_t * loc,uint64_t v,uint8_t bitsSize,uint8_t shift)238 static void writeShuffleValue(uint8_t *loc, uint64_t v, uint8_t bitsSize,
239 uint8_t shift) {
240 // See comments in readShuffle for purpose of this code.
241 uint16_t *words = (uint16_t *)loc;
242 if (E == support::little)
243 std::swap(words[0], words[1]);
244
245 writeValue(loc, v, bitsSize, shift);
246
247 if (E == support::little)
248 std::swap(words[0], words[1]);
249 }
250
251 template <endianness E>
writeMicroRelocation16(uint8_t * loc,uint64_t v,uint8_t bitsSize,uint8_t shift)252 static void writeMicroRelocation16(uint8_t *loc, uint64_t v, uint8_t bitsSize,
253 uint8_t shift) {
254 uint16_t instr = read16(loc);
255 uint16_t mask = 0xffff >> (16 - bitsSize);
256 uint16_t data = (instr & ~mask) | ((v >> shift) & mask);
257 write16(loc, data);
258 }
259
writePltHeader(uint8_t * buf) const260 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const {
261 if (isMicroMips()) {
262 uint64_t gotPlt = in.gotPlt->getVA();
263 uint64_t plt = in.plt->getVA();
264 // Overwrite trap instructions written by Writer::writeTrapInstr.
265 memset(buf, 0, pltHeaderSize);
266
267 write16(buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - .
268 write16(buf + 4, 0xff23); // lw $25, 0($3)
269 write16(buf + 8, 0x0535); // subu16 $2, $2, $3
270 write16(buf + 10, 0x2525); // srl16 $2, $2, 2
271 write16(buf + 12, 0x3302); // addiu $24, $2, -2
272 write16(buf + 14, 0xfffe);
273 write16(buf + 16, 0x0dff); // move $15, $31
274 if (isMipsR6()) {
275 write16(buf + 18, 0x0f83); // move $28, $3
276 write16(buf + 20, 0x472b); // jalrc $25
277 write16(buf + 22, 0x0c00); // nop
278 relocateNoSym(buf, R_MICROMIPS_PC19_S2, gotPlt - plt);
279 } else {
280 write16(buf + 18, 0x45f9); // jalrc $25
281 write16(buf + 20, 0x0f83); // move $28, $3
282 write16(buf + 22, 0x0c00); // nop
283 relocateNoSym(buf, R_MICROMIPS_PC23_S2, gotPlt - plt);
284 }
285 return;
286 }
287
288 if (config->mipsN32Abi) {
289 write32(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0])
290 write32(buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14)
291 write32(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0])
292 write32(buf + 12, 0x030ec023); // subu $24, $24, $14
293 write32(buf + 16, 0x03e07825); // move $15, $31
294 write32(buf + 20, 0x0018c082); // srl $24, $24, 2
295 } else if (ELFT::Is64Bits) {
296 write32(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0])
297 write32(buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14)
298 write32(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0])
299 write32(buf + 12, 0x030ec023); // subu $24, $24, $14
300 write32(buf + 16, 0x03e07825); // move $15, $31
301 write32(buf + 20, 0x0018c0c2); // srl $24, $24, 3
302 } else {
303 write32(buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0])
304 write32(buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28)
305 write32(buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0])
306 write32(buf + 12, 0x031cc023); // subu $24, $24, $28
307 write32(buf + 16, 0x03e07825); // move $15, $31
308 write32(buf + 20, 0x0018c082); // srl $24, $24, 2
309 }
310
311 uint32_t jalrInst = config->zHazardplt ? 0x0320fc09 : 0x0320f809;
312 write32(buf + 24, jalrInst); // jalr.hb $25 or jalr $25
313 write32(buf + 28, 0x2718fffe); // subu $24, $24, 2
314
315 uint64_t gotPlt = in.gotPlt->getVA();
316 writeValue(buf, gotPlt + 0x8000, 16, 16);
317 writeValue(buf + 4, gotPlt, 16, 0);
318 writeValue(buf + 8, gotPlt, 16, 0);
319 }
320
321 template <class ELFT>
writePlt(uint8_t * buf,const Symbol & sym,uint64_t pltEntryAddr) const322 void MIPS<ELFT>::writePlt(uint8_t *buf, const Symbol &sym,
323 uint64_t pltEntryAddr) const {
324 uint64_t gotPltEntryAddr = sym.getGotPltVA();
325 if (isMicroMips()) {
326 // Overwrite trap instructions written by Writer::writeTrapInstr.
327 memset(buf, 0, pltEntrySize);
328
329 if (isMipsR6()) {
330 write16(buf, 0x7840); // addiupc $2, (GOTPLT) - .
331 write16(buf + 4, 0xff22); // lw $25, 0($2)
332 write16(buf + 8, 0x0f02); // move $24, $2
333 write16(buf + 10, 0x4723); // jrc $25 / jr16 $25
334 relocateNoSym(buf, R_MICROMIPS_PC19_S2, gotPltEntryAddr - pltEntryAddr);
335 } else {
336 write16(buf, 0x7900); // addiupc $2, (GOTPLT) - .
337 write16(buf + 4, 0xff22); // lw $25, 0($2)
338 write16(buf + 8, 0x4599); // jrc $25 / jr16 $25
339 write16(buf + 10, 0x0f02); // move $24, $2
340 relocateNoSym(buf, R_MICROMIPS_PC23_S2, gotPltEntryAddr - pltEntryAddr);
341 }
342 return;
343 }
344
345 uint32_t loadInst = ELFT::Is64Bits ? 0xddf90000 : 0x8df90000;
346 uint32_t jrInst = isMipsR6() ? (config->zHazardplt ? 0x03200409 : 0x03200009)
347 : (config->zHazardplt ? 0x03200408 : 0x03200008);
348 uint32_t addInst = ELFT::Is64Bits ? 0x65f80000 : 0x25f80000;
349
350 write32(buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry)
351 write32(buf + 4, loadInst); // l[wd] $25, %lo(.got.plt entry)($15)
352 write32(buf + 8, jrInst); // jr $25 / jr.hb $25
353 write32(buf + 12, addInst); // [d]addiu $24, $15, %lo(.got.plt entry)
354 writeValue(buf, gotPltEntryAddr + 0x8000, 16, 16);
355 writeValue(buf + 4, gotPltEntryAddr, 16, 0);
356 writeValue(buf + 12, gotPltEntryAddr, 16, 0);
357 }
358
359 template <class ELFT>
needsThunk(RelExpr expr,RelType type,const InputFile * file,uint64_t branchAddr,const Symbol & s,int64_t) const360 bool MIPS<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file,
361 uint64_t branchAddr, const Symbol &s,
362 int64_t /*a*/) const {
363 // Any MIPS PIC code function is invoked with its address in register $t9.
364 // So if we have a branch instruction from non-PIC code to the PIC one
365 // we cannot make the jump directly and need to create a small stubs
366 // to save the target function address.
367 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
368 if (type != R_MIPS_26 && type != R_MIPS_PC26_S2 &&
369 type != R_MICROMIPS_26_S1 && type != R_MICROMIPS_PC26_S1)
370 return false;
371 auto *f = dyn_cast_or_null<ObjFile<ELFT>>(file);
372 if (!f)
373 return false;
374 // If current file has PIC code, LA25 stub is not required.
375 if (f->getObj().getHeader().e_flags & EF_MIPS_PIC)
376 return false;
377 auto *d = dyn_cast<Defined>(&s);
378 // LA25 is required if target file has PIC code
379 // or target symbol is a PIC symbol.
380 return d && isMipsPIC<ELFT>(d);
381 }
382
383 template <class ELFT>
getImplicitAddend(const uint8_t * buf,RelType type) const384 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const {
385 const endianness e = ELFT::TargetEndianness;
386 switch (type) {
387 case R_MIPS_32:
388 case R_MIPS_GPREL32:
389 case R_MIPS_TLS_DTPREL32:
390 case R_MIPS_TLS_TPREL32:
391 return SignExtend64<32>(read32(buf));
392 case R_MIPS_26:
393 // FIXME (simon): If the relocation target symbol is not a PLT entry
394 // we should use another expression for calculation:
395 // ((A << 2) | (P & 0xf0000000)) >> 2
396 return SignExtend64<28>(read32(buf) << 2);
397 case R_MIPS_GOT16:
398 case R_MIPS_HI16:
399 case R_MIPS_PCHI16:
400 return SignExtend64<16>(read32(buf)) << 16;
401 case R_MIPS_GPREL16:
402 case R_MIPS_LO16:
403 case R_MIPS_PCLO16:
404 case R_MIPS_TLS_DTPREL_HI16:
405 case R_MIPS_TLS_DTPREL_LO16:
406 case R_MIPS_TLS_TPREL_HI16:
407 case R_MIPS_TLS_TPREL_LO16:
408 return SignExtend64<16>(read32(buf));
409 case R_MICROMIPS_GOT16:
410 case R_MICROMIPS_HI16:
411 return SignExtend64<16>(readShuffle<e>(buf)) << 16;
412 case R_MICROMIPS_GPREL16:
413 case R_MICROMIPS_LO16:
414 case R_MICROMIPS_TLS_DTPREL_HI16:
415 case R_MICROMIPS_TLS_DTPREL_LO16:
416 case R_MICROMIPS_TLS_TPREL_HI16:
417 case R_MICROMIPS_TLS_TPREL_LO16:
418 return SignExtend64<16>(readShuffle<e>(buf));
419 case R_MICROMIPS_GPREL7_S2:
420 return SignExtend64<9>(readShuffle<e>(buf) << 2);
421 case R_MIPS_PC16:
422 return SignExtend64<18>(read32(buf) << 2);
423 case R_MIPS_PC19_S2:
424 return SignExtend64<21>(read32(buf) << 2);
425 case R_MIPS_PC21_S2:
426 return SignExtend64<23>(read32(buf) << 2);
427 case R_MIPS_PC26_S2:
428 return SignExtend64<28>(read32(buf) << 2);
429 case R_MIPS_PC32:
430 return SignExtend64<32>(read32(buf));
431 case R_MICROMIPS_26_S1:
432 return SignExtend64<27>(readShuffle<e>(buf) << 1);
433 case R_MICROMIPS_PC7_S1:
434 return SignExtend64<8>(read16(buf) << 1);
435 case R_MICROMIPS_PC10_S1:
436 return SignExtend64<11>(read16(buf) << 1);
437 case R_MICROMIPS_PC16_S1:
438 return SignExtend64<17>(readShuffle<e>(buf) << 1);
439 case R_MICROMIPS_PC18_S3:
440 return SignExtend64<21>(readShuffle<e>(buf) << 3);
441 case R_MICROMIPS_PC19_S2:
442 return SignExtend64<21>(readShuffle<e>(buf) << 2);
443 case R_MICROMIPS_PC21_S1:
444 return SignExtend64<22>(readShuffle<e>(buf) << 1);
445 case R_MICROMIPS_PC23_S2:
446 return SignExtend64<25>(readShuffle<e>(buf) << 2);
447 case R_MICROMIPS_PC26_S1:
448 return SignExtend64<27>(readShuffle<e>(buf) << 1);
449 default:
450 return 0;
451 }
452 }
453
454 static std::pair<uint32_t, uint64_t>
calculateMipsRelChain(uint8_t * loc,RelType type,uint64_t val)455 calculateMipsRelChain(uint8_t *loc, RelType type, uint64_t val) {
456 // MIPS N64 ABI packs multiple relocations into the single relocation
457 // record. In general, all up to three relocations can have arbitrary
458 // types. In fact, Clang and GCC uses only a few combinations. For now,
459 // we support two of them. That is allow to pass at least all LLVM
460 // test suite cases.
461 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
462 // <any relocation> / R_MIPS_64 / R_MIPS_NONE
463 // The first relocation is a 'real' relocation which is calculated
464 // using the corresponding symbol's value. The second and the third
465 // relocations used to modify result of the first one: extend it to
466 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
467 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
468 RelType type2 = (type >> 8) & 0xff;
469 RelType type3 = (type >> 16) & 0xff;
470 if (type2 == R_MIPS_NONE && type3 == R_MIPS_NONE)
471 return std::make_pair(type, val);
472 if (type2 == R_MIPS_64 && type3 == R_MIPS_NONE)
473 return std::make_pair(type2, val);
474 if (type2 == R_MIPS_SUB && (type3 == R_MIPS_HI16 || type3 == R_MIPS_LO16))
475 return std::make_pair(type3, -val);
476 error(getErrorLocation(loc) + "unsupported relocations combination " +
477 Twine(type));
478 return std::make_pair(type & 0xff, val);
479 }
480
isBranchReloc(RelType type)481 static bool isBranchReloc(RelType type) {
482 return type == R_MIPS_26 || type == R_MIPS_PC26_S2 ||
483 type == R_MIPS_PC21_S2 || type == R_MIPS_PC16;
484 }
485
isMicroBranchReloc(RelType type)486 static bool isMicroBranchReloc(RelType type) {
487 return type == R_MICROMIPS_26_S1 || type == R_MICROMIPS_PC16_S1 ||
488 type == R_MICROMIPS_PC10_S1 || type == R_MICROMIPS_PC7_S1;
489 }
490
491 template <class ELFT>
fixupCrossModeJump(uint8_t * loc,RelType type,uint64_t val)492 static uint64_t fixupCrossModeJump(uint8_t *loc, RelType type, uint64_t val) {
493 // Here we need to detect jump/branch from regular MIPS code
494 // to a microMIPS target and vice versa. In that cases jump
495 // instructions need to be replaced by their "cross-mode"
496 // equivalents.
497 const endianness e = ELFT::TargetEndianness;
498 bool isMicroTgt = val & 0x1;
499 bool isCrossJump = (isMicroTgt && isBranchReloc(type)) ||
500 (!isMicroTgt && isMicroBranchReloc(type));
501 if (!isCrossJump)
502 return val;
503
504 switch (type) {
505 case R_MIPS_26: {
506 uint32_t inst = read32(loc) >> 26;
507 if (inst == 0x3 || inst == 0x1d) { // JAL or JALX
508 writeValue(loc, 0x1d << 26, 32, 0);
509 return val;
510 }
511 break;
512 }
513 case R_MICROMIPS_26_S1: {
514 uint32_t inst = readShuffle<e>(loc) >> 26;
515 if (inst == 0x3d || inst == 0x3c) { // JAL32 or JALX32
516 val >>= 1;
517 writeShuffleValue<e>(loc, 0x3c << 26, 32, 0);
518 return val;
519 }
520 break;
521 }
522 case R_MIPS_PC26_S2:
523 case R_MIPS_PC21_S2:
524 case R_MIPS_PC16:
525 case R_MICROMIPS_PC16_S1:
526 case R_MICROMIPS_PC10_S1:
527 case R_MICROMIPS_PC7_S1:
528 // FIXME (simon): Support valid branch relocations.
529 break;
530 default:
531 llvm_unreachable("unexpected jump/branch relocation");
532 }
533
534 error(getErrorLocation(loc) +
535 "unsupported jump/branch instruction between ISA modes referenced by " +
536 toString(type) + " relocation");
537 return val;
538 }
539
540 template <class ELFT>
relocate(uint8_t * loc,const Relocation & rel,uint64_t val) const541 void MIPS<ELFT>::relocate(uint8_t *loc, const Relocation &rel,
542 uint64_t val) const {
543 const endianness e = ELFT::TargetEndianness;
544 RelType type = rel.type;
545
546 if (ELFT::Is64Bits || config->mipsN32Abi)
547 std::tie(type, val) = calculateMipsRelChain(loc, type, val);
548
549 // Detect cross-mode jump/branch and fix instruction.
550 val = fixupCrossModeJump<ELFT>(loc, type, val);
551
552 // Thread pointer and DRP offsets from the start of TLS data area.
553 // https://www.linux-mips.org/wiki/NPTL
554 if (type == R_MIPS_TLS_DTPREL_HI16 || type == R_MIPS_TLS_DTPREL_LO16 ||
555 type == R_MIPS_TLS_DTPREL32 || type == R_MIPS_TLS_DTPREL64 ||
556 type == R_MICROMIPS_TLS_DTPREL_HI16 ||
557 type == R_MICROMIPS_TLS_DTPREL_LO16) {
558 val -= 0x8000;
559 }
560
561 switch (type) {
562 case R_MIPS_32:
563 case R_MIPS_GPREL32:
564 case R_MIPS_TLS_DTPREL32:
565 case R_MIPS_TLS_TPREL32:
566 write32(loc, val);
567 break;
568 case R_MIPS_64:
569 case R_MIPS_TLS_DTPREL64:
570 case R_MIPS_TLS_TPREL64:
571 write64(loc, val);
572 break;
573 case R_MIPS_26:
574 writeValue(loc, val, 26, 2);
575 break;
576 case R_MIPS_GOT16:
577 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
578 // is updated addend (not a GOT index). In that case write high 16 bits
579 // to store a correct addend value.
580 if (config->relocatable) {
581 writeValue(loc, val + 0x8000, 16, 16);
582 } else {
583 checkInt(loc, val, 16, rel);
584 writeValue(loc, val, 16, 0);
585 }
586 break;
587 case R_MICROMIPS_GOT16:
588 if (config->relocatable) {
589 writeShuffleValue<e>(loc, val + 0x8000, 16, 16);
590 } else {
591 checkInt(loc, val, 16, rel);
592 writeShuffleValue<e>(loc, val, 16, 0);
593 }
594 break;
595 case R_MIPS_CALL16:
596 case R_MIPS_GOT_DISP:
597 case R_MIPS_GOT_PAGE:
598 case R_MIPS_GPREL16:
599 case R_MIPS_TLS_GD:
600 case R_MIPS_TLS_GOTTPREL:
601 case R_MIPS_TLS_LDM:
602 checkInt(loc, val, 16, rel);
603 LLVM_FALLTHROUGH;
604 case R_MIPS_CALL_LO16:
605 case R_MIPS_GOT_LO16:
606 case R_MIPS_GOT_OFST:
607 case R_MIPS_LO16:
608 case R_MIPS_PCLO16:
609 case R_MIPS_TLS_DTPREL_LO16:
610 case R_MIPS_TLS_TPREL_LO16:
611 writeValue(loc, val, 16, 0);
612 break;
613 case R_MICROMIPS_GPREL16:
614 case R_MICROMIPS_TLS_GD:
615 case R_MICROMIPS_TLS_LDM:
616 checkInt(loc, val, 16, rel);
617 writeShuffleValue<e>(loc, val, 16, 0);
618 break;
619 case R_MICROMIPS_CALL16:
620 case R_MICROMIPS_CALL_LO16:
621 case R_MICROMIPS_LO16:
622 case R_MICROMIPS_TLS_DTPREL_LO16:
623 case R_MICROMIPS_TLS_GOTTPREL:
624 case R_MICROMIPS_TLS_TPREL_LO16:
625 writeShuffleValue<e>(loc, val, 16, 0);
626 break;
627 case R_MICROMIPS_GPREL7_S2:
628 checkInt(loc, val, 7, rel);
629 writeShuffleValue<e>(loc, val, 7, 2);
630 break;
631 case R_MIPS_CALL_HI16:
632 case R_MIPS_GOT_HI16:
633 case R_MIPS_HI16:
634 case R_MIPS_PCHI16:
635 case R_MIPS_TLS_DTPREL_HI16:
636 case R_MIPS_TLS_TPREL_HI16:
637 writeValue(loc, val + 0x8000, 16, 16);
638 break;
639 case R_MICROMIPS_CALL_HI16:
640 case R_MICROMIPS_GOT_HI16:
641 case R_MICROMIPS_HI16:
642 case R_MICROMIPS_TLS_DTPREL_HI16:
643 case R_MICROMIPS_TLS_TPREL_HI16:
644 writeShuffleValue<e>(loc, val + 0x8000, 16, 16);
645 break;
646 case R_MIPS_HIGHER:
647 writeValue(loc, val + 0x80008000, 16, 32);
648 break;
649 case R_MIPS_HIGHEST:
650 writeValue(loc, val + 0x800080008000, 16, 48);
651 break;
652 case R_MIPS_JALR:
653 val -= 4;
654 // Replace jalr/jr instructions by bal/b if the target
655 // offset fits into the 18-bit range.
656 if (isInt<18>(val)) {
657 switch (read32(loc)) {
658 case 0x0320f809: // jalr $25 => bal sym
659 write32(loc, 0x04110000 | ((val >> 2) & 0xffff));
660 break;
661 case 0x03200008: // jr $25 => b sym
662 write32(loc, 0x10000000 | ((val >> 2) & 0xffff));
663 break;
664 }
665 }
666 break;
667 case R_MICROMIPS_JALR:
668 // Ignore this optimization relocation for now
669 break;
670 case R_MIPS_PC16:
671 checkAlignment(loc, val, 4, rel);
672 checkInt(loc, val, 18, rel);
673 writeValue(loc, val, 16, 2);
674 break;
675 case R_MIPS_PC19_S2:
676 checkAlignment(loc, val, 4, rel);
677 checkInt(loc, val, 21, rel);
678 writeValue(loc, val, 19, 2);
679 break;
680 case R_MIPS_PC21_S2:
681 checkAlignment(loc, val, 4, rel);
682 checkInt(loc, val, 23, rel);
683 writeValue(loc, val, 21, 2);
684 break;
685 case R_MIPS_PC26_S2:
686 checkAlignment(loc, val, 4, rel);
687 checkInt(loc, val, 28, rel);
688 writeValue(loc, val, 26, 2);
689 break;
690 case R_MIPS_PC32:
691 writeValue(loc, val, 32, 0);
692 break;
693 case R_MICROMIPS_26_S1:
694 case R_MICROMIPS_PC26_S1:
695 checkInt(loc, val, 27, rel);
696 writeShuffleValue<e>(loc, val, 26, 1);
697 break;
698 case R_MICROMIPS_PC7_S1:
699 checkInt(loc, val, 8, rel);
700 writeMicroRelocation16<e>(loc, val, 7, 1);
701 break;
702 case R_MICROMIPS_PC10_S1:
703 checkInt(loc, val, 11, rel);
704 writeMicroRelocation16<e>(loc, val, 10, 1);
705 break;
706 case R_MICROMIPS_PC16_S1:
707 checkInt(loc, val, 17, rel);
708 writeShuffleValue<e>(loc, val, 16, 1);
709 break;
710 case R_MICROMIPS_PC18_S3:
711 checkInt(loc, val, 21, rel);
712 writeShuffleValue<e>(loc, val, 18, 3);
713 break;
714 case R_MICROMIPS_PC19_S2:
715 checkInt(loc, val, 21, rel);
716 writeShuffleValue<e>(loc, val, 19, 2);
717 break;
718 case R_MICROMIPS_PC21_S1:
719 checkInt(loc, val, 22, rel);
720 writeShuffleValue<e>(loc, val, 21, 1);
721 break;
722 case R_MICROMIPS_PC23_S2:
723 checkInt(loc, val, 25, rel);
724 writeShuffleValue<e>(loc, val, 23, 2);
725 break;
726 default:
727 llvm_unreachable("unknown relocation");
728 }
729 }
730
usesOnlyLowPageBits(RelType type) const731 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType type) const {
732 return type == R_MIPS_LO16 || type == R_MIPS_GOT_OFST ||
733 type == R_MICROMIPS_LO16;
734 }
735
736 // Return true if the symbol is a PIC function.
isMipsPIC(const Defined * sym)737 template <class ELFT> bool elf::isMipsPIC(const Defined *sym) {
738 if (!sym->isFunc())
739 return false;
740
741 if (sym->stOther & STO_MIPS_PIC)
742 return true;
743
744 if (!sym->section)
745 return false;
746
747 ObjFile<ELFT> *file =
748 cast<InputSectionBase>(sym->section)->template getFile<ELFT>();
749 if (!file)
750 return false;
751
752 return file->getObj().getHeader().e_flags & EF_MIPS_PIC;
753 }
754
getMipsTargetInfo()755 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
756 static MIPS<ELFT> target;
757 return ⌖
758 }
759
760 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
761 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
762 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
763 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
764
765 template bool elf::isMipsPIC<ELF32LE>(const Defined *);
766 template bool elf::isMipsPIC<ELF32BE>(const Defined *);
767 template bool elf::isMipsPIC<ELF64LE>(const Defined *);
768 template bool elf::isMipsPIC<ELF64BE>(const Defined *);
769