1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineOperand.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/IR/IntrinsicInst.h"
25 #include "llvm/IR/IntrinsicsARM.h"
26 #include <array>
27 #include <cstdint>
28
29 #define GET_INSTRINFO_HEADER
30 #include "ARMGenInstrInfo.inc"
31
32 namespace llvm {
33
34 class ARMBaseRegisterInfo;
35 class ARMSubtarget;
36
37 class ARMBaseInstrInfo : public ARMGenInstrInfo {
38 const ARMSubtarget &Subtarget;
39
40 protected:
41 // Can be only subclassed.
42 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
43
44 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
45 unsigned LoadImmOpc, unsigned LoadOpc) const;
46
47 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
48 /// and \p DefIdx.
49 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
50 /// the list is modeled as <Reg:SubReg, SubIdx>.
51 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
52 /// two elements:
53 /// - %1:sub1, sub0
54 /// - %2<:0>, sub1
55 ///
56 /// \returns true if it is possible to build such an input sequence
57 /// with the pair \p MI, \p DefIdx. False otherwise.
58 ///
59 /// \pre MI.isRegSequenceLike().
60 bool getRegSequenceLikeInputs(
61 const MachineInstr &MI, unsigned DefIdx,
62 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
63
64 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
65 /// and \p DefIdx.
66 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
67 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
68 /// - %1:sub1, sub0
69 ///
70 /// \returns true if it is possible to build such an input sequence
71 /// with the pair \p MI, \p DefIdx. False otherwise.
72 ///
73 /// \pre MI.isExtractSubregLike().
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
75 RegSubRegPairAndIdx &InputReg) const override;
76
77 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
78 /// and \p DefIdx.
79 /// \p [out] BaseReg and \p [out] InsertedReg contain
80 /// the equivalent inputs of INSERT_SUBREG.
81 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
82 /// - BaseReg: %0:sub0
83 /// - InsertedReg: %1:sub1, sub3
84 ///
85 /// \returns true if it is possible to build such an input sequence
86 /// with the pair \p MI, \p DefIdx. False otherwise.
87 ///
88 /// \pre MI.isInsertSubregLike().
89 bool
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
91 RegSubRegPair &BaseReg,
92 RegSubRegPairAndIdx &InsertedReg) const override;
93
94 /// Commutes the operands in the given instruction.
95 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
96 ///
97 /// Do not call this method for a non-commutable instruction or for
98 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
99 /// Even though the instruction is commutable, the method may still
100 /// fail to commute the operands, null pointer is returned in such cases.
101 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
102 unsigned OpIdx1,
103 unsigned OpIdx2) const override;
104 /// If the specific machine instruction is an instruction that moves/copies
105 /// value from one register to another register return destination and source
106 /// registers as machine operands.
107 Optional<DestSourcePair>
108 isCopyInstrImpl(const MachineInstr &MI) const override;
109
110 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
111 /// enhance debug entry value descriptions for ARM targets.
112 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
113 Register Reg) const override;
114
115 public:
116 // Return whether the target has an explicit NOP encoding.
117 bool hasNOP() const;
118
119 // Return the non-pre/post incrementing version of 'Opc'. Return 0
120 // if there is not such an opcode.
121 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
122
123 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
124 MachineInstr &MI,
125 LiveVariables *LV) const override;
126
127 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
getSubtarget()128 const ARMSubtarget &getSubtarget() const { return Subtarget; }
129
130 ScheduleHazardRecognizer *
131 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
132 const ScheduleDAG *DAG) const override;
133
134 ScheduleHazardRecognizer *
135 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
136 const ScheduleDAG *DAG) const override;
137
138 // Branch analysis.
139 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
140 MachineBasicBlock *&FBB,
141 SmallVectorImpl<MachineOperand> &Cond,
142 bool AllowModify = false) const override;
143 unsigned removeBranch(MachineBasicBlock &MBB,
144 int *BytesRemoved = nullptr) const override;
145 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
146 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
147 const DebugLoc &DL,
148 int *BytesAdded = nullptr) const override;
149
150 bool
151 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
152
153 // Predication support.
154 bool isPredicated(const MachineInstr &MI) const override;
155
156 // MIR printer helper function to annotate Operands with a comment.
157 std::string
158 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
159 unsigned OpIdx,
160 const TargetRegisterInfo *TRI) const override;
161
getPredicate(const MachineInstr & MI)162 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
163 int PIdx = MI.findFirstPredOperandIdx();
164 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
165 : ARMCC::AL;
166 }
167
168 bool PredicateInstruction(MachineInstr &MI,
169 ArrayRef<MachineOperand> Pred) const override;
170
171 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
172 ArrayRef<MachineOperand> Pred2) const override;
173
174 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
175 bool SkipDead) const override;
176
177 bool isPredicable(const MachineInstr &MI) const override;
178
179 // CPSR defined in instruction
180 static bool isCPSRDefined(const MachineInstr &MI);
181
182 /// GetInstSize - Returns the size of the specified MachineInstr.
183 ///
184 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
185
186 unsigned isLoadFromStackSlot(const MachineInstr &MI,
187 int &FrameIndex) const override;
188 unsigned isStoreToStackSlot(const MachineInstr &MI,
189 int &FrameIndex) const override;
190 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
191 int &FrameIndex) const override;
192 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
193 int &FrameIndex) const override;
194
195 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
196 unsigned SrcReg, bool KillSrc,
197 const ARMSubtarget &Subtarget) const;
198 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
199 unsigned DestReg, bool KillSrc,
200 const ARMSubtarget &Subtarget) const;
201
202 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
203 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
204 bool KillSrc) const override;
205
206 void storeRegToStackSlot(MachineBasicBlock &MBB,
207 MachineBasicBlock::iterator MBBI,
208 Register SrcReg, bool isKill, int FrameIndex,
209 const TargetRegisterClass *RC,
210 const TargetRegisterInfo *TRI) const override;
211
212 void loadRegFromStackSlot(MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator MBBI,
214 Register DestReg, int FrameIndex,
215 const TargetRegisterClass *RC,
216 const TargetRegisterInfo *TRI) const override;
217
218 bool expandPostRAPseudo(MachineInstr &MI) const override;
219
220 bool shouldSink(const MachineInstr &MI) const override;
221
222 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
223 Register DestReg, unsigned SubIdx,
224 const MachineInstr &Orig,
225 const TargetRegisterInfo &TRI) const override;
226
227 MachineInstr &
228 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
229 const MachineInstr &Orig) const override;
230
231 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
232 unsigned SubIdx, unsigned State,
233 const TargetRegisterInfo *TRI) const;
234
235 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
236 const MachineRegisterInfo *MRI) const override;
237
238 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
239 /// determine if two loads are loading from the same base address. It should
240 /// only return true if the base pointers are the same and the only
241 /// differences between the two addresses is the offset. It also returns the
242 /// offsets by reference.
243 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
244 int64_t &Offset2) const override;
245
246 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
247 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
248 /// should be scheduled togther. On some targets if two loads are loading from
249 /// addresses in the same cache line, it's better if they are scheduled
250 /// together. This function takes two integers that represent the load offsets
251 /// from the common base address. It returns true if it decides it's desirable
252 /// to schedule the two loads together. "NumLoads" is the number of loads that
253 /// have already been scheduled after Load1.
254 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
255 int64_t Offset1, int64_t Offset2,
256 unsigned NumLoads) const override;
257
258 bool isSchedulingBoundary(const MachineInstr &MI,
259 const MachineBasicBlock *MBB,
260 const MachineFunction &MF) const override;
261
262 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
263 unsigned NumCycles, unsigned ExtraPredCycles,
264 BranchProbability Probability) const override;
265
266 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
267 unsigned ExtraT, MachineBasicBlock &FMBB,
268 unsigned NumF, unsigned ExtraF,
269 BranchProbability Probability) const override;
270
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,BranchProbability Probability)271 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
272 BranchProbability Probability) const override {
273 return NumCycles == 1;
274 }
275
276 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,
277 unsigned NumInsts) const override;
278 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
279
280 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
281 MachineBasicBlock &FMBB) const override;
282
283 /// analyzeCompare - For a comparison instruction, return the source registers
284 /// in SrcReg and SrcReg2 if having two register operands, and the value it
285 /// compares against in CmpValue. Return true if the comparison instruction
286 /// can be analyzed.
287 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
288 Register &SrcReg2, int &CmpMask,
289 int &CmpValue) const override;
290
291 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
292 /// that we can remove a "comparison with zero"; Remove a redundant CMP
293 /// instruction if the flags can be updated in the same way by an earlier
294 /// instruction such as SUB.
295 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
296 Register SrcReg2, int CmpMask, int CmpValue,
297 const MachineRegisterInfo *MRI) const override;
298
299 bool analyzeSelect(const MachineInstr &MI,
300 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
301 unsigned &FalseOp, bool &Optimizable) const override;
302
303 MachineInstr *optimizeSelect(MachineInstr &MI,
304 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
305 bool) const override;
306
307 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
308 /// instruction, try to fold the immediate into the use instruction.
309 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
310 MachineRegisterInfo *MRI) const override;
311
312 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
313 const MachineInstr &MI) const override;
314
315 int getOperandLatency(const InstrItineraryData *ItinData,
316 const MachineInstr &DefMI, unsigned DefIdx,
317 const MachineInstr &UseMI,
318 unsigned UseIdx) const override;
319 int getOperandLatency(const InstrItineraryData *ItinData,
320 SDNode *DefNode, unsigned DefIdx,
321 SDNode *UseNode, unsigned UseIdx) const override;
322
323 /// VFP/NEON execution domains.
324 std::pair<uint16_t, uint16_t>
325 getExecutionDomain(const MachineInstr &MI) const override;
326 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
327
328 unsigned
329 getPartialRegUpdateClearance(const MachineInstr &, unsigned,
330 const TargetRegisterInfo *) const override;
331 void breakPartialRegDependency(MachineInstr &, unsigned,
332 const TargetRegisterInfo *TRI) const override;
333
334 /// Get the number of addresses by LDM or VLDM or zero for unknown.
335 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
336
337 std::pair<unsigned, unsigned>
338 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
339 ArrayRef<std::pair<unsigned, const char *>>
340 getSerializableDirectMachineOperandTargetFlags() const override;
341 ArrayRef<std::pair<unsigned, const char *>>
342 getSerializableBitmaskMachineOperandTargetFlags() const override;
343
344 /// ARM supports the MachineOutliner.
345 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
346 bool OutlineFromLinkOnceODRs) const override;
347 outliner::OutlinedFunction getOutliningCandidateInfo(
348 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
349 outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT,
350 unsigned Flags) const override;
351 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
352 unsigned &Flags) const override;
353 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
354 const outliner::OutlinedFunction &OF) const override;
355 MachineBasicBlock::iterator
356 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
357 MachineBasicBlock::iterator &It, MachineFunction &MF,
358 const outliner::Candidate &C) const override;
359
360 /// Enable outlining by default at -Oz.
361 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
362
363 private:
364 /// Returns an unused general-purpose register which can be used for
365 /// constructing an outlined call if one exists. Returns 0 otherwise.
366 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
367
368 // Adds an instruction which saves the link register on top of the stack into
369 /// the MachineBasicBlock \p MBB at position \p It.
370 void saveLROnStack(MachineBasicBlock &MBB,
371 MachineBasicBlock::iterator It) const;
372
373 /// Adds an instruction which restores the link register from the top the
374 /// stack into the MachineBasicBlock \p MBB at position \p It.
375 void restoreLRFromStack(MachineBasicBlock &MBB,
376 MachineBasicBlock::iterator It) const;
377
378 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
379 /// for the case when the LR is saved on the stack.
380 void emitCFIForLRSaveOnStack(MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator It) const;
382
383 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
384 /// for the case when the LR is saved in the register \p Reg.
385 void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
386 MachineBasicBlock::iterator It,
387 Register Reg) const;
388
389 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
390 /// after the LR is was restored from the stack.
391 void emitCFIForLRRestoreFromStack(MachineBasicBlock &MBB,
392 MachineBasicBlock::iterator It) const;
393
394 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
395 /// after the LR is was restored from a register.
396 void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
397 MachineBasicBlock::iterator It) const;
398
399 unsigned getInstBundleLength(const MachineInstr &MI) const;
400
401 int getVLDMDefCycle(const InstrItineraryData *ItinData,
402 const MCInstrDesc &DefMCID,
403 unsigned DefClass,
404 unsigned DefIdx, unsigned DefAlign) const;
405 int getLDMDefCycle(const InstrItineraryData *ItinData,
406 const MCInstrDesc &DefMCID,
407 unsigned DefClass,
408 unsigned DefIdx, unsigned DefAlign) const;
409 int getVSTMUseCycle(const InstrItineraryData *ItinData,
410 const MCInstrDesc &UseMCID,
411 unsigned UseClass,
412 unsigned UseIdx, unsigned UseAlign) const;
413 int getSTMUseCycle(const InstrItineraryData *ItinData,
414 const MCInstrDesc &UseMCID,
415 unsigned UseClass,
416 unsigned UseIdx, unsigned UseAlign) const;
417 int getOperandLatency(const InstrItineraryData *ItinData,
418 const MCInstrDesc &DefMCID,
419 unsigned DefIdx, unsigned DefAlign,
420 const MCInstrDesc &UseMCID,
421 unsigned UseIdx, unsigned UseAlign) const;
422
423 int getOperandLatencyImpl(const InstrItineraryData *ItinData,
424 const MachineInstr &DefMI, unsigned DefIdx,
425 const MCInstrDesc &DefMCID, unsigned DefAdj,
426 const MachineOperand &DefMO, unsigned Reg,
427 const MachineInstr &UseMI, unsigned UseIdx,
428 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
429
430 unsigned getPredicationCost(const MachineInstr &MI) const override;
431
432 unsigned getInstrLatency(const InstrItineraryData *ItinData,
433 const MachineInstr &MI,
434 unsigned *PredCost = nullptr) const override;
435
436 int getInstrLatency(const InstrItineraryData *ItinData,
437 SDNode *Node) const override;
438
439 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
440 const MachineRegisterInfo *MRI,
441 const MachineInstr &DefMI, unsigned DefIdx,
442 const MachineInstr &UseMI,
443 unsigned UseIdx) const override;
444 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
445 const MachineInstr &DefMI,
446 unsigned DefIdx) const override;
447
448 /// verifyInstruction - Perform target specific instruction verification.
449 bool verifyInstruction(const MachineInstr &MI,
450 StringRef &ErrInfo) const override;
451
452 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
453
454 void expandMEMCPY(MachineBasicBlock::iterator) const;
455
456 /// Identify instructions that can be folded into a MOVCC instruction, and
457 /// return the defining instruction.
458 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
459 const TargetInstrInfo *TII) const;
460
461 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
462 AAResults *AA) const override;
463
464 private:
465 /// Modeling special VFP / NEON fp MLA / MLS hazards.
466
467 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
468 /// MLx table.
469 DenseMap<unsigned, unsigned> MLxEntryMap;
470
471 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
472 /// stalls when scheduled together with fp MLA / MLS opcodes.
473 SmallSet<unsigned, 16> MLxHazardOpcodes;
474
475 public:
476 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
477 /// instruction.
isFpMLxInstruction(unsigned Opcode)478 bool isFpMLxInstruction(unsigned Opcode) const {
479 return MLxEntryMap.count(Opcode);
480 }
481
482 /// isFpMLxInstruction - This version also returns the multiply opcode and the
483 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
484 /// the MLX instructions with an extra lane operand.
485 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
486 unsigned &AddSubOpc, bool &NegAcc,
487 bool &HasLane) const;
488
489 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
490 /// will cause stalls when scheduled after (within 4-cycle window) a fp
491 /// MLA / MLS instruction.
canCauseFpMLxStall(unsigned Opcode)492 bool canCauseFpMLxStall(unsigned Opcode) const {
493 return MLxHazardOpcodes.count(Opcode);
494 }
495
496 /// Returns true if the instruction has a shift by immediate that can be
497 /// executed in one cycle less.
498 bool isSwiftFastImmShift(const MachineInstr *MI) const;
499
500 /// Returns predicate register associated with the given frame instruction.
getFramePred(const MachineInstr & MI)501 unsigned getFramePred(const MachineInstr &MI) const {
502 assert(isFrameInstr(MI));
503 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
504 // - argument declared in the pattern:
505 // 0 - frame size
506 // 1 - arg of CALLSEQ_START/CALLSEQ_END
507 // 2 - predicate code (like ARMCC::AL)
508 // - added by predOps:
509 // 3 - predicate reg
510 return MI.getOperand(3).getReg();
511 }
512
513 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
514 Register Reg) const override;
515 };
516
517 /// Get the operands corresponding to the given \p Pred value. By default, the
518 /// predicate register is assumed to be 0 (no register), but you can pass in a
519 /// \p PredReg if that is not the case.
520 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
521 unsigned PredReg = 0) {
522 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
523 MachineOperand::CreateReg(PredReg, false)}};
524 }
525
526 /// Get the operand corresponding to the conditional code result. By default,
527 /// this is 0 (no register).
528 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
529 return MachineOperand::CreateReg(CCReg, false);
530 }
531
532 /// Get the operand corresponding to the conditional code result for Thumb1.
533 /// This operand will always refer to CPSR and it will have the Define flag set.
534 /// You can optionally set the Dead flag by means of \p isDead.
535 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
536 return MachineOperand::CreateReg(ARM::CPSR,
537 /*Define*/ true, /*Implicit*/ false,
538 /*Kill*/ false, isDead);
539 }
540
541 static inline
isUncondBranchOpcode(int Opc)542 bool isUncondBranchOpcode(int Opc) {
543 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
544 }
545
546 // This table shows the VPT instruction variants, i.e. the different
547 // mask field encodings, see also B5.6. Predication/conditional execution in
548 // the ArmARM.
isVPTOpcode(int Opc)549 static inline bool isVPTOpcode(int Opc) {
550 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
551 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
552 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
553 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
554 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
555 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
556 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
557 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
558 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
559 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
560 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
561 Opc == ARM::MVE_VPST;
562 }
563
564 static inline
VCMPOpcodeToVPT(unsigned Opcode)565 unsigned VCMPOpcodeToVPT(unsigned Opcode) {
566 switch (Opcode) {
567 default:
568 return 0;
569 case ARM::MVE_VCMPf32:
570 return ARM::MVE_VPTv4f32;
571 case ARM::MVE_VCMPf16:
572 return ARM::MVE_VPTv8f16;
573 case ARM::MVE_VCMPi8:
574 return ARM::MVE_VPTv16i8;
575 case ARM::MVE_VCMPi16:
576 return ARM::MVE_VPTv8i16;
577 case ARM::MVE_VCMPi32:
578 return ARM::MVE_VPTv4i32;
579 case ARM::MVE_VCMPu8:
580 return ARM::MVE_VPTv16u8;
581 case ARM::MVE_VCMPu16:
582 return ARM::MVE_VPTv8u16;
583 case ARM::MVE_VCMPu32:
584 return ARM::MVE_VPTv4u32;
585 case ARM::MVE_VCMPs8:
586 return ARM::MVE_VPTv16s8;
587 case ARM::MVE_VCMPs16:
588 return ARM::MVE_VPTv8s16;
589 case ARM::MVE_VCMPs32:
590 return ARM::MVE_VPTv4s32;
591
592 case ARM::MVE_VCMPf32r:
593 return ARM::MVE_VPTv4f32r;
594 case ARM::MVE_VCMPf16r:
595 return ARM::MVE_VPTv8f16r;
596 case ARM::MVE_VCMPi8r:
597 return ARM::MVE_VPTv16i8r;
598 case ARM::MVE_VCMPi16r:
599 return ARM::MVE_VPTv8i16r;
600 case ARM::MVE_VCMPi32r:
601 return ARM::MVE_VPTv4i32r;
602 case ARM::MVE_VCMPu8r:
603 return ARM::MVE_VPTv16u8r;
604 case ARM::MVE_VCMPu16r:
605 return ARM::MVE_VPTv8u16r;
606 case ARM::MVE_VCMPu32r:
607 return ARM::MVE_VPTv4u32r;
608 case ARM::MVE_VCMPs8r:
609 return ARM::MVE_VPTv16s8r;
610 case ARM::MVE_VCMPs16r:
611 return ARM::MVE_VPTv8s16r;
612 case ARM::MVE_VCMPs32r:
613 return ARM::MVE_VPTv4s32r;
614 }
615 }
616
617 static inline
isCondBranchOpcode(int Opc)618 bool isCondBranchOpcode(int Opc) {
619 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
620 }
621
isJumpTableBranchOpcode(int Opc)622 static inline bool isJumpTableBranchOpcode(int Opc) {
623 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
624 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
625 Opc == ARM::t2BR_JT;
626 }
627
628 static inline
isIndirectBranchOpcode(int Opc)629 bool isIndirectBranchOpcode(int Opc) {
630 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
631 }
632
isPopOpcode(int Opc)633 static inline bool isPopOpcode(int Opc) {
634 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
635 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
636 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
637 }
638
isPushOpcode(int Opc)639 static inline bool isPushOpcode(int Opc) {
640 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
641 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
642 }
643
isSubImmOpcode(int Opc)644 static inline bool isSubImmOpcode(int Opc) {
645 return Opc == ARM::SUBri ||
646 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
647 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
648 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
649 }
650
isMovRegOpcode(int Opc)651 static inline bool isMovRegOpcode(int Opc) {
652 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
653 }
654 /// isValidCoprocessorNumber - decide whether an explicit coprocessor
655 /// number is legal in generic instructions like CDP. The answer can
656 /// vary with the subtarget.
isValidCoprocessorNumber(unsigned Num,const FeatureBitset & featureBits)657 static inline bool isValidCoprocessorNumber(unsigned Num,
658 const FeatureBitset& featureBits) {
659 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
660 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
661 // useful for code which is shared with older architectures which do not know
662 // the new VFP/NEON mnemonics.
663
664 // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
665 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
666 return false;
667
668 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
669 // which clash with MVE.
670 if (featureBits[ARM::HasV8_1MMainlineOps] &&
671 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
672 return false;
673
674 return true;
675 }
676
677 /// getInstrPredicate - If instruction is predicated, returns its predicate
678 /// condition, otherwise returns AL. It also returns the condition code
679 /// register by reference.
680 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
681
682 unsigned getMatchingCondBranchOpcode(unsigned Opc);
683
684 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
685 /// the instruction is encoded with an 'S' bit is determined by the optional
686 /// CPSR def operand.
687 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
688
689 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
690 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
691 /// code.
692 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
693 MachineBasicBlock::iterator &MBBI,
694 const DebugLoc &dl, Register DestReg,
695 Register BaseReg, int NumBytes,
696 ARMCC::CondCodes Pred, Register PredReg,
697 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
698
699 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
700 MachineBasicBlock::iterator &MBBI,
701 const DebugLoc &dl, Register DestReg,
702 Register BaseReg, int NumBytes,
703 ARMCC::CondCodes Pred, Register PredReg,
704 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
705 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
706 MachineBasicBlock::iterator &MBBI,
707 const DebugLoc &dl, Register DestReg,
708 Register BaseReg, int NumBytes,
709 const TargetInstrInfo &TII,
710 const ARMBaseRegisterInfo &MRI,
711 unsigned MIFlags = 0);
712
713 /// Tries to add registers to the reglist of a given base-updating
714 /// push/pop instruction to adjust the stack by an additional
715 /// NumBytes. This can save a few bytes per function in code-size, but
716 /// obviously generates more memory traffic. As such, it only takes
717 /// effect in functions being optimised for size.
718 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
719 MachineFunction &MF, MachineInstr *MI,
720 unsigned NumBytes);
721
722 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
723 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
724 /// offset could not be handled directly in MI, and return the left-over
725 /// portion by reference.
726 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
727 Register FrameReg, int &Offset,
728 const ARMBaseInstrInfo &TII);
729
730 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
731 Register FrameReg, int &Offset,
732 const ARMBaseInstrInfo &TII,
733 const TargetRegisterInfo *TRI);
734
735 /// Return true if Reg is defd between From and To
736 bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From,
737 MachineBasicBlock::iterator To,
738 const TargetRegisterInfo *TRI);
739
740 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
741 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
742 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
743 const TargetRegisterInfo *TRI);
744
745 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
746 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
747
748 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
749 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
750 unsigned Inactive);
751
752 /// Returns the number of instructions required to materialize the given
753 /// constant in a register, or 3 if a literal pool load is needed.
754 /// If ForCodesize is specified, an approximate cost in bytes is returned.
755 unsigned ConstantMaterializationCost(unsigned Val,
756 const ARMSubtarget *Subtarget,
757 bool ForCodesize = false);
758
759 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
760 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
761 /// specified. If the scores are equal, return the comparison for !ForCodesize.
762 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
763 const ARMSubtarget *Subtarget,
764 bool ForCodesize = false);
765
766 // Return the immediate if this is ADDri or SUBri, scaled as appropriate.
767 // Returns 0 for unknown instructions.
getAddSubImmediate(MachineInstr & MI)768 inline int getAddSubImmediate(MachineInstr &MI) {
769 int Scale = 1;
770 unsigned ImmOp;
771 switch (MI.getOpcode()) {
772 case ARM::t2ADDri:
773 ImmOp = 2;
774 break;
775 case ARM::t2SUBri:
776 case ARM::t2SUBri12:
777 ImmOp = 2;
778 Scale = -1;
779 break;
780 case ARM::tSUBi3:
781 case ARM::tSUBi8:
782 ImmOp = 3;
783 Scale = -1;
784 break;
785 default:
786 return 0;
787 }
788 return Scale * MI.getOperand(ImmOp).getImm();
789 }
790
791 // Given a memory access Opcode, check that the give Imm would be a valid Offset
792 // for this instruction using its addressing mode.
isLegalAddressImm(unsigned Opcode,int Imm,const TargetInstrInfo * TII)793 inline bool isLegalAddressImm(unsigned Opcode, int Imm,
794 const TargetInstrInfo *TII) {
795 const MCInstrDesc &Desc = TII->get(Opcode);
796 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
797 switch (AddrMode) {
798 case ARMII::AddrModeT2_i7:
799 return std::abs(Imm) < (((1 << 7) * 1) - 1);
800 case ARMII::AddrModeT2_i7s2:
801 return std::abs(Imm) < (((1 << 7) * 2) - 1) && Imm % 2 == 0;
802 case ARMII::AddrModeT2_i7s4:
803 return std::abs(Imm) < (((1 << 7) * 4) - 1) && Imm % 4 == 0;
804 case ARMII::AddrModeT2_i8:
805 return std::abs(Imm) < (((1 << 8) * 1) - 1);
806 case ARMII::AddrModeT2_i12:
807 return Imm >= 0 && Imm < (((1 << 12) * 1) - 1);
808 default:
809 llvm_unreachable("Unhandled Addressing mode");
810 }
811 }
812
813 // Return true if the given intrinsic is a gather
isGather(IntrinsicInst * IntInst)814 inline bool isGather(IntrinsicInst *IntInst) {
815 if (IntInst == nullptr)
816 return false;
817 unsigned IntrinsicID = IntInst->getIntrinsicID();
818 return (IntrinsicID == Intrinsic::masked_gather ||
819 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
820 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
821 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
822 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
823 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
824 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
825 }
826
827 // Return true if the given intrinsic is a scatter
isScatter(IntrinsicInst * IntInst)828 inline bool isScatter(IntrinsicInst *IntInst) {
829 if (IntInst == nullptr)
830 return false;
831 unsigned IntrinsicID = IntInst->getIntrinsicID();
832 return (IntrinsicID == Intrinsic::masked_scatter ||
833 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
834 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
835 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
836 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
837 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
838 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
839 }
840
841 // Return true if the given intrinsic is a gather or scatter
isGatherScatter(IntrinsicInst * IntInst)842 inline bool isGatherScatter(IntrinsicInst *IntInst) {
843 if (IntInst == nullptr)
844 return false;
845 return isGather(IntInst) || isScatter(IntInst);
846 }
847
848 } // end namespace llvm
849
850 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
851