1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef MEMCTRL_V2_H
9 #define MEMCTRL_V2_H
10
11 #include <arch.h>
12
13 #include <tegra_def.h>
14
15 /*******************************************************************************
16 * Memory Controller SMMU Bypass config register
17 ******************************************************************************/
18 #define MC_SMMU_BYPASS_CONFIG 0x1820U
19 #define MC_SMMU_BYPASS_CTRL_MASK 0x3U
20 #define MC_SMMU_BYPASS_CTRL_SHIFT 0U
21 #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT)
22 #define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT)
23 #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT)
24 #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT)
25 #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31)
26 #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
27 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
28
29 #ifndef __ASSEMBLER__
30
31 #include <assert.h>
32
33 typedef struct mc_regs {
34 uint32_t reg;
35 uint32_t val;
36 } mc_regs_t;
37
38 #define mc_smmu_bypass_cfg \
39 { \
40 .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
41 .val = 0x00000000U, \
42 }
43
44 #define _START_OF_TABLE_ \
45 { \
46 .reg = 0xCAFE05C7U, \
47 .val = 0x00000000U, \
48 }
49
50 #define _END_OF_TABLE_ \
51 { \
52 .reg = 0xFFFFFFFFU, \
53 .val = 0xFFFFFFFFU, \
54 }
55
56 #endif /* __ASSEMBLER__ */
57
58 #ifndef __ASSEMBLER__
59
60 #include <lib/mmio.h>
61
tegra_mc_read_32(uint32_t off)62 static inline uint32_t tegra_mc_read_32(uint32_t off)
63 {
64 return mmio_read_32(TEGRA_MC_BASE + off);
65 }
66
tegra_mc_write_32(uint32_t off,uint32_t val)67 static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
68 {
69 mmio_write_32(TEGRA_MC_BASE + off, val);
70 }
71
72 #if defined(TEGRA_MC_STREAMID_BASE)
tegra_mc_streamid_read_32(uint32_t off)73 static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
74 {
75 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off);
76 }
77
tegra_mc_streamid_write_32(uint32_t off,uint32_t val)78 static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
79 {
80 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
81 assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val);
82 }
83 #endif
84
85 void plat_memctrl_setup(void);
86
87 void plat_memctrl_restore(void);
88 mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void);
89
90 /*******************************************************************************
91 * Handler to save MC settings before "System Suspend" to TZDRAM
92 *
93 * Implemented by Tegra common memctrl_v2 driver under common/drivers/memctrl
94 ******************************************************************************/
95 void tegra_mc_save_context(uint64_t mc_ctx_addr);
96
97 /*******************************************************************************
98 * Handler to program the scratch registers with TZDRAM settings for the
99 * resume firmware.
100 *
101 * Implemented by SoCs under tegra/soc/txxx
102 ******************************************************************************/
103 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes);
104
105 #endif /* __ASSEMBLER__ */
106
107 #endif /* MEMCTRL_V2_H */
108