1 /*
2 * Copyright (C) 2019-2020 Collabora, Ltd.
3 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #ifndef _MDG_COMPILER_H
26 #define _MDG_COMPILER_H
27
28 #include "midgard.h"
29 #include "helpers.h"
30 #include "midgard_compile.h"
31 #include "midgard_ops.h"
32
33 #include "util/hash_table.h"
34 #include "util/u_dynarray.h"
35 #include "util/set.h"
36 #include "util/list.h"
37
38 #include "main/mtypes.h"
39 #include "compiler/nir_types.h"
40 #include "compiler/nir/nir.h"
41 #include "panfrost/util/pan_ir.h"
42 #include "panfrost/util/lcra.h"
43
44 /* Forward declare */
45 struct midgard_block;
46
47 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
48 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
49 * instruction is actually a discard op. */
50
51 #define TARGET_GOTO 0
52 #define TARGET_BREAK 1
53 #define TARGET_CONTINUE 2
54 #define TARGET_DISCARD 3
55 #define TARGET_TILEBUF_WAIT 4
56
57 typedef struct midgard_branch {
58 /* If conditional, the condition is specified in r31.w */
59 bool conditional;
60
61 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
62 bool invert_conditional;
63
64 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
65 unsigned target_type;
66
67 /* The actual target */
68 union {
69 int target_block;
70 int target_break;
71 int target_continue;
72 };
73 } midgard_branch;
74
75 /* Generic in-memory data type repesenting a single logical instruction, rather
76 * than a single instruction group. This is the preferred form for code gen.
77 * Multiple midgard_insturctions will later be combined during scheduling,
78 * though this is not represented in this structure. Its format bridges
79 * the low-level binary representation with the higher level semantic meaning.
80 *
81 * Notably, it allows registers to be specified as block local SSA, for code
82 * emitted before the register allocation pass.
83 */
84
85 #define MIR_SRC_COUNT 4
86 #define MIR_VEC_COMPONENTS 16
87
88 typedef struct midgard_instruction {
89 /* Must be first for casting */
90 struct list_head link;
91
92 unsigned type; /* ALU, load/store, texture */
93
94 /* Instruction arguments represented as block-local SSA
95 * indices, rather than registers. ~0 means unused. */
96 unsigned src[MIR_SRC_COUNT];
97 unsigned dest;
98
99 /* vec16 swizzle, unpacked, per source */
100 unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
101
102 /* Types! */
103 nir_alu_type src_types[MIR_SRC_COUNT];
104 nir_alu_type dest_type;
105
106 /* Packing ops have non-32-bit dest types even though they functionally
107 * work at the 32-bit level, use this as a signal to disable copyprop.
108 * We maybe need synthetic pack ops instead. */
109 bool is_pack;
110
111 /* Modifiers, depending on type */
112 union {
113 struct {
114 bool src_abs[MIR_SRC_COUNT];
115 bool src_neg[MIR_SRC_COUNT];
116 };
117
118 struct {
119 bool src_shift[MIR_SRC_COUNT];
120 };
121 };
122
123 /* Out of the union for csel (could maybe be fixed..) */
124 bool src_invert[MIR_SRC_COUNT];
125
126 /* If the op supports it */
127 enum midgard_roundmode roundmode;
128
129 /* For textures: should helpers execute this instruction (instead of
130 * just helping with derivatives)? Should helpers terminate after? */
131 bool helper_terminate;
132 bool helper_execute;
133
134 /* I.e. (1 << alu_bit) */
135 int unit;
136
137 bool has_constants;
138 midgard_constants constants;
139 uint16_t inline_constant;
140 bool has_inline_constant;
141
142 bool compact_branch;
143 uint8_t writeout;
144 bool last_writeout;
145
146 /* Masks in a saneish format. One bit per channel, not packed fancy.
147 * Use this instead of the op specific ones, and switch over at emit
148 * time */
149
150 uint16_t mask;
151
152 /* Hint for the register allocator not to spill the destination written
153 * from this instruction (because it is a spill/unspill node itself).
154 * Bitmask of spilled classes */
155
156 unsigned no_spill;
157
158 /* Generic hint for intra-pass use */
159 bool hint;
160
161 /* During scheduling, the backwards dependency graph
162 * (DAG). nr_dependencies is the number of unscheduled
163 * instructions that must still be scheduled after
164 * (before) this instruction. dependents are which
165 * instructions need to be scheduled before (after) this
166 * instruction. */
167
168 unsigned nr_dependencies;
169 BITSET_WORD *dependents;
170
171 /* Use this in conjunction with `type` */
172 unsigned op;
173
174 /* This refers to midgard_outmod_float or midgard_outmod_int.
175 * In case of a ALU op, use midgard_is_integer_out_op() to know which
176 * one is used.
177 * If it's a texture op, it's always midgard_outmod_float. */
178 unsigned outmod;
179
180 union {
181 midgard_load_store_word load_store;
182 midgard_texture_word texture;
183
184 midgard_branch branch;
185 };
186 } midgard_instruction;
187
188 typedef struct midgard_block {
189 pan_block base;
190
191 bool scheduled;
192
193 /* List of midgard_bundles emitted (after the scheduler has run) */
194 struct util_dynarray bundles;
195
196 /* Number of quadwords _actually_ emitted, as determined after scheduling */
197 unsigned quadword_count;
198
199 /* Indicates this is a fixed-function fragment epilogue block */
200 bool epilogue;
201
202 /* Are helper invocations required by this block? */
203 bool helpers_in;
204 } midgard_block;
205
206 typedef struct midgard_bundle {
207 /* Tag for the overall bundle */
208 int tag;
209
210 /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
211 * sadd, vadd, smul, vlut, branch) */
212 int instruction_count;
213 midgard_instruction *instructions[6];
214
215 /* Bundle-wide ALU configuration */
216 int padding;
217 int control;
218 bool has_embedded_constants;
219 midgard_constants constants;
220 bool last_writeout;
221 } midgard_bundle;
222
223 enum midgard_rt_id {
224 MIDGARD_COLOR_RT0 = 0,
225 MIDGARD_COLOR_RT1,
226 MIDGARD_COLOR_RT2,
227 MIDGARD_COLOR_RT3,
228 MIDGARD_COLOR_RT4,
229 MIDGARD_COLOR_RT5,
230 MIDGARD_COLOR_RT6,
231 MIDGARD_COLOR_RT7,
232 MIDGARD_ZS_RT,
233 MIDGARD_NUM_RTS,
234 };
235
236 typedef struct compiler_context {
237 nir_shader *nir;
238 gl_shader_stage stage;
239
240 /* Is internally a blend shader? Depends on stage == FRAGMENT */
241 bool is_blend;
242
243 /* Render target number for a keyed blend shader. Depends on is_blend */
244 unsigned blend_rt;
245
246 /* Index to precolour to r0 for an input blend colour */
247 unsigned blend_input;
248
249 /* Index to precolour to r2 for a dual-source blend colour */
250 unsigned blend_src1;
251
252 /* Blend constants */
253 float blend_constants[4];
254
255 /* Number of bytes used for Thread Local Storage */
256 unsigned tls_size;
257
258 /* Count of spills and fills for shaderdb */
259 unsigned spills;
260 unsigned fills;
261
262 /* Current NIR function */
263 nir_function *func;
264
265 /* Allocated compiler temporary counter */
266 unsigned temp_alloc;
267
268 /* Unordered list of midgard_blocks */
269 int block_count;
270 struct list_head blocks;
271
272 /* TODO merge with block_count? */
273 unsigned block_source_count;
274
275 /* List of midgard_instructions emitted for the current block */
276 midgard_block *current_block;
277
278 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
279 midgard_block *after_block;
280
281 /* The current "depth" of the loop, for disambiguating breaks/continues
282 * when using nested loops */
283 int current_loop_depth;
284
285 /* Total number of loops for shader-db */
286 unsigned loop_count;
287
288 /* Constants which have been loaded, for later inlining */
289 struct hash_table_u64 *ssa_constants;
290
291 int temp_count;
292 int max_hash;
293
294 /* Set of NIR indices that were already emitted as outmods */
295 BITSET_WORD *already_emitted;
296
297 /* Just the count of the max register used. Higher count => higher
298 * register pressure */
299 int work_registers;
300
301 /* The number of uniforms allowable for the fast path */
302 int uniform_cutoff;
303
304 /* Count of instructions emitted from NIR overall, across all blocks */
305 int instruction_count;
306
307 unsigned quadword_count;
308
309 /* Bitmask of valid metadata */
310 unsigned metadata;
311
312 /* Model-specific quirk set */
313 uint32_t quirks;
314
315 /* Writeout instructions for each render target */
316 midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
317
318 struct panfrost_sysvals sysvals;
319 } compiler_context;
320
321 /* Per-block live_in/live_out */
322 #define MIDGARD_METADATA_LIVENESS (1 << 0)
323
324 /* Helpers for manipulating the above structures (forming the driver IR) */
325
326 /* Append instruction to end of current block */
327
328 static inline midgard_instruction *
mir_upload_ins(struct compiler_context * ctx,struct midgard_instruction ins)329 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
330 {
331 midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
332 memcpy(heap, &ins, sizeof(ins));
333 return heap;
334 }
335
336 static inline midgard_instruction *
emit_mir_instruction(struct compiler_context * ctx,struct midgard_instruction ins)337 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
338 {
339 midgard_instruction *u = mir_upload_ins(ctx, ins);
340 list_addtail(&u->link, &ctx->current_block->base.instructions);
341 return u;
342 }
343
344 static inline struct midgard_instruction *
mir_insert_instruction_before(struct compiler_context * ctx,struct midgard_instruction * tag,struct midgard_instruction ins)345 mir_insert_instruction_before(struct compiler_context *ctx,
346 struct midgard_instruction *tag,
347 struct midgard_instruction ins)
348 {
349 struct midgard_instruction *u = mir_upload_ins(ctx, ins);
350 list_addtail(&u->link, &tag->link);
351 return u;
352 }
353
354 static inline void
mir_remove_instruction(struct midgard_instruction * ins)355 mir_remove_instruction(struct midgard_instruction *ins)
356 {
357 list_del(&ins->link);
358 }
359
360 static inline midgard_instruction*
mir_prev_op(struct midgard_instruction * ins)361 mir_prev_op(struct midgard_instruction *ins)
362 {
363 return list_last_entry(&(ins->link), midgard_instruction, link);
364 }
365
366 static inline midgard_instruction*
mir_next_op(struct midgard_instruction * ins)367 mir_next_op(struct midgard_instruction *ins)
368 {
369 return list_first_entry(&(ins->link), midgard_instruction, link);
370 }
371
372 #define mir_foreach_block(ctx, v) \
373 list_for_each_entry(pan_block, v, &ctx->blocks, link)
374
375 #define mir_foreach_block_from(ctx, from, v) \
376 list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
377
378 #define mir_foreach_instr_in_block(block, v) \
379 list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
380 #define mir_foreach_instr_in_block_rev(block, v) \
381 list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
382
383 #define mir_foreach_instr_in_block_safe(block, v) \
384 list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
385
386 #define mir_foreach_instr_in_block_safe_rev(block, v) \
387 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
388
389 #define mir_foreach_instr_in_block_from(block, v, from) \
390 list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
391
392 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
393 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
394
395 #define mir_foreach_bundle_in_block(block, v) \
396 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
397
398 #define mir_foreach_bundle_in_block_rev(block, v) \
399 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
400
401 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
402 midgard_instruction* v; \
403 signed i = 0; \
404 mir_foreach_bundle_in_block_rev(block, _bundle) \
405 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
406 i >= 0; \
407 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
408
409 #define mir_foreach_instr_global(ctx, v) \
410 mir_foreach_block(ctx, v_block) \
411 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
412
413 #define mir_foreach_instr_global_safe(ctx, v) \
414 mir_foreach_block(ctx, v_block) \
415 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
416
417 /* Based on set_foreach, expanded with automatic type casts */
418
419 #define mir_foreach_predecessor(blk, v) \
420 struct set_entry *_entry_##v; \
421 struct midgard_block *v; \
422 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
423 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
424 _entry_##v != NULL; \
425 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
426 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
427
428 #define mir_foreach_src(ins, v) \
429 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
430
431 static inline midgard_instruction *
mir_last_in_block(struct midgard_block * block)432 mir_last_in_block(struct midgard_block *block)
433 {
434 return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
435 }
436
437 static inline midgard_block *
mir_get_block(compiler_context * ctx,int idx)438 mir_get_block(compiler_context *ctx, int idx)
439 {
440 struct list_head *lst = &ctx->blocks;
441
442 while ((idx--) + 1)
443 lst = lst->next;
444
445 return (struct midgard_block *) lst;
446 }
447
448 static inline bool
mir_is_alu_bundle(midgard_bundle * bundle)449 mir_is_alu_bundle(midgard_bundle *bundle)
450 {
451 return IS_ALU(bundle->tag);
452 }
453
454 static inline unsigned
make_compiler_temp(compiler_context * ctx)455 make_compiler_temp(compiler_context *ctx)
456 {
457 return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
458 }
459
460 static inline unsigned
make_compiler_temp_reg(compiler_context * ctx)461 make_compiler_temp_reg(compiler_context *ctx)
462 {
463 return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
464 }
465
466 static inline unsigned
nir_ssa_index(nir_ssa_def * ssa)467 nir_ssa_index(nir_ssa_def *ssa)
468 {
469 return (ssa->index << 1) | 0;
470 }
471
472 static inline unsigned
nir_src_index(compiler_context * ctx,nir_src * src)473 nir_src_index(compiler_context *ctx, nir_src *src)
474 {
475 if (src->is_ssa)
476 return nir_ssa_index(src->ssa);
477 else {
478 assert(!src->reg.indirect);
479 return (src->reg.reg->index << 1) | PAN_IS_REG;
480 }
481 }
482
483 static inline unsigned
nir_dest_index(nir_dest * dst)484 nir_dest_index(nir_dest *dst)
485 {
486 if (dst->is_ssa)
487 return (dst->ssa.index << 1) | 0;
488 else {
489 assert(!dst->reg.indirect);
490 return (dst->reg.reg->index << 1) | PAN_IS_REG;
491 }
492 }
493
494
495
496 /* MIR manipulation */
497
498 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
499 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
500 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
501 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
502 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
503 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
504 bool mir_single_use(compiler_context *ctx, unsigned value);
505 unsigned mir_use_count(compiler_context *ctx, unsigned value);
506 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
507 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
508 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
509 uint16_t mir_bytemask(midgard_instruction *ins);
510 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
511 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
512 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
513 unsigned mir_components_for_type(nir_alu_type T);
514 unsigned max_bitsize_for_alu(midgard_instruction *ins);
515 midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
516
517 /* MIR printing */
518
519 void mir_print_instruction(midgard_instruction *ins);
520 void mir_print_bundle(midgard_bundle *ctx);
521 void mir_print_block(midgard_block *block);
522 void mir_print_shader(compiler_context *ctx);
523 bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
524 bool mir_nontrivial_outmod(midgard_instruction *ins);
525
526 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
527 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
528 void mir_flip(midgard_instruction *ins);
529 void mir_compute_temp_count(compiler_context *ctx);
530
531 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
532
533 /* 'Intrinsic' move for aliasing */
534
535 static inline midgard_instruction
v_mov(unsigned src,unsigned dest)536 v_mov(unsigned src, unsigned dest)
537 {
538 midgard_instruction ins = {
539 .type = TAG_ALU_4,
540 .mask = 0xF,
541 .src = { ~0, src, ~0, ~0 },
542 .src_types = { 0, nir_type_uint32 },
543 .swizzle = SWIZZLE_IDENTITY,
544 .dest = dest,
545 .dest_type = nir_type_uint32,
546 .op = midgard_alu_op_imov,
547 .outmod = midgard_outmod_int_wrap
548 };
549
550 return ins;
551 }
552
553 /* Broad types of register classes so we can handle special
554 * registers */
555
556 #define REG_CLASS_WORK 0
557 #define REG_CLASS_LDST 1
558 #define REG_CLASS_TEXR 3
559 #define REG_CLASS_TEXW 4
560
561 /* Like a move, but to thread local storage! */
562
563 static inline midgard_instruction
v_load_store_scratch(unsigned srcdest,unsigned index,bool is_store,unsigned mask)564 v_load_store_scratch(
565 unsigned srcdest,
566 unsigned index,
567 bool is_store,
568 unsigned mask)
569 {
570 /* We index by 32-bit vec4s */
571 unsigned byte = (index * 4 * 4);
572
573 midgard_instruction ins = {
574 .type = TAG_LOAD_STORE_4,
575 .mask = mask,
576 .dest_type = nir_type_uint32,
577 .dest = ~0,
578 .src = { ~0, ~0, ~0, ~0 },
579 .swizzle = SWIZZLE_IDENTITY_4,
580 .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
581 .load_store = {
582 /* For register spilling - to thread local storage */
583 .arg_1 = 0xEA,
584 .arg_2 = 0x1E,
585 },
586
587 /* If we spill an unspill, RA goes into an infinite loop */
588 .no_spill = (1 << REG_CLASS_WORK)
589 };
590
591 ins.constants.u32[0] = byte;
592
593 if (is_store) {
594 ins.src[0] = srcdest;
595 ins.src_types[0] = nir_type_uint32;
596
597 /* Ensure we are tightly swizzled so liveness analysis is
598 * correct */
599
600 for (unsigned i = 0; i < 4; ++i) {
601 if (!(mask & (1 << i)))
602 ins.swizzle[0][i] = COMPONENT_X;
603 }
604 } else
605 ins.dest = srcdest;
606
607 return ins;
608 }
609
610 static inline bool
mir_has_arg(midgard_instruction * ins,unsigned arg)611 mir_has_arg(midgard_instruction *ins, unsigned arg)
612 {
613 if (!ins)
614 return false;
615
616 mir_foreach_src(ins, i) {
617 if (ins->src[i] == arg)
618 return true;
619 }
620
621 return false;
622 }
623
624 /* Scheduling */
625
626 void midgard_schedule_program(compiler_context *ctx);
627
628 void mir_ra(compiler_context *ctx);
629 void mir_squeeze_index(compiler_context *ctx);
630 void mir_lower_special_reads(compiler_context *ctx);
631 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
632 void mir_compute_liveness(compiler_context *ctx);
633 void mir_invalidate_liveness(compiler_context *ctx);
634 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
635
636 void mir_create_pipeline_registers(compiler_context *ctx);
637 void midgard_promote_uniforms(compiler_context *ctx);
638
639 void
640 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
641
642 void
643 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
644
645 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
646
647 void mir_analyze_helper_terminate(compiler_context *ctx);
648 void mir_analyze_helper_requirements(compiler_context *ctx);
649
650 /* Final emission */
651
652 void emit_binary_bundle(
653 compiler_context *ctx,
654 midgard_block *block,
655 midgard_bundle *bundle,
656 struct util_dynarray *emission,
657 int next_tag);
658
659 bool nir_fuse_io_16(nir_shader *shader);
660
661 bool midgard_nir_lod_errata(nir_shader *shader);
662
663 unsigned midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx);
664
665 /* Optimizations */
666
667 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
668 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
669 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
670 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
671 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
672
673 #endif
674