1 /*
2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 * Copyright (C) 2019-2020 Collabora, Ltd.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include "compiler.h"
26 #include "midgard_ops.h"
27
mir_rewrite_index_src_single(midgard_instruction * ins,unsigned old,unsigned new)28 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new)
29 {
30 mir_foreach_src(ins, i) {
31 if (ins->src[i] == old)
32 ins->src[i] = new;
33 }
34 }
35
mir_rewrite_index_dst_single(midgard_instruction * ins,unsigned old,unsigned new)36 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new)
37 {
38 if (ins->dest == old)
39 ins->dest = new;
40 }
41
42 static void
mir_rewrite_index_src_single_swizzle(midgard_instruction * ins,unsigned old,unsigned new,unsigned * swizzle)43 mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned *swizzle)
44 {
45 for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
46 if (ins->src[i] != old) continue;
47
48 ins->src[i] = new;
49 mir_compose_swizzle(ins->swizzle[i], swizzle, ins->swizzle[i]);
50 }
51 }
52
53 void
mir_rewrite_index_src(compiler_context * ctx,unsigned old,unsigned new)54 mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new)
55 {
56 mir_foreach_instr_global(ctx, ins) {
57 mir_rewrite_index_src_single(ins, old, new);
58 }
59 }
60
61 void
mir_rewrite_index_src_swizzle(compiler_context * ctx,unsigned old,unsigned new,unsigned * swizzle)62 mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle)
63 {
64 mir_foreach_instr_global(ctx, ins) {
65 mir_rewrite_index_src_single_swizzle(ins, old, new, swizzle);
66 }
67 }
68
69 void
mir_rewrite_index_dst(compiler_context * ctx,unsigned old,unsigned new)70 mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new)
71 {
72 mir_foreach_instr_global(ctx, ins) {
73 mir_rewrite_index_dst_single(ins, old, new);
74 }
75
76 /* Implicitly written before the shader */
77 if (ctx->blend_input == old)
78 ctx->blend_input = new;
79
80 if (ctx->blend_src1 == old)
81 ctx->blend_src1 = new;
82 }
83
84 void
mir_rewrite_index(compiler_context * ctx,unsigned old,unsigned new)85 mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new)
86 {
87 mir_rewrite_index_src(ctx, old, new);
88 mir_rewrite_index_dst(ctx, old, new);
89 }
90
91 unsigned
mir_use_count(compiler_context * ctx,unsigned value)92 mir_use_count(compiler_context *ctx, unsigned value)
93 {
94 unsigned used_count = 0;
95
96 mir_foreach_instr_global(ctx, ins) {
97 if (mir_has_arg(ins, value))
98 ++used_count;
99 }
100
101 return used_count;
102 }
103
104 /* Checks if a value is used only once (or totally dead), which is an important
105 * heuristic to figure out if certain optimizations are Worth It (TM) */
106
107 bool
mir_single_use(compiler_context * ctx,unsigned value)108 mir_single_use(compiler_context *ctx, unsigned value)
109 {
110 /* We can replicate constants in places so who cares */
111 if (value == SSA_FIXED_REGISTER(REGISTER_CONSTANT))
112 return true;
113
114 return mir_use_count(ctx, value) <= 1;
115 }
116
117 bool
mir_nontrivial_mod(midgard_instruction * ins,unsigned i,bool check_swizzle)118 mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle)
119 {
120 bool is_int = midgard_is_integer_op(ins->op);
121
122 if (is_int) {
123 if (ins->src_shift[i]) return true;
124 } else {
125 if (ins->src_neg[i]) return true;
126 if (ins->src_abs[i]) return true;
127 }
128
129 if (ins->dest_type != ins->src_types[i]) return true;
130
131 if (check_swizzle) {
132 for (unsigned c = 0; c < 16; ++c) {
133 if (!(ins->mask & (1 << c))) continue;
134 if (ins->swizzle[i][c] != c) return true;
135 }
136 }
137
138 return false;
139 }
140
141 bool
mir_nontrivial_outmod(midgard_instruction * ins)142 mir_nontrivial_outmod(midgard_instruction *ins)
143 {
144 bool is_int = midgard_is_integer_op(ins->op);
145 unsigned mod = ins->outmod;
146
147 if (ins->dest_type != ins->src_types[1])
148 return true;
149
150 if (is_int)
151 return mod != midgard_outmod_int_wrap;
152 else
153 return mod != midgard_outmod_none;
154 }
155
156 /* 128 / sz = exp2(log2(128 / sz))
157 * = exp2(log2(128) - log2(sz))
158 * = exp2(7 - log2(sz))
159 * = 1 << (7 - log2(sz))
160 */
161
162 static unsigned
mir_components_for_bits(unsigned bits)163 mir_components_for_bits(unsigned bits)
164 {
165 return 1 << (7 - util_logbase2(bits));
166 }
167
168 unsigned
mir_components_for_type(nir_alu_type T)169 mir_components_for_type(nir_alu_type T)
170 {
171 unsigned sz = nir_alu_type_get_type_size(T);
172 return mir_components_for_bits(sz);
173 }
174
175 uint16_t
mir_from_bytemask(uint16_t bytemask,unsigned bits)176 mir_from_bytemask(uint16_t bytemask, unsigned bits)
177 {
178 unsigned value = 0;
179 unsigned count = bits / 8;
180
181 for (unsigned c = 0, d = 0; c < 16; c += count, ++d) {
182 bool a = (bytemask & (1 << c)) != 0;
183
184 for (unsigned q = c; q < count; ++q)
185 assert(((bytemask & (1 << q)) != 0) == a);
186
187 value |= (a << d);
188 }
189
190 return value;
191 }
192
193 /* Rounds up a bytemask to fill a given component count. Iterate each
194 * component, and check if any bytes in the component are masked on */
195
196 uint16_t
mir_round_bytemask_up(uint16_t mask,unsigned bits)197 mir_round_bytemask_up(uint16_t mask, unsigned bits)
198 {
199 unsigned bytes = bits / 8;
200 unsigned maxmask = mask_of(bytes);
201 unsigned channels = mir_components_for_bits(bits);
202
203 for (unsigned c = 0; c < channels; ++c) {
204 unsigned submask = maxmask << (c * bytes);
205
206 if (mask & submask)
207 mask |= submask;
208 }
209
210 return mask;
211 }
212
213 /* Grabs the per-byte mask of an instruction (as opposed to per-component) */
214
215 uint16_t
mir_bytemask(midgard_instruction * ins)216 mir_bytemask(midgard_instruction *ins)
217 {
218 unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
219 return pan_to_bytemask(type_size, ins->mask);
220 }
221
222 void
mir_set_bytemask(midgard_instruction * ins,uint16_t bytemask)223 mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask)
224 {
225 unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
226 ins->mask = mir_from_bytemask(bytemask, type_size);
227 }
228
229 /* Checks if we should use an upper destination override, rather than the lower
230 * one in the IR. Returns zero if no, returns the bytes to shift otherwise */
231
232 signed
mir_upper_override(midgard_instruction * ins,unsigned inst_size)233 mir_upper_override(midgard_instruction *ins, unsigned inst_size)
234 {
235 unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
236
237 /* If the sizes are the same, there's nothing to override */
238 if (type_size == inst_size)
239 return -1;
240
241 /* There are 16 bytes per vector, so there are (16/bytes)
242 * components per vector. So the magic half is half of
243 * (16/bytes), which simplifies to 8/bytes = 8 / (bits / 8) = 64 / bits
244 * */
245
246 unsigned threshold = mir_components_for_bits(type_size) >> 1;
247
248 /* How many components did we shift over? */
249 unsigned zeroes = __builtin_ctz(ins->mask);
250
251 /* Did we hit the threshold? */
252 return (zeroes >= threshold) ? threshold : 0;
253 }
254
255 /* Creates a mask of the components of a node read by an instruction, by
256 * analyzing the swizzle with respect to the instruction's mask. E.g.:
257 *
258 * fadd r0.xz, r1.yyyy, r2.zwyx
259 *
260 * will return a mask of Z/Y for r2
261 */
262
263 static uint16_t
mir_bytemask_of_read_components_single(unsigned * swizzle,unsigned inmask,unsigned bits)264 mir_bytemask_of_read_components_single(unsigned *swizzle, unsigned inmask, unsigned bits)
265 {
266 unsigned cmask = 0;
267
268 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
269 if (!(inmask & (1 << c))) continue;
270 cmask |= (1 << swizzle[c]);
271 }
272
273 return pan_to_bytemask(bits, cmask);
274 }
275
276 uint16_t
mir_bytemask_of_read_components_index(midgard_instruction * ins,unsigned i)277 mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i)
278 {
279 /* Conditional branches read one 32-bit component = 4 bytes (TODO: multi branch??) */
280 if (ins->compact_branch && ins->branch.conditional && (i == 0))
281 return 0xF;
282
283 /* ALU ops act componentwise so we need to pay attention to
284 * their mask. Texture/ldst does not so we don't clamp source
285 * readmasks based on the writemask */
286 unsigned qmask = ~0;
287
288 /* Handle dot products and things */
289 if (ins->type == TAG_ALU_4 && !ins->compact_branch) {
290 unsigned props = alu_opcode_props[ins->op].props;
291
292 unsigned channel_override = GET_CHANNEL_COUNT(props);
293
294 if (channel_override)
295 qmask = mask_of(channel_override);
296 else
297 qmask = ins->mask;
298 }
299
300 return mir_bytemask_of_read_components_single(ins->swizzle[i], qmask,
301 nir_alu_type_get_type_size(ins->src_types[i]));
302 }
303
304 uint16_t
mir_bytemask_of_read_components(midgard_instruction * ins,unsigned node)305 mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node)
306 {
307 uint16_t mask = 0;
308
309 if (node == ~0)
310 return 0;
311
312 mir_foreach_src(ins, i) {
313 if (ins->src[i] != node) continue;
314 mask |= mir_bytemask_of_read_components_index(ins, i);
315 }
316
317 return mask;
318 }
319
320 /* Register allocation occurs after instruction scheduling, which is fine until
321 * we start needing to spill registers and therefore insert instructions into
322 * an already-scheduled program. We don't have to be terribly efficient about
323 * this, since spilling is already slow. So just semantically we need to insert
324 * the instruction into a new bundle before/after the bundle of the instruction
325 * in question */
326
327 static midgard_bundle
mir_bundle_for_op(compiler_context * ctx,midgard_instruction ins)328 mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
329 {
330 midgard_instruction *u = mir_upload_ins(ctx, ins);
331
332 midgard_bundle bundle = {
333 .tag = ins.type,
334 .instruction_count = 1,
335 .instructions = { u },
336 };
337
338 if (bundle.tag == TAG_ALU_4) {
339 assert(OP_IS_MOVE(u->op));
340 u->unit = UNIT_VMUL;
341
342 size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) + sizeof(midgard_vector_alu);
343 bundle.padding = ~(bytes_emitted - 1) & 0xF;
344 bundle.control = ins.type | u->unit;
345 }
346
347 return bundle;
348 }
349
350 static unsigned
mir_bundle_idx_for_ins(midgard_instruction * tag,midgard_block * block)351 mir_bundle_idx_for_ins(midgard_instruction *tag, midgard_block *block)
352 {
353 midgard_bundle *bundles =
354 (midgard_bundle *) block->bundles.data;
355
356 size_t count = (block->bundles.size / sizeof(midgard_bundle));
357
358 for (unsigned i = 0; i < count; ++i) {
359 for (unsigned j = 0; j < bundles[i].instruction_count; ++j) {
360 if (bundles[i].instructions[j] == tag)
361 return i;
362 }
363 }
364
365 mir_print_instruction(tag);
366 unreachable("Instruction not scheduled in block");
367 }
368
369 void
mir_insert_instruction_before_scheduled(compiler_context * ctx,midgard_block * block,midgard_instruction * tag,midgard_instruction ins)370 mir_insert_instruction_before_scheduled(
371 compiler_context *ctx,
372 midgard_block *block,
373 midgard_instruction *tag,
374 midgard_instruction ins)
375 {
376 unsigned before = mir_bundle_idx_for_ins(tag, block);
377 size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
378 UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
379
380 midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
381 memmove(bundles + before + 1, bundles + before, (count - before) * sizeof(midgard_bundle));
382 midgard_bundle *before_bundle = bundles + before + 1;
383
384 midgard_bundle new = mir_bundle_for_op(ctx, ins);
385 memcpy(bundles + before, &new, sizeof(new));
386
387 list_addtail(&new.instructions[0]->link, &before_bundle->instructions[0]->link);
388 block->quadword_count += midgard_tag_props[new.tag].size;
389 }
390
391 void
mir_insert_instruction_after_scheduled(compiler_context * ctx,midgard_block * block,midgard_instruction * tag,midgard_instruction ins)392 mir_insert_instruction_after_scheduled(
393 compiler_context *ctx,
394 midgard_block *block,
395 midgard_instruction *tag,
396 midgard_instruction ins)
397 {
398 /* We need to grow the bundles array to add our new bundle */
399 size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
400 UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
401
402 /* Find the bundle that we want to insert after */
403 unsigned after = mir_bundle_idx_for_ins(tag, block);
404
405 /* All the bundles after that one, we move ahead by one */
406 midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
407 memmove(bundles + after + 2, bundles + after + 1, (count - after - 1) * sizeof(midgard_bundle));
408 midgard_bundle *after_bundle = bundles + after;
409
410 midgard_bundle new = mir_bundle_for_op(ctx, ins);
411 memcpy(bundles + after + 1, &new, sizeof(new));
412 list_add(&new.instructions[0]->link, &after_bundle->instructions[after_bundle->instruction_count - 1]->link);
413 block->quadword_count += midgard_tag_props[new.tag].size;
414 }
415
416 /* Flip the first-two arguments of a (binary) op. Currently ALU
417 * only, no known uses for ldst/tex */
418
419 void
mir_flip(midgard_instruction * ins)420 mir_flip(midgard_instruction *ins)
421 {
422 unsigned temp = ins->src[0];
423 ins->src[0] = ins->src[1];
424 ins->src[1] = temp;
425
426 assert(ins->type == TAG_ALU_4);
427
428 temp = ins->src_types[0];
429 ins->src_types[0] = ins->src_types[1];
430 ins->src_types[1] = temp;
431
432 temp = ins->src_abs[0];
433 ins->src_abs[0] = ins->src_abs[1];
434 ins->src_abs[1] = temp;
435
436 temp = ins->src_neg[0];
437 ins->src_neg[0] = ins->src_neg[1];
438 ins->src_neg[1] = temp;
439
440 temp = ins->src_invert[0];
441 ins->src_invert[0] = ins->src_invert[1];
442 ins->src_invert[1] = temp;
443
444 unsigned temp_swizzle[16];
445 memcpy(temp_swizzle, ins->swizzle[0], sizeof(ins->swizzle[0]));
446 memcpy(ins->swizzle[0], ins->swizzle[1], sizeof(ins->swizzle[0]));
447 memcpy(ins->swizzle[1], temp_swizzle, sizeof(ins->swizzle[0]));
448 }
449
450 /* Before squashing, calculate ctx->temp_count just by observing the MIR */
451
452 void
mir_compute_temp_count(compiler_context * ctx)453 mir_compute_temp_count(compiler_context *ctx)
454 {
455 if (ctx->temp_count)
456 return;
457
458 unsigned max_dest = 0;
459
460 mir_foreach_instr_global(ctx, ins) {
461 if (ins->dest < SSA_FIXED_MINIMUM)
462 max_dest = MAX2(max_dest, ins->dest + 1);
463 }
464
465 ctx->temp_count = max_dest;
466 }
467