1 /*
2 * Copyright (c) 2019, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <common/bl_common.h>
9 #include <common/debug.h>
10 #include <drivers/arm/gicv3.h>
11 #include <bl31/interrupt_mgmt.h>
12 #include <mt_gic_v3.h>
13 #include <mtk_plat_common.h>
14 #include "../drivers/arm/gic/v3/gicv3_private.h"
15 #include "plat_private.h"
16 #include <plat/common/platform.h>
17 #include <platform_def.h>
18 #include <stdint.h>
19 #include <stdio.h>
20
21 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
22 static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
23
24 /* we save and restore the GICv3 context on system suspend */
25 gicv3_dist_ctx_t dist_ctx;
26
mt_mpidr_to_core_pos(u_register_t mpidr)27 static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
28 {
29 return plat_core_pos_by_mpidr(mpidr);
30 }
31
32 gicv3_driver_data_t mt_gicv3_data = {
33 .gicd_base = MT_GIC_BASE,
34 .gicr_base = MT_GIC_RDIST_BASE,
35 .rdistif_num = PLATFORM_CORE_COUNT,
36 .rdistif_base_addrs = rdistif_base_addrs,
37 .mpidr_to_core_pos = mt_mpidr_to_core_pos,
38 };
39
40 struct gic_chip_data {
41 unsigned int saved_group;
42 unsigned int saved_enable;
43 unsigned int saved_conf0;
44 unsigned int saved_conf1;
45 unsigned int saved_grpmod;
46 };
47
48 static struct gic_chip_data gic_data;
49
clear_sec_pol_ctl_en(void)50 void clear_sec_pol_ctl_en(void)
51 {
52 unsigned int i;
53
54 /* total 19 polarity ctrl registers */
55 for (i = 0; i <= NR_INT_POL_CTL - 1; i++) {
56 mmio_write_32((SEC_POL_CTL_EN0 + (i * 4)), 0);
57 }
58 dsb();
59 }
60
mt_gic_driver_init(void)61 void mt_gic_driver_init(void)
62 {
63 gicv3_driver_init(&mt_gicv3_data);
64 }
65
mt_gic_set_pending(uint32_t irq)66 void mt_gic_set_pending(uint32_t irq)
67 {
68 gicv3_set_interrupt_pending(irq, plat_my_core_pos());
69 }
70
mt_gic_cpuif_enable(void)71 void mt_gic_cpuif_enable(void)
72 {
73 gicv3_cpuif_enable(plat_my_core_pos());
74 }
75
mt_gic_cpuif_disable(void)76 void mt_gic_cpuif_disable(void)
77 {
78 gicv3_cpuif_disable(plat_my_core_pos());
79 }
80
mt_gic_rdistif_init(void)81 void mt_gic_rdistif_init(void)
82 {
83 unsigned int proc_num;
84 unsigned int index;
85 uintptr_t gicr_base;
86
87 proc_num = plat_my_core_pos();
88 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
89
90 /* set all SGI/PPI as non-secure GROUP1 by default */
91 mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
92 mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
93
94 /* setup the default PPI/SGI priorities */
95 for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
96 gicr_write_ipriorityr(gicr_base, index,
97 GICD_IPRIORITYR_DEF_VAL);
98 }
99
mt_gic_distif_save(void)100 void mt_gic_distif_save(void)
101 {
102 gicv3_distif_save(&dist_ctx);
103 }
104
mt_gic_distif_restore(void)105 void mt_gic_distif_restore(void)
106 {
107 gicv3_distif_init_restore(&dist_ctx);
108 }
109
mt_gic_rdistif_save(void)110 void mt_gic_rdistif_save(void)
111 {
112 unsigned int proc_num;
113 uintptr_t gicr_base;
114
115 proc_num = plat_my_core_pos();
116 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
117
118 gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
119 gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
120 gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
121 gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
122 gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
123
124 rdist_has_saved[proc_num] = 1;
125 }
126
mt_gic_rdistif_restore(void)127 void mt_gic_rdistif_restore(void)
128 {
129 unsigned int proc_num;
130 uintptr_t gicr_base;
131
132 proc_num = plat_my_core_pos();
133 if (rdist_has_saved[proc_num] == 1) {
134 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
135 mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
136 mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable);
137 mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
138 mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
139 mmio_write_32(gicr_base + GICR_IGRPMODR0, gic_data.saved_grpmod);
140 }
141 }
142
mt_gic_sync_dcm_enable(void)143 void mt_gic_sync_dcm_enable(void)
144 {
145 mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON);
146 }
147
mt_gic_sync_dcm_disable(void)148 void mt_gic_sync_dcm_disable(void)
149 {
150 mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF);
151 }
152
mt_gic_init(void)153 void mt_gic_init(void)
154 {
155 gicv3_distif_init();
156 gicv3_cpuif_enable(plat_my_core_pos());
157 mt_gic_rdistif_init();
158
159 clear_sec_pol_ctl_en();
160 }
161