1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jason Ekstrand (jason@jlekstrand.net)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_control_flow.h"
30 #include "nir_search_helpers.h"
31
32 /*
33 * Implements a small peephole optimization that looks for
34 *
35 * if (cond) {
36 * <then SSA defs>
37 * } else {
38 * <else SSA defs>
39 * }
40 * phi
41 * ...
42 * phi
43 *
44 * and replaces it with:
45 *
46 * <then SSA defs>
47 * <else SSA defs>
48 * bcsel
49 * ...
50 * bcsel
51 *
52 * where the SSA defs are ALU operations or other cheap instructions (not
53 * texturing, for example).
54 *
55 * If the number of ALU operations in the branches is greater than the limit
56 * parameter, then the optimization is skipped. In limit=0 mode, the SSA defs
57 * must only be MOVs which we expect to get copy-propagated away once they're
58 * out of the inner blocks.
59 */
60
61 static bool
block_check_for_allowed_instrs(nir_block * block,unsigned * count,bool alu_ok,bool indirect_load_ok,bool expensive_alu_ok)62 block_check_for_allowed_instrs(nir_block *block, unsigned *count,
63 bool alu_ok, bool indirect_load_ok,
64 bool expensive_alu_ok)
65 {
66 nir_foreach_instr(instr, block) {
67 switch (instr->type) {
68 case nir_instr_type_intrinsic: {
69 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
70
71 switch (intrin->intrinsic) {
72 case nir_intrinsic_load_deref: {
73 nir_deref_instr *const deref = nir_src_as_deref(intrin->src[0]);
74
75 switch (deref->modes) {
76 case nir_var_shader_in:
77 case nir_var_uniform:
78 /* Don't try to remove flow control around an indirect load
79 * because that flow control may be trying to avoid invalid
80 * loads.
81 */
82 if (!indirect_load_ok && nir_deref_instr_has_indirect(deref))
83 return false;
84
85 break;
86
87 default:
88 return false;
89 }
90 break;
91 }
92
93 case nir_intrinsic_load_uniform:
94 if (!alu_ok)
95 return false;
96 break;
97
98 default:
99 return false;
100 }
101
102 break;
103 }
104
105 case nir_instr_type_deref:
106 case nir_instr_type_load_const:
107 break;
108
109 case nir_instr_type_alu: {
110 nir_alu_instr *mov = nir_instr_as_alu(instr);
111 bool movelike = false;
112
113 switch (mov->op) {
114 case nir_op_mov:
115 case nir_op_fneg:
116 case nir_op_ineg:
117 case nir_op_fabs:
118 case nir_op_iabs:
119 case nir_op_vec2:
120 case nir_op_vec3:
121 case nir_op_vec4:
122 case nir_op_vec8:
123 case nir_op_vec16:
124 movelike = true;
125 break;
126
127 case nir_op_fcos:
128 case nir_op_fdiv:
129 case nir_op_fexp2:
130 case nir_op_flog2:
131 case nir_op_fmod:
132 case nir_op_fpow:
133 case nir_op_frcp:
134 case nir_op_frem:
135 case nir_op_frsq:
136 case nir_op_fsin:
137 case nir_op_idiv:
138 case nir_op_irem:
139 case nir_op_udiv:
140 if (!alu_ok || !expensive_alu_ok)
141 return false;
142
143 break;
144
145 default:
146 if (!alu_ok) {
147 /* It must be a move-like operation. */
148 return false;
149 }
150 break;
151 }
152
153 /* It must be SSA */
154 if (!mov->dest.dest.is_ssa)
155 return false;
156
157 if (alu_ok) {
158 /* If the ALU operation is an fsat or a move-like operation, do
159 * not count it. The expectation is that it will eventually be
160 * merged as a destination modifier or source modifier on some
161 * other instruction.
162 */
163 if (mov->op != nir_op_fsat && !movelike)
164 (*count)++;
165 } else {
166 /* Can't handle saturate */
167 if (mov->dest.saturate)
168 return false;
169
170 /* It cannot have any if-uses */
171 if (!list_is_empty(&mov->dest.dest.ssa.if_uses))
172 return false;
173
174 /* The only uses of this definition must be phis in the successor */
175 nir_foreach_use(use, &mov->dest.dest.ssa) {
176 if (use->parent_instr->type != nir_instr_type_phi ||
177 use->parent_instr->block != block->successors[0])
178 return false;
179 }
180 }
181 break;
182 }
183
184 default:
185 return false;
186 }
187 }
188
189 return true;
190 }
191
192 static bool
nir_opt_peephole_select_block(nir_block * block,nir_shader * shader,unsigned limit,bool indirect_load_ok,bool expensive_alu_ok)193 nir_opt_peephole_select_block(nir_block *block, nir_shader *shader,
194 unsigned limit, bool indirect_load_ok,
195 bool expensive_alu_ok)
196 {
197 if (nir_cf_node_is_first(&block->cf_node))
198 return false;
199
200 nir_cf_node *prev_node = nir_cf_node_prev(&block->cf_node);
201 if (prev_node->type != nir_cf_node_if)
202 return false;
203
204 nir_if *if_stmt = nir_cf_node_as_if(prev_node);
205
206 if (if_stmt->control == nir_selection_control_dont_flatten)
207 return false;
208
209 nir_block *then_block = nir_if_first_then_block(if_stmt);
210 nir_block *else_block = nir_if_first_else_block(if_stmt);
211
212 /* We can only have one block in each side ... */
213 if (nir_if_last_then_block(if_stmt) != then_block ||
214 nir_if_last_else_block(if_stmt) != else_block)
215 return false;
216
217 if (if_stmt->control == nir_selection_control_flatten) {
218 /* Override driver defaults */
219 indirect_load_ok = true;
220 expensive_alu_ok = true;
221 }
222
223 /* ... and those blocks must only contain "allowed" instructions. */
224 unsigned count = 0;
225 if (!block_check_for_allowed_instrs(then_block, &count, limit != 0,
226 indirect_load_ok, expensive_alu_ok) ||
227 !block_check_for_allowed_instrs(else_block, &count, limit != 0,
228 indirect_load_ok, expensive_alu_ok))
229 return false;
230
231 if (count > limit && if_stmt->control != nir_selection_control_flatten)
232 return false;
233
234 /* At this point, we know that the previous CFG node is an if-then
235 * statement containing only moves to phi nodes in this block. We can
236 * just remove that entire CF node and replace all of the phi nodes with
237 * selects.
238 */
239
240 nir_block *prev_block = nir_cf_node_as_block(nir_cf_node_prev(prev_node));
241
242 /* First, we move the remaining instructions from the blocks to the
243 * block before. We have already guaranteed that this is safe by
244 * calling block_check_for_allowed_instrs()
245 */
246 nir_foreach_instr_safe(instr, then_block) {
247 exec_node_remove(&instr->node);
248 instr->block = prev_block;
249 exec_list_push_tail(&prev_block->instr_list, &instr->node);
250 }
251
252 nir_foreach_instr_safe(instr, else_block) {
253 exec_node_remove(&instr->node);
254 instr->block = prev_block;
255 exec_list_push_tail(&prev_block->instr_list, &instr->node);
256 }
257
258 nir_foreach_instr_safe(instr, block) {
259 if (instr->type != nir_instr_type_phi)
260 break;
261
262 nir_phi_instr *phi = nir_instr_as_phi(instr);
263 nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_bcsel);
264 nir_src_copy(&sel->src[0].src, &if_stmt->condition, sel);
265 /* Splat the condition to all channels */
266 memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle);
267
268 assert(exec_list_length(&phi->srcs) == 2);
269 nir_foreach_phi_src(src, phi) {
270 assert(src->pred == then_block || src->pred == else_block);
271 assert(src->src.is_ssa);
272
273 unsigned idx = src->pred == then_block ? 1 : 2;
274 nir_src_copy(&sel->src[idx].src, &src->src, sel);
275 }
276
277 nir_ssa_dest_init(&sel->instr, &sel->dest.dest,
278 phi->dest.ssa.num_components,
279 phi->dest.ssa.bit_size, phi->dest.ssa.name);
280 sel->dest.write_mask = (1 << phi->dest.ssa.num_components) - 1;
281
282 nir_ssa_def_rewrite_uses(&phi->dest.ssa,
283 nir_src_for_ssa(&sel->dest.dest.ssa));
284
285 nir_instr_insert_before(&phi->instr, &sel->instr);
286 nir_instr_remove(&phi->instr);
287 }
288
289 nir_cf_node_remove(&if_stmt->cf_node);
290 return true;
291 }
292
293 static bool
nir_opt_peephole_select_impl(nir_function_impl * impl,unsigned limit,bool indirect_load_ok,bool expensive_alu_ok)294 nir_opt_peephole_select_impl(nir_function_impl *impl, unsigned limit,
295 bool indirect_load_ok, bool expensive_alu_ok)
296 {
297 nir_shader *shader = impl->function->shader;
298 bool progress = false;
299
300 nir_foreach_block_safe(block, impl) {
301 progress |= nir_opt_peephole_select_block(block, shader, limit,
302 indirect_load_ok,
303 expensive_alu_ok);
304 }
305
306 if (progress) {
307 nir_metadata_preserve(impl, nir_metadata_none);
308 } else {
309 nir_metadata_preserve(impl, nir_metadata_all);
310 }
311
312 return progress;
313 }
314
315 bool
nir_opt_peephole_select(nir_shader * shader,unsigned limit,bool indirect_load_ok,bool expensive_alu_ok)316 nir_opt_peephole_select(nir_shader *shader, unsigned limit,
317 bool indirect_load_ok, bool expensive_alu_ok)
318 {
319 bool progress = false;
320
321 nir_foreach_function(function, shader) {
322 if (function->impl)
323 progress |= nir_opt_peephole_select_impl(function->impl, limit,
324 indirect_load_ok,
325 expensive_alu_ok);
326 }
327
328 return progress;
329 }
330