1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32 #include "util/u_threaded_context.h"
33
34 #if UTIL_ARCH_BIG_ENDIAN
35 #define SI_BIG_ENDIAN 1
36 #else
37 #define SI_BIG_ENDIAN 0
38 #endif
39
40 #define ATI_VENDOR_ID 0x1002
41 #define SI_PRIM_DISCARD_DEBUG 0
42 #define SI_NOT_QUERY 0xffffffff
43
44 /* The base vertex and primitive restart can be any number, but we must pick
45 * one which will mean "unknown" for the purpose of state tracking and
46 * the number shouldn't be a commonly-used one. */
47 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
48 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
49 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_MAX_POINT_SIZE 2048
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
55
56 /* Tunables for compute-based clear_buffer and copy_buffer: */
57 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
58 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
59 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
60
61 /* Pipeline & streamout query controls. */
62 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
63 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
64 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
65 /* Instruction cache. */
66 #define SI_CONTEXT_INV_ICACHE (1 << 3)
67 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
68 * GFX10: This also invalidates the L1 shader array cache. */
69 #define SI_CONTEXT_INV_SCACHE (1 << 4)
70 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
71 * GFX10: This also invalidates the L1 shader array cache. */
72 #define SI_CONTEXT_INV_VCACHE (1 << 5)
73 /* L2 cache + L2 metadata cache writeback & invalidate.
74 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
75 #define SI_CONTEXT_INV_L2 (1 << 6)
76 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
77 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
78 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
79 #define SI_CONTEXT_WB_L2 (1 << 7)
80 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
81 * a CB or DB flush. */
82 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
83 /* Framebuffer caches. */
84 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
85 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
86 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
87 /* Engine synchronization. */
88 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
89 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
90 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
91 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
92 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
93
94 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
95 #define SI_PREFETCH_LS (1 << 1)
96 #define SI_PREFETCH_HS (1 << 2)
97 #define SI_PREFETCH_ES (1 << 3)
98 #define SI_PREFETCH_GS (1 << 4)
99 #define SI_PREFETCH_VS (1 << 5)
100 #define SI_PREFETCH_PS (1 << 6)
101
102 #define SI_MAX_BORDER_COLORS 4096
103 #define SI_MAX_VIEWPORTS 16
104 #define SIX_BITS 0x3F
105 #define SI_MAP_BUFFER_ALIGNMENT 64
106 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
107
108 #define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
109 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
110 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
111 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
112 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
113 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
114 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
115 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
116 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
117 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
118 /* Set a micro tile mode: */
119 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
120 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
121 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \
122 (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
123 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
124 (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
125 #define SI_RESOURCE_FLAG_UNCACHED (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
126 #define SI_RESOURCE_FLAG_DRIVER_INTERNAL (PIPE_RESOURCE_FLAG_DRV_PRIV << 13)
127
128 enum si_clear_code
129 {
130 DCC_CLEAR_COLOR_0000 = 0x00000000,
131 DCC_CLEAR_COLOR_0001 = 0x40404040,
132 DCC_CLEAR_COLOR_1110 = 0x80808080,
133 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
134 DCC_CLEAR_COLOR_REG = 0x20202020,
135 DCC_UNCOMPRESSED = 0xFFFFFFFF,
136 };
137
138 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
139 #define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
140
141 /* Debug flags. */
142 enum
143 {
144 /* Shader logging options: */
145 DBG_VS = MESA_SHADER_VERTEX,
146 DBG_TCS = MESA_SHADER_TESS_CTRL,
147 DBG_TES = MESA_SHADER_TESS_EVAL,
148 DBG_GS = MESA_SHADER_GEOMETRY,
149 DBG_PS = MESA_SHADER_FRAGMENT,
150 DBG_CS = MESA_SHADER_COMPUTE,
151 DBG_NO_IR,
152 DBG_NO_NIR,
153 DBG_NO_ASM,
154 DBG_PREOPT_IR,
155
156 /* Shader compiler options the shader cache should be aware of: */
157 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
158 DBG_GISEL,
159 DBG_W32_GE,
160 DBG_W32_PS,
161 DBG_W32_CS,
162 DBG_W64_GE,
163 DBG_W64_PS,
164 DBG_W64_CS,
165
166 /* Shader compiler options (with no effect on the shader cache): */
167 DBG_CHECK_IR,
168 DBG_MONOLITHIC_SHADERS,
169 DBG_NO_OPT_VARIANT,
170
171 /* Information logging options: */
172 DBG_INFO,
173 DBG_TEX,
174 DBG_COMPUTE,
175 DBG_VM,
176 DBG_CACHE_STATS,
177
178 /* Driver options: */
179 DBG_FORCE_SDMA,
180 DBG_NO_SDMA,
181 DBG_NO_SDMA_CLEARS,
182 DBG_NO_SDMA_COPY_IMAGE,
183 DBG_NO_WC,
184 DBG_CHECK_VM,
185 DBG_RESERVE_VMID,
186 DBG_ZERO_VRAM,
187 DBG_SHADOW_REGS,
188
189 /* 3D engine options: */
190 DBG_NO_GFX,
191 DBG_NO_NGG,
192 DBG_ALWAYS_NGG_CULLING_ALL,
193 DBG_ALWAYS_NGG_CULLING_TESS,
194 DBG_NO_NGG_CULLING,
195 DBG_ALWAYS_PD,
196 DBG_PD,
197 DBG_NO_PD,
198 DBG_SWITCH_ON_EOP,
199 DBG_NO_OUT_OF_ORDER,
200 DBG_NO_DPBB,
201 DBG_NO_DFSM,
202 DBG_DPBB,
203 DBG_DFSM,
204 DBG_NO_HYPERZ,
205 DBG_NO_RB_PLUS,
206 DBG_NO_2D_TILING,
207 DBG_NO_TILING,
208 DBG_NO_DCC,
209 DBG_NO_DCC_CLEAR,
210 DBG_NO_DCC_FB,
211 DBG_NO_DCC_MSAA,
212 DBG_NO_FMASK,
213
214 DBG_TMZ,
215
216 DBG_COUNT
217 };
218
219 enum
220 {
221 /* Tests: */
222 DBG_TEST_DMA,
223 DBG_TEST_VMFAULT_CP,
224 DBG_TEST_VMFAULT_SDMA,
225 DBG_TEST_VMFAULT_SHADER,
226 DBG_TEST_DMA_PERF,
227 DBG_TEST_GDS,
228 DBG_TEST_GDS_MM,
229 DBG_TEST_GDS_OA_MM,
230 };
231
232 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
233 #define DBG(name) (1ull << DBG_##name)
234
235 enum si_cache_policy
236 {
237 L2_BYPASS,
238 L2_STREAM, /* same as SLC=1 */
239 L2_LRU, /* same as SLC=0 */
240 };
241
242 enum si_coherency
243 {
244 SI_COHERENCY_NONE, /* no cache flushes needed */
245 SI_COHERENCY_SHADER,
246 SI_COHERENCY_CB_META,
247 SI_COHERENCY_DB_META,
248 SI_COHERENCY_CP,
249 };
250
251 struct si_compute;
252 struct si_shader_context;
253 struct hash_table;
254 struct u_suballocator;
255
256 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
257 * at the moment.
258 */
259 struct si_resource {
260 struct threaded_resource b;
261
262 /* Winsys objects. */
263 struct pb_buffer *buf;
264 uint64_t gpu_address;
265 /* Memory usage if the buffer placement is optimal. */
266 uint64_t vram_usage;
267 uint64_t gart_usage;
268
269 /* Resource properties. */
270 uint64_t bo_size;
271 unsigned bo_alignment;
272 enum radeon_bo_domain domains;
273 enum radeon_bo_flag flags;
274 unsigned bind_history;
275 int max_forced_staging_uploads;
276
277 /* The buffer range which is initialized (with a write transfer,
278 * streamout, DMA, or as a random access target). The rest of
279 * the buffer is considered invalid and can be mapped unsynchronized.
280 *
281 * This allows unsychronized mapping of a buffer range which hasn't
282 * been used yet. It's for applications which forget to use
283 * the unsynchronized map flag and expect the driver to figure it out.
284 */
285 struct util_range valid_buffer_range;
286
287 /* For buffers only. This indicates that a write operation has been
288 * performed by TC L2, but the cache hasn't been flushed.
289 * Any hw block which doesn't use or bypasses TC L2 should check this
290 * flag and flush the cache before using the buffer.
291 *
292 * For example, TC L2 must be flushed if a buffer which has been
293 * modified by a shader store instruction is about to be used as
294 * an index buffer. The reason is that VGT DMA index fetching doesn't
295 * use TC L2.
296 */
297 bool TC_L2_dirty;
298
299 /* Whether this resource is referenced by bindless handles. */
300 bool texture_handle_allocated;
301 bool image_handle_allocated;
302
303 /* Whether the resource has been exported via resource_get_handle. */
304 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
305 };
306
307 struct si_transfer {
308 struct threaded_transfer b;
309 struct si_resource *staging;
310 unsigned offset;
311 };
312
313 struct si_texture {
314 struct si_resource buffer;
315
316 struct radeon_surf surface;
317 struct si_texture *flushed_depth_texture;
318
319 /* One texture allocation can contain these buffers:
320 * - image (pixel data)
321 * - FMASK buffer (MSAA compression)
322 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
323 * - HTILE buffer (Z/S compression and fast Z/S clear)
324 * - DCC buffer (color compression and new fast color clear)
325 * - displayable DCC buffer (if the DCC buffer is not displayable)
326 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
327 */
328 uint64_t cmask_base_address_reg;
329 struct si_resource *cmask_buffer;
330 unsigned cb_color_info; /* fast clear enable bit */
331 unsigned color_clear_value[2];
332 unsigned last_msaa_resolve_target_micro_mode;
333 unsigned num_level0_transfers;
334 unsigned plane_index; /* other planes are different pipe_resources */
335 unsigned num_planes;
336
337 /* Depth buffer compression and fast clear. */
338 float depth_clear_value;
339 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
340 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
341 enum pipe_format db_render_format : 16;
342 uint8_t stencil_clear_value;
343 bool fmask_is_identity : 1;
344 bool tc_compatible_htile : 1;
345 bool enable_tc_compatible_htile_next_clear : 1;
346 bool htile_stencil_disabled : 1;
347 bool depth_cleared : 1; /* if it was cleared at least once */
348 bool stencil_cleared : 1; /* if it was cleared at least once */
349 bool upgraded_depth : 1; /* upgraded from unorm to Z32_FLOAT */
350 bool is_depth : 1;
351 bool db_compatible : 1;
352 bool can_sample_z : 1;
353 bool can_sample_s : 1;
354
355 /* We need to track DCC dirtiness, because st/dri usually calls
356 * flush_resource twice per frame (not a bug) and we don't wanna
357 * decompress DCC twice. Also, the dirty tracking must be done even
358 * if DCC isn't used, because it's required by the DCC usage analysis
359 * for a possible future enablement.
360 */
361 bool separate_dcc_dirty : 1;
362 bool displayable_dcc_dirty : 1;
363
364 /* Statistics gathering for the DCC enablement heuristic. */
365 bool dcc_gather_statistics : 1;
366 /* Counter that should be non-zero if the texture is bound to a
367 * framebuffer.
368 */
369 unsigned framebuffers_bound;
370 /* Whether the texture is a displayable back buffer and needs DCC
371 * decompression, which is expensive. Therefore, it's enabled only
372 * if statistics suggest that it will pay off and it's allocated
373 * separately. It can't be bound as a sampler by apps. Limited to
374 * target == 2D and last_level == 0. If enabled, dcc_offset contains
375 * the absolute GPUVM address, not the relative one.
376 */
377 struct si_resource *dcc_separate_buffer;
378 /* When DCC is temporarily disabled, the separate buffer is here. */
379 struct si_resource *last_dcc_separate_buffer;
380 /* Estimate of how much this color buffer is written to in units of
381 * full-screen draws: ps_invocations / (width * height)
382 * Shader kills, late Z, and blending with trivial discards make it
383 * inaccurate (we need to count CB updates, not PS invocations).
384 */
385 unsigned ps_draw_ratio;
386 /* The number of clears since the last DCC usage analysis. */
387 unsigned num_slow_clears;
388
389 struct si_resource *dcc_retile_buffer;
390 };
391
392 struct si_surface {
393 struct pipe_surface base;
394
395 /* These can vary with block-compressed textures. */
396 uint16_t width0;
397 uint16_t height0;
398
399 bool color_initialized : 1;
400 bool depth_initialized : 1;
401
402 /* Misc. color flags. */
403 bool color_is_int8 : 1;
404 bool color_is_int10 : 1;
405 bool dcc_incompatible : 1;
406
407 /* Color registers. */
408 unsigned cb_color_info;
409 unsigned cb_color_view;
410 unsigned cb_color_attrib;
411 unsigned cb_color_attrib2; /* GFX9 and later */
412 unsigned cb_color_attrib3; /* GFX10 and later */
413 unsigned cb_dcc_control; /* GFX8 and later */
414 unsigned spi_shader_col_format : 8; /* no blending, no alpha-to-coverage. */
415 unsigned spi_shader_col_format_alpha : 8; /* alpha-to-coverage */
416 unsigned spi_shader_col_format_blend : 8; /* blending without alpha. */
417 unsigned spi_shader_col_format_blend_alpha : 8; /* blending with alpha. */
418
419 /* DB registers. */
420 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
421 uint64_t db_stencil_base;
422 uint64_t db_htile_data_base;
423 unsigned db_depth_info;
424 unsigned db_z_info;
425 unsigned db_z_info2; /* GFX9 only */
426 unsigned db_depth_view;
427 unsigned db_depth_size;
428 unsigned db_depth_slice;
429 unsigned db_stencil_info;
430 unsigned db_stencil_info2; /* GFX9 only */
431 unsigned db_htile_surface;
432 };
433
434 struct si_mmio_counter {
435 unsigned busy;
436 unsigned idle;
437 };
438
439 union si_mmio_counters {
440 struct si_mmio_counters_named {
441 /* For global GPU load including SDMA. */
442 struct si_mmio_counter gpu;
443
444 /* GRBM_STATUS */
445 struct si_mmio_counter spi;
446 struct si_mmio_counter gui;
447 struct si_mmio_counter ta;
448 struct si_mmio_counter gds;
449 struct si_mmio_counter vgt;
450 struct si_mmio_counter ia;
451 struct si_mmio_counter sx;
452 struct si_mmio_counter wd;
453 struct si_mmio_counter bci;
454 struct si_mmio_counter sc;
455 struct si_mmio_counter pa;
456 struct si_mmio_counter db;
457 struct si_mmio_counter cp;
458 struct si_mmio_counter cb;
459
460 /* SRBM_STATUS2 */
461 struct si_mmio_counter sdma;
462
463 /* CP_STAT */
464 struct si_mmio_counter pfp;
465 struct si_mmio_counter meq;
466 struct si_mmio_counter me;
467 struct si_mmio_counter surf_sync;
468 struct si_mmio_counter cp_dma;
469 struct si_mmio_counter scratch_ram;
470 } named;
471
472 unsigned array[sizeof(struct si_mmio_counters_named) / sizeof(unsigned)];
473 };
474
475 struct si_memory_object {
476 struct pipe_memory_object b;
477 struct pb_buffer *buf;
478 uint32_t stride;
479 };
480
481 /* Saved CS data for debugging features. */
482 struct radeon_saved_cs {
483 uint32_t *ib;
484 unsigned num_dw;
485
486 struct radeon_bo_list_item *bo_list;
487 unsigned bo_count;
488 };
489
490 struct si_screen {
491 struct pipe_screen b;
492 struct radeon_winsys *ws;
493 struct disk_cache *disk_shader_cache;
494
495 struct radeon_info info;
496 struct nir_shader_compiler_options nir_options;
497 uint64_t debug_flags;
498 char renderer_string[183];
499
500 void (*make_texture_descriptor)(struct si_screen *screen, struct si_texture *tex, bool sampler,
501 enum pipe_texture_target target, enum pipe_format pipe_format,
502 const unsigned char state_swizzle[4], unsigned first_level,
503 unsigned last_level, unsigned first_layer, unsigned last_layer,
504 unsigned width, unsigned height, unsigned depth, uint32_t *state,
505 uint32_t *fmask_state);
506
507 unsigned num_vbos_in_user_sgprs;
508 unsigned pa_sc_raster_config;
509 unsigned pa_sc_raster_config_1;
510 unsigned se_tile_repeat;
511 unsigned gs_table_depth;
512 unsigned tess_offchip_block_dw_size;
513 unsigned tess_offchip_ring_size;
514 unsigned tess_factor_ring_size;
515 unsigned vgt_hs_offchip_param;
516 unsigned eqaa_force_coverage_samples;
517 unsigned eqaa_force_z_samples;
518 unsigned eqaa_force_color_samples;
519 unsigned pbb_context_states_per_bin;
520 unsigned pbb_persistent_states_per_bin;
521 bool has_draw_indirect_multi;
522 bool has_out_of_order_rast;
523 bool assume_no_z_fights;
524 bool commutative_blend_add;
525 bool dpbb_allowed;
526 bool dfsm_allowed;
527 bool llvm_has_working_vgpr_indexing;
528 bool use_ngg;
529 bool use_ngg_culling;
530 bool use_ngg_streamout;
531
532 struct {
533 #define OPT_BOOL(name, dflt, description) bool name : 1;
534 #include "si_debug_options.h"
535 } options;
536
537 /* Whether shaders are monolithic (1-part) or separate (3-part). */
538 bool use_monolithic_shaders;
539 bool record_llvm_ir;
540 bool dcc_msaa_allowed;
541
542 struct slab_parent_pool pool_transfers;
543
544 /* Texture filter settings. */
545 int force_aniso; /* -1 = disabled */
546
547 /* Auxiliary context. Mainly used to initialize resources.
548 * It must be locked prior to using and flushed before unlocking. */
549 struct pipe_context *aux_context;
550 simple_mtx_t aux_context_lock;
551
552 /* This must be in the screen, because UE4 uses one context for
553 * compilation and another one for rendering.
554 */
555 unsigned num_compilations;
556 /* Along with ST_DEBUG=precompile, this should show if applications
557 * are loading shaders on demand. This is a monotonic counter.
558 */
559 unsigned num_shaders_created;
560 unsigned num_memory_shader_cache_hits;
561 unsigned num_memory_shader_cache_misses;
562 unsigned num_disk_shader_cache_hits;
563 unsigned num_disk_shader_cache_misses;
564
565 /* GPU load thread. */
566 simple_mtx_t gpu_load_mutex;
567 thrd_t gpu_load_thread;
568 union si_mmio_counters mmio_counters;
569 volatile unsigned gpu_load_stop_thread; /* bool */
570
571 /* Performance counters. */
572 struct si_perfcounters *perfcounters;
573
574 /* If pipe_screen wants to recompute and re-emit the framebuffer,
575 * sampler, and image states of all contexts, it should atomically
576 * increment this.
577 *
578 * Each context will compare this with its own last known value of
579 * the counter before drawing and re-emit the states accordingly.
580 */
581 unsigned dirty_tex_counter;
582 unsigned dirty_buf_counter;
583
584 /* Atomically increment this counter when an existing texture's
585 * metadata is enabled or disabled in a way that requires changing
586 * contexts' compressed texture binding masks.
587 */
588 unsigned compressed_colortex_counter;
589
590 struct {
591 /* Context flags to set so that all writes from earlier jobs
592 * in the CP are seen by L2 clients.
593 */
594 unsigned cp_to_L2;
595
596 /* Context flags to set so that all writes from earlier jobs
597 * that end in L2 are seen by CP.
598 */
599 unsigned L2_to_cp;
600 } barrier_flags;
601
602 simple_mtx_t shader_parts_mutex;
603 struct si_shader_part *vs_prologs;
604 struct si_shader_part *tcs_epilogs;
605 struct si_shader_part *gs_prologs;
606 struct si_shader_part *ps_prologs;
607 struct si_shader_part *ps_epilogs;
608
609 /* Shader cache in memory.
610 *
611 * Design & limitations:
612 * - The shader cache is per screen (= per process), never saved to
613 * disk, and skips redundant shader compilations from NIR to bytecode.
614 * - It can only be used with one-variant-per-shader support, in which
615 * case only the main (typically middle) part of shaders is cached.
616 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
617 * variants of VS and TES are cached, so LS and ES aren't.
618 * - GS and CS aren't cached, but it's certainly possible to cache
619 * those as well.
620 */
621 simple_mtx_t shader_cache_mutex;
622 struct hash_table *shader_cache;
623
624 /* Shader cache of live shaders. */
625 struct util_live_shader_cache live_shader_cache;
626
627 /* Shader compiler queue for multithreaded compilation. */
628 struct util_queue shader_compiler_queue;
629 /* Use at most 3 normal compiler threads on quadcore and better.
630 * Hyperthreaded CPUs report the number of threads, but we want
631 * the number of cores. We only need this many threads for shader-db. */
632 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
633
634 struct util_queue shader_compiler_queue_low_priority;
635 /* Use at most 2 low priority threads on quadcore and better.
636 * We want to minimize the impact on multithreaded Mesa. */
637 struct ac_llvm_compiler compiler_lowp[10];
638
639 unsigned compute_wave_size;
640 unsigned ps_wave_size;
641 unsigned ge_wave_size;
642 };
643
644 struct si_blend_color {
645 struct pipe_blend_color state;
646 bool any_nonzeros;
647 };
648
649 struct si_sampler_view {
650 struct pipe_sampler_view base;
651 /* [0..7] = image descriptor
652 * [4..7] = buffer descriptor */
653 uint32_t state[8];
654 uint32_t fmask_state[8];
655 const struct legacy_surf_level *base_level_info;
656 ubyte base_level;
657 ubyte block_width;
658 bool is_stencil_sampler;
659 bool is_integer;
660 bool dcc_incompatible;
661 };
662
663 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
664
665 struct si_sampler_state {
666 #ifndef NDEBUG
667 unsigned magic;
668 #endif
669 uint32_t val[4];
670 uint32_t integer_val[4];
671 uint32_t upgraded_depth_val[4];
672 };
673
674 struct si_cs_shader_state {
675 struct si_compute *program;
676 struct si_compute *emitted_program;
677 unsigned offset;
678 bool initialized;
679 bool uses_scratch;
680 };
681
682 struct si_samplers {
683 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
684 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
685
686 /* The i-th bit is set if that element is enabled (non-NULL resource). */
687 unsigned enabled_mask;
688 uint32_t needs_depth_decompress_mask;
689 uint32_t needs_color_decompress_mask;
690 };
691
692 struct si_images {
693 struct pipe_image_view views[SI_NUM_IMAGES];
694 uint32_t needs_color_decompress_mask;
695 unsigned enabled_mask;
696 };
697
698 struct si_framebuffer {
699 struct pipe_framebuffer_state state;
700 unsigned colorbuf_enabled_4bit;
701 unsigned spi_shader_col_format;
702 unsigned spi_shader_col_format_alpha;
703 unsigned spi_shader_col_format_blend;
704 unsigned spi_shader_col_format_blend_alpha;
705 ubyte nr_samples : 5; /* at most 16xAA */
706 ubyte log_samples : 3; /* at most 4 = 16xAA */
707 ubyte nr_color_samples; /* at most 8xAA */
708 ubyte compressed_cb_mask;
709 ubyte uncompressed_cb_mask;
710 ubyte color_is_int8;
711 ubyte color_is_int10;
712 ubyte dirty_cbufs;
713 ubyte dcc_overwrite_combiner_watermark;
714 ubyte min_bytes_per_pixel;
715 bool dirty_zsbuf;
716 bool any_dst_linear;
717 bool CB_has_shader_readable_metadata;
718 bool DB_has_shader_readable_metadata;
719 bool all_DCC_pipe_aligned;
720 };
721
722 enum si_quant_mode
723 {
724 /* This is the list we want to support. */
725 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
726 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
727 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
728 };
729
730 struct si_signed_scissor {
731 int minx;
732 int miny;
733 int maxx;
734 int maxy;
735 enum si_quant_mode quant_mode;
736 };
737
738 struct si_viewports {
739 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
740 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
741 bool y_inverted;
742 };
743
744 struct si_clip_state {
745 struct pipe_clip_state state;
746 bool any_nonzeros;
747 };
748
749 struct si_streamout_target {
750 struct pipe_stream_output_target b;
751
752 /* The buffer where BUFFER_FILLED_SIZE is stored. */
753 struct si_resource *buf_filled_size;
754 unsigned buf_filled_size_offset;
755 bool buf_filled_size_valid;
756
757 unsigned stride_in_dw;
758 };
759
760 struct si_streamout {
761 bool begin_emitted;
762
763 unsigned enabled_mask;
764 unsigned num_targets;
765 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
766
767 unsigned append_bitmask;
768 bool suspended;
769
770 /* External state which comes from the vertex shader,
771 * it must be set explicitly when binding a shader. */
772 uint16_t *stride_in_dw;
773 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
774
775 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
776 unsigned hw_enabled_mask;
777
778 /* The state of VGT_STRMOUT_(CONFIG|EN). */
779 bool streamout_enabled;
780 bool prims_gen_query_enabled;
781 int num_prims_gen_queries;
782 };
783
784 /* A shader state consists of the shader selector, which is a constant state
785 * object shared by multiple contexts and shouldn't be modified, and
786 * the current shader variant selected for this context.
787 */
788 struct si_shader_ctx_state {
789 struct si_shader_selector *cso;
790 struct si_shader *current;
791 };
792
793 #define SI_NUM_VGT_PARAM_KEY_BITS 12
794 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
795
796 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
797 * Some fields are set by state-change calls, most are set by draw_vbo.
798 */
799 union si_vgt_param_key {
800 struct {
801 #if UTIL_ARCH_LITTLE_ENDIAN
802 unsigned prim : 4;
803 unsigned uses_instancing : 1;
804 unsigned multi_instances_smaller_than_primgroup : 1;
805 unsigned primitive_restart : 1;
806 unsigned count_from_stream_output : 1;
807 unsigned line_stipple_enabled : 1;
808 unsigned uses_tess : 1;
809 unsigned tess_uses_prim_id : 1;
810 unsigned uses_gs : 1;
811 unsigned _pad : 32 - SI_NUM_VGT_PARAM_KEY_BITS;
812 #else /* UTIL_ARCH_BIG_ENDIAN */
813 unsigned _pad : 32 - SI_NUM_VGT_PARAM_KEY_BITS;
814 unsigned uses_gs : 1;
815 unsigned tess_uses_prim_id : 1;
816 unsigned uses_tess : 1;
817 unsigned line_stipple_enabled : 1;
818 unsigned count_from_stream_output : 1;
819 unsigned primitive_restart : 1;
820 unsigned multi_instances_smaller_than_primgroup : 1;
821 unsigned uses_instancing : 1;
822 unsigned prim : 4;
823 #endif
824 } u;
825 uint32_t index;
826 };
827
828 #define SI_NUM_VGT_STAGES_KEY_BITS 6
829 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
830
831 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
832 * Some fields are set by state-change calls, most are set by draw_vbo.
833 */
834 union si_vgt_stages_key {
835 struct {
836 #if UTIL_ARCH_LITTLE_ENDIAN
837 unsigned tess : 1;
838 unsigned gs : 1;
839 unsigned ngg_gs_fast_launch : 1;
840 unsigned ngg_passthrough : 1;
841 unsigned ngg : 1; /* gfx10+ */
842 unsigned streamout : 1; /* only used with NGG */
843 unsigned _pad : 32 - SI_NUM_VGT_STAGES_KEY_BITS;
844 #else /* UTIL_ARCH_BIG_ENDIAN */
845 unsigned _pad : 32 - SI_NUM_VGT_STAGES_KEY_BITS;
846 unsigned streamout : 1;
847 unsigned ngg : 1;
848 unsigned ngg_passthrough : 1;
849 unsigned ngg_gs_fast_launch : 1;
850 unsigned gs : 1;
851 unsigned tess : 1;
852 #endif
853 } u;
854 uint32_t index;
855 };
856
857 struct si_texture_handle {
858 unsigned desc_slot;
859 bool desc_dirty;
860 struct pipe_sampler_view *view;
861 struct si_sampler_state sstate;
862 };
863
864 struct si_image_handle {
865 unsigned desc_slot;
866 bool desc_dirty;
867 struct pipe_image_view view;
868 };
869
870 struct si_saved_cs {
871 struct pipe_reference reference;
872 struct si_context *ctx;
873 struct radeon_saved_cs gfx;
874 struct radeon_saved_cs compute;
875 struct si_resource *trace_buf;
876 unsigned trace_id;
877
878 unsigned gfx_last_dw;
879 unsigned compute_last_dw;
880 bool flushed;
881 int64_t time_flush;
882 };
883
884 struct si_sdma_upload {
885 struct si_resource *dst;
886 struct si_resource *src;
887 unsigned src_offset;
888 unsigned dst_offset;
889 unsigned size;
890 };
891
892 struct si_small_prim_cull_info {
893 float scale[2], translate[2];
894 float small_prim_precision;
895 };
896
897 struct si_context {
898 struct pipe_context b; /* base class */
899
900 enum radeon_family family;
901 enum chip_class chip_class;
902
903 struct radeon_winsys *ws;
904 struct radeon_winsys_ctx *ctx;
905 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
906 struct radeon_cmdbuf *sdma_cs;
907 struct pipe_fence_handle *last_gfx_fence;
908 struct pipe_fence_handle *last_sdma_fence;
909 struct si_resource *eop_bug_scratch;
910 struct si_resource *eop_bug_scratch_tmz;
911 struct u_upload_mgr *cached_gtt_allocator;
912 struct threaded_context *tc;
913 struct u_suballocator *allocator_zeroed_memory;
914 struct slab_child_pool pool_transfers;
915 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
916 struct pipe_device_reset_callback device_reset_callback;
917 struct u_log_context *log;
918 void *query_result_shader;
919 void *sh_query_result_shader;
920 struct si_resource *shadowed_regs;
921
922 void (*emit_cache_flush)(struct si_context *ctx);
923
924 struct blitter_context *blitter;
925 void *noop_blend;
926 void *noop_dsa;
927 void *discard_rasterizer_state;
928 void *custom_dsa_flush;
929 void *custom_blend_resolve;
930 void *custom_blend_fmask_decompress;
931 void *custom_blend_eliminate_fastclear;
932 void *custom_blend_dcc_decompress;
933 void *vs_blit_pos;
934 void *vs_blit_pos_layered;
935 void *vs_blit_color;
936 void *vs_blit_color_layered;
937 void *vs_blit_texcoord;
938 void *cs_clear_buffer;
939 void *cs_copy_buffer;
940 void *cs_copy_image;
941 void *cs_copy_image_1d_array;
942 void *cs_clear_render_target;
943 void *cs_clear_render_target_1d_array;
944 void *cs_clear_12bytes_buffer;
945 void *cs_dcc_decompress;
946 void *cs_dcc_retile;
947 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
948 struct si_screen *screen;
949 struct pipe_debug_callback debug;
950 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
951 struct si_shader_ctx_state fixed_func_tcs_shader;
952 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
953 struct si_resource *wait_mem_scratch;
954 struct si_resource *wait_mem_scratch_tmz;
955 unsigned wait_mem_number;
956 uint16_t prefetch_L2_mask;
957
958 bool is_noop;
959 bool has_graphics;
960 bool gfx_flush_in_progress : 1;
961 bool gfx_last_ib_is_busy : 1;
962 bool compute_is_busy : 1;
963
964 unsigned num_gfx_cs_flushes;
965 unsigned initial_gfx_cs_size;
966 unsigned last_dirty_tex_counter;
967 unsigned last_dirty_buf_counter;
968 unsigned last_compressed_colortex_counter;
969 unsigned last_num_draw_calls;
970 unsigned flags; /* flush flags */
971 /* Current unaccounted memory usage. */
972 uint64_t vram;
973 uint64_t gtt;
974
975 /* Compute-based primitive discard. */
976 unsigned prim_discard_vertex_count_threshold;
977 struct pb_buffer *gds;
978 struct pb_buffer *gds_oa;
979 struct radeon_cmdbuf *prim_discard_compute_cs;
980 unsigned compute_gds_offset;
981 struct si_shader *compute_ib_last_shader;
982 uint32_t compute_rewind_va;
983 unsigned compute_num_prims_in_batch;
984 bool preserve_prim_restart_gds_at_flush;
985 /* index_ring is divided into 2 halves for doublebuffering. */
986 struct si_resource *index_ring;
987 unsigned index_ring_base; /* offset of a per-IB portion */
988 unsigned index_ring_offset; /* offset within a per-IB portion */
989 unsigned index_ring_size_per_ib; /* max available size per IB */
990 bool prim_discard_compute_ib_initialized;
991 /* For tracking the last execution barrier - it can be either
992 * a WRITE_DATA packet or a fence. */
993 uint32_t *last_pkt3_write_data;
994 struct si_resource *barrier_buf;
995 unsigned barrier_buf_offset;
996 struct pipe_fence_handle *last_ib_barrier_fence;
997 struct si_resource *last_ib_barrier_buf;
998 unsigned last_ib_barrier_buf_offset;
999
1000 /* Atoms (direct states). */
1001 union si_state_atoms atoms;
1002 unsigned dirty_atoms; /* mask */
1003 /* PM4 states (precomputed immutable states) */
1004 unsigned dirty_states;
1005 union si_state queued;
1006 union si_state emitted;
1007
1008 /* Atom declarations. */
1009 struct si_framebuffer framebuffer;
1010 unsigned sample_locs_num_samples;
1011 uint16_t sample_mask;
1012 unsigned last_cb_target_mask;
1013 struct si_blend_color blend_color;
1014 struct si_clip_state clip_state;
1015 struct si_shader_data shader_pointers;
1016 struct si_stencil_ref stencil_ref;
1017 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
1018 struct si_streamout streamout;
1019 struct si_viewports viewports;
1020 unsigned num_window_rectangles;
1021 bool window_rectangles_include;
1022 struct pipe_scissor_state window_rectangles[4];
1023
1024 /* Precomputed states. */
1025 struct si_pm4_state *cs_preamble_state;
1026 struct si_pm4_state *cs_preamble_tess_rings;
1027 struct si_pm4_state *cs_preamble_tess_rings_tmz;
1028 struct si_pm4_state *cs_preamble_gs_rings;
1029 bool cs_preamble_has_vgt_flush;
1030 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
1031
1032 /* shaders */
1033 struct si_shader_ctx_state ps_shader;
1034 struct si_shader_ctx_state gs_shader;
1035 struct si_shader_ctx_state vs_shader;
1036 struct si_shader_ctx_state tcs_shader;
1037 struct si_shader_ctx_state tes_shader;
1038 struct si_shader_ctx_state cs_prim_discard_state;
1039 struct si_cs_shader_state cs_shader_state;
1040
1041 /* shader information */
1042 struct si_vertex_elements *vertex_elements;
1043 unsigned num_vertex_elements;
1044 unsigned sprite_coord_enable;
1045 unsigned cs_max_waves_per_sh;
1046 bool flatshade;
1047 bool do_update_shaders;
1048 bool compute_shaderbuf_sgprs_dirty;
1049 bool compute_image_sgprs_dirty;
1050
1051 /* shader descriptors */
1052 struct si_descriptors descriptors[SI_NUM_DESCS];
1053 unsigned descriptors_dirty;
1054 unsigned shader_pointers_dirty;
1055 unsigned shader_needs_decompress_mask;
1056 unsigned shader_has_inlinable_uniforms_mask;
1057 unsigned inlinable_uniforms_dirty_mask;
1058 unsigned inlinable_uniforms_valid_mask;
1059 uint32_t inlinable_uniforms[SI_NUM_SHADERS][MAX_INLINABLE_UNIFORMS];
1060 struct si_buffer_resources rw_buffers;
1061 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1062 struct si_samplers samplers[SI_NUM_SHADERS];
1063 struct si_images images[SI_NUM_SHADERS];
1064 bool bo_list_add_all_resident_resources;
1065 bool bo_list_add_all_gfx_resources;
1066 bool bo_list_add_all_compute_resources;
1067
1068 /* other shader resources */
1069 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1070 struct pipe_resource *esgs_ring;
1071 struct pipe_resource *gsvs_ring;
1072 struct pipe_resource *tess_rings;
1073 struct pipe_resource *tess_rings_tmz;
1074 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1075 struct si_resource *border_color_buffer;
1076 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1077 unsigned border_color_count;
1078 unsigned num_vs_blit_sgprs;
1079 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1080 uint32_t cs_user_data[4];
1081
1082 /* Vertex buffers. */
1083 bool vertex_buffers_dirty;
1084 bool vertex_buffer_pointer_dirty;
1085 bool vertex_buffer_user_sgprs_dirty;
1086 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1087 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1088 uint32_t *vb_descriptors_gpu_list;
1089 struct si_resource *vb_descriptors_buffer;
1090 unsigned vb_descriptors_offset;
1091 unsigned vb_descriptor_user_sgprs[5 * 4];
1092
1093 /* MSAA config state. */
1094 int ps_iter_samples;
1095 bool ps_uses_fbfetch;
1096 bool smoothing_enabled;
1097
1098 /* DB render state. */
1099 unsigned ps_db_shader_control;
1100 unsigned dbcb_copy_sample;
1101 bool dbcb_depth_copy_enabled : 1;
1102 bool dbcb_stencil_copy_enabled : 1;
1103 bool db_flush_depth_inplace : 1;
1104 bool db_flush_stencil_inplace : 1;
1105 bool db_depth_clear : 1;
1106 bool db_depth_disable_expclear : 1;
1107 bool db_stencil_clear : 1;
1108 bool db_stencil_disable_expclear : 1;
1109 bool occlusion_queries_disabled : 1;
1110 bool generate_mipmap_for_depth : 1;
1111
1112 /* Emitted draw state. */
1113 bool gs_tri_strip_adj_fix : 1;
1114 bool ls_vgpr_fix : 1;
1115 bool prim_discard_cs_instancing : 1;
1116 bool ngg : 1;
1117 uint8_t ngg_culling;
1118 int last_index_size;
1119 int last_base_vertex;
1120 int last_start_instance;
1121 int last_instance_count;
1122 int last_drawid;
1123 int last_sh_base_reg;
1124 int last_primitive_restart_en;
1125 int last_restart_index;
1126 int last_prim;
1127 int last_multi_vgt_param;
1128 int last_gs_out_prim;
1129 int last_binning_enabled;
1130 unsigned current_vs_state;
1131 unsigned last_vs_state;
1132 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1133
1134 struct si_small_prim_cull_info last_small_prim_cull_info;
1135 struct si_resource *small_prim_cull_info_buf;
1136 uint64_t small_prim_cull_info_address;
1137
1138 /* Scratch buffer */
1139 struct si_resource *scratch_buffer;
1140 unsigned scratch_waves;
1141 unsigned spi_tmpring_size;
1142 unsigned max_seen_scratch_bytes_per_wave;
1143 unsigned max_seen_compute_scratch_bytes_per_wave;
1144
1145 struct si_resource *compute_scratch_buffer;
1146
1147 /* Emitted derived tessellation state. */
1148 /* Local shader (VS), or HS if LS-HS are merged. */
1149 struct si_shader *last_ls;
1150 struct si_shader_selector *last_tcs;
1151 int last_num_tcs_input_cp;
1152 int last_tes_sh_base;
1153 bool last_tess_uses_primid;
1154 unsigned last_num_patches;
1155 int last_ls_hs_config;
1156
1157 /* Debug state. */
1158 bool is_debug;
1159 struct si_saved_cs *current_saved_cs;
1160 uint64_t dmesg_timestamp;
1161 unsigned apitrace_call_number;
1162
1163 /* Other state */
1164 bool need_check_render_feedback;
1165 bool decompression_enabled;
1166 bool dpbb_force_off;
1167 bool vs_writes_viewport_index;
1168 bool vs_disables_clipping_viewport;
1169
1170 /* Precomputed IA_MULTI_VGT_PARAM */
1171 union si_vgt_param_key ia_multi_vgt_param_key;
1172 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1173
1174 /* Bindless descriptors. */
1175 struct si_descriptors bindless_descriptors;
1176 struct util_idalloc bindless_used_slots;
1177 unsigned num_bindless_descriptors;
1178 bool bindless_descriptors_dirty;
1179 bool graphics_bindless_pointer_dirty;
1180 bool compute_bindless_pointer_dirty;
1181
1182 /* Allocated bindless handles */
1183 struct hash_table *tex_handles;
1184 struct hash_table *img_handles;
1185
1186 /* Resident bindless handles */
1187 struct util_dynarray resident_tex_handles;
1188 struct util_dynarray resident_img_handles;
1189
1190 /* Resident bindless handles which need decompression */
1191 struct util_dynarray resident_tex_needs_color_decompress;
1192 struct util_dynarray resident_img_needs_color_decompress;
1193 struct util_dynarray resident_tex_needs_depth_decompress;
1194
1195 /* Bindless state */
1196 bool uses_bindless_samplers;
1197 bool uses_bindless_images;
1198
1199 /* MSAA sample locations.
1200 * The first index is the sample index.
1201 * The second index is the coordinate: X, Y. */
1202 struct {
1203 float x1[1][2];
1204 float x2[2][2];
1205 float x4[4][2];
1206 float x8[8][2];
1207 float x16[16][2];
1208 } sample_positions;
1209 struct pipe_resource *sample_pos_buffer;
1210
1211 /* Misc stats. */
1212 unsigned num_draw_calls;
1213 unsigned num_decompress_calls;
1214 unsigned num_mrt_draw_calls;
1215 unsigned num_prim_restart_calls;
1216 unsigned num_spill_draw_calls;
1217 unsigned num_compute_calls;
1218 unsigned num_spill_compute_calls;
1219 unsigned num_dma_calls;
1220 unsigned num_cp_dma_calls;
1221 unsigned num_vs_flushes;
1222 unsigned num_ps_flushes;
1223 unsigned num_cs_flushes;
1224 unsigned num_cb_cache_flushes;
1225 unsigned num_db_cache_flushes;
1226 unsigned num_L2_invalidates;
1227 unsigned num_L2_writebacks;
1228 unsigned num_resident_handles;
1229 uint64_t num_alloc_tex_transfer_bytes;
1230 unsigned last_tex_ps_draw_ratio; /* for query */
1231 unsigned compute_num_verts_accepted;
1232 unsigned compute_num_verts_rejected;
1233 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1234 unsigned context_roll;
1235
1236 /* Queries. */
1237 /* Maintain the list of active queries for pausing between IBs. */
1238 int num_occlusion_queries;
1239 int num_perfect_occlusion_queries;
1240 int num_pipeline_stat_queries;
1241 struct list_head active_queries;
1242 unsigned num_cs_dw_queries_suspend;
1243
1244 /* Render condition. */
1245 struct pipe_query *render_cond;
1246 unsigned render_cond_mode;
1247 bool render_cond_invert;
1248 bool render_cond_force_off; /* for u_blitter */
1249
1250 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1251 bool sdma_uploads_in_progress;
1252 struct si_sdma_upload *sdma_uploads;
1253 unsigned num_sdma_uploads;
1254 unsigned max_sdma_uploads;
1255
1256 /* Shader-based queries. */
1257 struct list_head shader_query_buffers;
1258 unsigned num_active_shader_queries;
1259
1260 /* Statistics gathering for the DCC enablement heuristic. It can't be
1261 * in si_texture because si_texture can be shared by multiple
1262 * contexts. This is for back buffers only. We shouldn't get too many
1263 * of those.
1264 *
1265 * X11 DRI3 rotates among a finite set of back buffers. They should
1266 * all fit in this array. If they don't, separate DCC might never be
1267 * enabled by DCC stat gathering.
1268 */
1269 struct {
1270 struct si_texture *tex;
1271 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1272 struct pipe_query *ps_stats[3];
1273 /* If all slots are used and another slot is needed,
1274 * the least recently used slot is evicted based on this. */
1275 int64_t last_use_timestamp;
1276 bool query_active;
1277 } dcc_stats[5];
1278
1279 /* Copy one resource to another using async DMA. */
1280 void (*dma_copy)(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dst_level,
1281 unsigned dst_x, unsigned dst_y, unsigned dst_z, struct pipe_resource *src,
1282 unsigned src_level, const struct pipe_box *src_box);
1283
1284 struct si_tracked_regs tracked_regs;
1285 };
1286
1287 /* cik_sdma.c */
1288 void cik_init_sdma_functions(struct si_context *sctx);
1289
1290 /* si_blit.c */
1291 enum si_blitter_op /* bitmask */
1292 {
1293 SI_SAVE_TEXTURES = 1,
1294 SI_SAVE_FRAMEBUFFER = 2,
1295 SI_SAVE_FRAGMENT_STATE = 4,
1296 SI_DISABLE_RENDER_COND = 8,
1297 };
1298
1299 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1300 void si_blitter_end(struct si_context *sctx);
1301 void si_init_blit_functions(struct si_context *sctx);
1302 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1303 void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
1304 unsigned level, unsigned first_layer, unsigned last_layer);
1305 void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
1306 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1307 struct pipe_resource *src, unsigned src_level,
1308 const struct pipe_box *src_box);
1309 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1310
1311 /* si_buffer.c */
1312 bool si_rings_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf,
1313 enum radeon_bo_usage usage);
1314 void *si_buffer_map_sync_with_rings(struct si_context *sctx, struct si_resource *resource,
1315 unsigned usage);
1316 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1317 unsigned alignment);
1318 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1319 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1320 unsigned usage, unsigned size, unsigned alignment);
1321 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1322 unsigned usage, unsigned size, unsigned alignment);
1323 void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst,
1324 struct pipe_resource *src);
1325 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1326 void si_init_buffer_functions(struct si_context *sctx);
1327
1328 /* si_clear.c */
1329 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1330 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1331 bool vi_dcc_clear_level(struct si_context *sctx, struct si_texture *tex, unsigned level,
1332 unsigned clear_value);
1333 void si_init_clear_functions(struct si_context *sctx);
1334
1335 /* si_compute_blit.c */
1336 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1337 enum si_cache_policy cache_policy);
1338 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset,
1339 uint64_t size, uint32_t *clear_value, uint32_t clear_value_size,
1340 enum si_coherency coher, bool force_cpdma);
1341 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1342 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1343 void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1344 struct pipe_resource *src, unsigned src_level, unsigned dstx,
1345 unsigned dsty, unsigned dstz, const struct pipe_box *src_box,
1346 bool is_dcc_decompress);
1347 void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dstsurf,
1348 const union pipe_color_union *color, unsigned dstx,
1349 unsigned dsty, unsigned width, unsigned height,
1350 bool render_condition_enabled);
1351 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1352 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1353 void si_init_compute_blit_functions(struct si_context *sctx);
1354
1355 /* si_cp_dma.c */
1356 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1357 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1358 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1359 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1360 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1361 #define SI_CPDMA_SKIP_TMZ (1 << 5) /* don't update tmz state */
1362 #define SI_CPDMA_SKIP_ALL \
1363 (SI_CPDMA_SKIP_CHECK_CS_SPACE | SI_CPDMA_SKIP_SYNC_AFTER | SI_CPDMA_SKIP_SYNC_BEFORE | \
1364 SI_CPDMA_SKIP_GFX_SYNC | SI_CPDMA_SKIP_BO_LIST_UPDATE | SI_CPDMA_SKIP_TMZ)
1365
1366 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1367 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1368 struct pipe_resource *dst, uint64_t offset, uint64_t size,
1369 unsigned value, unsigned user_flags, enum si_coherency coher,
1370 enum si_cache_policy cache_policy);
1371 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1372 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1373 unsigned size, unsigned user_flags, enum si_coherency coher,
1374 enum si_cache_policy cache_policy);
1375 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf, uint64_t offset,
1376 unsigned size);
1377 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1378 void si_test_gds(struct si_context *sctx);
1379 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1380 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1381 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1382 struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
1383 struct si_resource *src, unsigned src_offset);
1384
1385 /* si_cp_reg_shadowing.c */
1386 void si_init_cp_reg_shadowing(struct si_context *sctx);
1387
1388 /* si_debug.c */
1389 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1390 bool get_buffer_list);
1391 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1392 void si_destroy_saved_cs(struct si_saved_cs *scs);
1393 void si_auto_log_cs(void *data, struct u_log_context *log);
1394 void si_log_hw_flush(struct si_context *sctx);
1395 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1396 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1397 void si_init_debug_functions(struct si_context *sctx);
1398 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved,
1399 enum ring_type ring);
1400 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1401
1402 /* si_dma_cs.c */
1403 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst, uint64_t offset);
1404 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset,
1405 uint64_t size, unsigned clear_value);
1406 void si_sdma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1407 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1408 uint64_t size);
1409 void si_need_dma_space(struct si_context *ctx, unsigned num_dw, struct si_resource *dst,
1410 struct si_resource *src);
1411 void si_flush_dma_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1412 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset,
1413 uint64_t size, unsigned value);
1414
1415 /* si_fence.c */
1416 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1417 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1418 struct si_resource *buf, uint64_t va, uint32_t new_fence,
1419 unsigned query_type);
1420 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1421 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1422 uint32_t mask, unsigned flags);
1423 void si_init_fence_functions(struct si_context *ctx);
1424 void si_init_screen_fence_functions(struct si_screen *screen);
1425 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1426 struct tc_unflushed_batch_token *tc_token);
1427
1428 /* si_get.c */
1429 void si_init_screen_get_functions(struct si_screen *sscreen);
1430
1431 /* si_gfx_cs.c */
1432 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1433 void si_allocate_gds(struct si_context *ctx);
1434 void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
1435 void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs);
1436 void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws);
1437 void si_unref_sdma_uploads(struct si_context *sctx);
1438
1439 /* si_gpu_load.c */
1440 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1441 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1442 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1443
1444 /* si_compute.c */
1445 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1446 void si_init_compute_functions(struct si_context *sctx);
1447
1448 /* si_compute_prim_discard.c */
1449 enum si_prim_discard_outcome
1450 {
1451 SI_PRIM_DISCARD_ENABLED,
1452 SI_PRIM_DISCARD_DISABLED,
1453 SI_PRIM_DISCARD_DRAW_SPLIT,
1454 SI_PRIM_DISCARD_MULTI_DRAW_SPLIT,
1455 };
1456
1457 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1458 enum si_prim_discard_outcome
1459 si_prepare_prim_discard_or_split_draw(struct si_context *sctx, const struct pipe_draw_info *info,
1460 const struct pipe_draw_start_count *draws,
1461 unsigned num_draws, bool primitive_restart,
1462 unsigned total_count);
1463 void si_compute_signal_gfx(struct si_context *sctx);
1464 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1465 const struct pipe_draw_info *info,
1466 unsigned count, unsigned index_size,
1467 unsigned base_vertex, uint64_t input_indexbuf_va,
1468 unsigned input_indexbuf_max_elements);
1469 void si_initialize_prim_discard_tunables(struct si_screen *sscreen, bool is_aux_context,
1470 unsigned *prim_discard_vertex_count_threshold,
1471 unsigned *index_ring_size_per_ib);
1472
1473 /* si_pipe.c */
1474 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler);
1475
1476 /* si_perfcounters.c */
1477 void si_init_perfcounters(struct si_screen *screen);
1478 void si_destroy_perfcounters(struct si_screen *screen);
1479
1480 /* si_query.c */
1481 void si_init_screen_query_functions(struct si_screen *sscreen);
1482 void si_init_query_functions(struct si_context *sctx);
1483 void si_suspend_queries(struct si_context *sctx);
1484 void si_resume_queries(struct si_context *sctx);
1485
1486 /* si_shaderlib_tgsi.c */
1487 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1488 unsigned num_layers);
1489 void *si_create_fixed_func_tcs(struct si_context *sctx);
1490 void *si_create_dma_compute_shader(struct pipe_context *ctx, unsigned num_dwords_per_thread,
1491 bool dst_stream_cache_policy, bool is_copy);
1492 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1493 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1494 void *si_create_dcc_decompress_cs(struct pipe_context *ctx);
1495 void *si_clear_render_target_shader(struct pipe_context *ctx);
1496 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1497 void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx);
1498 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1499 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples, bool is_array);
1500 void *si_create_query_result_cs(struct si_context *sctx);
1501 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1502
1503 /* gfx10_query.c */
1504 void gfx10_init_query(struct si_context *sctx);
1505 void gfx10_destroy_query(struct si_context *sctx);
1506
1507 /* si_test_dma.c */
1508 void si_test_dma(struct si_screen *sscreen);
1509
1510 /* si_test_clearbuffer.c */
1511 void si_test_dma_perf(struct si_screen *sscreen);
1512
1513 /* si_uvd.c */
1514 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1515 const struct pipe_video_codec *templ);
1516
1517 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1518 const struct pipe_video_buffer *tmpl);
1519
1520 /* si_viewport.c */
1521 void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_cull_info *out);
1522 void si_update_vs_viewport_state(struct si_context *ctx);
1523 void si_init_viewport_functions(struct si_context *ctx);
1524
1525 /* si_texture.c */
1526 bool si_prepare_for_dma_blit(struct si_context *sctx, struct si_texture *dst, unsigned dst_level,
1527 unsigned dstx, unsigned dsty, unsigned dstz, struct si_texture *src,
1528 unsigned src_level, const struct pipe_box *src_box);
1529 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1530 bool *ctx_flushed);
1531 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex);
1532 bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture);
1533 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
1534 struct u_log_context *log);
1535 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1536 const struct pipe_resource *templ);
1537 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1,
1538 enum pipe_format format2);
1539 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level,
1540 enum pipe_format view_format);
1541 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1542 unsigned level, enum pipe_format view_format);
1543 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1544 struct pipe_resource *texture,
1545 const struct pipe_surface *templ, unsigned width0,
1546 unsigned height0, unsigned width, unsigned height);
1547 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1548 void vi_separate_dcc_try_enable(struct si_context *sctx, struct si_texture *tex);
1549 void vi_separate_dcc_start_query(struct si_context *sctx, struct si_texture *tex);
1550 void vi_separate_dcc_stop_query(struct si_context *sctx, struct si_texture *tex);
1551 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx, struct si_texture *tex);
1552 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1553 void si_init_screen_texture_functions(struct si_screen *sscreen);
1554 void si_init_context_texture_functions(struct si_context *sctx);
1555
1556 /*
1557 * common helpers
1558 */
1559
si_resource(struct pipe_resource * r)1560 static inline struct si_resource *si_resource(struct pipe_resource *r)
1561 {
1562 return (struct si_resource *)r;
1563 }
1564
si_resource_reference(struct si_resource ** ptr,struct si_resource * res)1565 static inline void si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1566 {
1567 pipe_resource_reference((struct pipe_resource **)ptr, (struct pipe_resource *)res);
1568 }
1569
si_texture_reference(struct si_texture ** ptr,struct si_texture * res)1570 static inline void si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1571 {
1572 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1573 }
1574
1575 static inline void
si_shader_selector_reference(struct si_context * sctx,struct si_shader_selector ** dst,struct si_shader_selector * src)1576 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */
1577 struct si_shader_selector **dst, struct si_shader_selector *src)
1578 {
1579 if (*dst == src)
1580 return;
1581
1582 struct si_screen *sscreen = src ? src->screen : (*dst)->screen;
1583 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src);
1584 }
1585
vi_dcc_enabled(struct si_texture * tex,unsigned level)1586 static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level)
1587 {
1588 return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels;
1589 }
1590
si_tile_mode_index(struct si_texture * tex,unsigned level,bool stencil)1591 static inline unsigned si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1592 {
1593 if (stencil)
1594 return tex->surface.u.legacy.stencil_tiling_index[level];
1595 else
1596 return tex->surface.u.legacy.tiling_index[level];
1597 }
1598
si_get_minimum_num_gfx_cs_dwords(struct si_context * sctx,unsigned num_draws)1599 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx,
1600 unsigned num_draws)
1601 {
1602 /* Don't count the needed CS space exactly and just use an upper bound.
1603 *
1604 * Also reserve space for stopping queries at the end of IB, because
1605 * the number of active queries is unlimited in theory.
1606 *
1607 * Both indexed and non-indexed draws use 6 dwords per draw.
1608 */
1609 return 2048 + sctx->num_cs_dw_queries_suspend + num_draws * 6;
1610 }
1611
si_context_add_resource_size(struct si_context * sctx,struct pipe_resource * r)1612 static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1613 {
1614 if (r) {
1615 /* Add memory usage for need_gfx_cs_space */
1616 sctx->vram += si_resource(r)->vram_usage;
1617 sctx->gtt += si_resource(r)->gart_usage;
1618 }
1619 }
1620
si_invalidate_draw_sh_constants(struct si_context * sctx)1621 static inline void si_invalidate_draw_sh_constants(struct si_context *sctx)
1622 {
1623 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1624 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1625 }
1626
si_get_atom_bit(struct si_context * sctx,struct si_atom * atom)1627 static inline unsigned si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1628 {
1629 return 1 << (atom - sctx->atoms.array);
1630 }
1631
si_set_atom_dirty(struct si_context * sctx,struct si_atom * atom,bool dirty)1632 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1633 {
1634 unsigned bit = si_get_atom_bit(sctx, atom);
1635
1636 if (dirty)
1637 sctx->dirty_atoms |= bit;
1638 else
1639 sctx->dirty_atoms &= ~bit;
1640 }
1641
si_is_atom_dirty(struct si_context * sctx,struct si_atom * atom)1642 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1643 {
1644 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1645 }
1646
si_mark_atom_dirty(struct si_context * sctx,struct si_atom * atom)1647 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1648 {
1649 si_set_atom_dirty(sctx, atom, true);
1650 }
1651
si_get_vs(struct si_context * sctx)1652 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1653 {
1654 if (sctx->gs_shader.cso)
1655 return &sctx->gs_shader;
1656 if (sctx->tes_shader.cso)
1657 return &sctx->tes_shader;
1658
1659 return &sctx->vs_shader;
1660 }
1661
si_get_vs_info(struct si_context * sctx)1662 static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
1663 {
1664 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1665
1666 return vs->cso ? &vs->cso->info : NULL;
1667 }
1668
si_get_vs_state(struct si_context * sctx)1669 static inline struct si_shader *si_get_vs_state(struct si_context *sctx)
1670 {
1671 if (sctx->gs_shader.cso && sctx->gs_shader.current && !sctx->gs_shader.current->key.as_ngg)
1672 return sctx->gs_shader.cso->gs_copy_shader;
1673
1674 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1675 return vs->current ? vs->current : NULL;
1676 }
1677
si_can_dump_shader(struct si_screen * sscreen,gl_shader_stage stage)1678 static inline bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage)
1679 {
1680 return sscreen->debug_flags & (1 << stage);
1681 }
1682
si_get_strmout_en(struct si_context * sctx)1683 static inline bool si_get_strmout_en(struct si_context *sctx)
1684 {
1685 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;
1686 }
1687
si_optimal_tcc_alignment(struct si_context * sctx,unsigned upload_size)1688 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1689 {
1690 unsigned alignment, tcc_cache_line_size;
1691
1692 /* If the upload size is less than the cache line size (e.g. 16, 32),
1693 * the whole thing will fit into a cache line if we align it to its size.
1694 * The idea is that multiple small uploads can share a cache line.
1695 * If the upload size is greater, align it to the cache line size.
1696 */
1697 alignment = util_next_power_of_two(upload_size);
1698 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1699 return MIN2(alignment, tcc_cache_line_size);
1700 }
1701
si_saved_cs_reference(struct si_saved_cs ** dst,struct si_saved_cs * src)1702 static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1703 {
1704 if (pipe_reference(&(*dst)->reference, &src->reference))
1705 si_destroy_saved_cs(*dst);
1706
1707 *dst = src;
1708 }
1709
si_make_CB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool shaders_read_metadata,bool dcc_pipe_aligned)1710 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1711 bool shaders_read_metadata, bool dcc_pipe_aligned)
1712 {
1713 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE;
1714
1715 if (sctx->chip_class >= GFX10) {
1716 if (sctx->screen->info.tcc_harvested)
1717 sctx->flags |= SI_CONTEXT_INV_L2;
1718 else if (shaders_read_metadata)
1719 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1720 } else if (sctx->chip_class == GFX9) {
1721 /* Single-sample color is coherent with shaders on GFX9, but
1722 * L2 metadata must be flushed if shaders read metadata.
1723 * (DCC, CMASK).
1724 */
1725 if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned))
1726 sctx->flags |= SI_CONTEXT_INV_L2;
1727 else if (shaders_read_metadata)
1728 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1729 } else {
1730 /* GFX6-GFX8 */
1731 sctx->flags |= SI_CONTEXT_INV_L2;
1732 }
1733 }
1734
si_make_DB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool include_stencil,bool shaders_read_metadata)1735 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1736 bool include_stencil, bool shaders_read_metadata)
1737 {
1738 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
1739
1740 if (sctx->chip_class >= GFX10) {
1741 if (sctx->screen->info.tcc_harvested)
1742 sctx->flags |= SI_CONTEXT_INV_L2;
1743 else if (shaders_read_metadata)
1744 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1745 } else if (sctx->chip_class == GFX9) {
1746 /* Single-sample depth (not stencil) is coherent with shaders
1747 * on GFX9, but L2 metadata must be flushed if shaders read
1748 * metadata.
1749 */
1750 if (num_samples >= 2 || include_stencil)
1751 sctx->flags |= SI_CONTEXT_INV_L2;
1752 else if (shaders_read_metadata)
1753 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1754 } else {
1755 /* GFX6-GFX8 */
1756 sctx->flags |= SI_CONTEXT_INV_L2;
1757 }
1758 }
1759
si_can_sample_zs(struct si_texture * tex,bool stencil_sampler)1760 static inline bool si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1761 {
1762 return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z);
1763 }
1764
si_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1765 static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1766 {
1767 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1768 return false;
1769
1770 return tex->surface.htile_offset && level == 0;
1771 }
1772
vi_tc_compat_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1773 static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,
1774 unsigned zs_mask)
1775 {
1776 assert(!tex->tc_compatible_htile || tex->surface.htile_offset);
1777 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1778 }
1779
si_get_ps_iter_samples(struct si_context * sctx)1780 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1781 {
1782 if (sctx->ps_uses_fbfetch)
1783 return sctx->framebuffer.nr_color_samples;
1784
1785 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1786 }
1787
si_get_total_colormask(struct si_context * sctx)1788 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1789 {
1790 if (sctx->queued.named.rasterizer->rasterizer_discard)
1791 return 0;
1792
1793 struct si_shader_selector *ps = sctx->ps_shader.cso;
1794 if (!ps)
1795 return 0;
1796
1797 unsigned colormask =
1798 sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask;
1799
1800 if (!ps->info.color0_writes_all_cbufs)
1801 colormask &= ps->colors_written_4bit;
1802 else if (!ps->colors_written_4bit)
1803 colormask = 0; /* color0 writes all cbufs, but it's not written */
1804
1805 return colormask;
1806 }
1807
1808 #define UTIL_ALL_PRIM_LINE_MODES \
1809 ((1 << PIPE_PRIM_LINES) | (1 << PIPE_PRIM_LINE_LOOP) | (1 << PIPE_PRIM_LINE_STRIP) | \
1810 (1 << PIPE_PRIM_LINES_ADJACENCY) | (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1811
util_prim_is_lines(unsigned prim)1812 static inline bool util_prim_is_lines(unsigned prim)
1813 {
1814 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1815 }
1816
util_prim_is_points_or_lines(unsigned prim)1817 static inline bool util_prim_is_points_or_lines(unsigned prim)
1818 {
1819 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | (1 << PIPE_PRIM_POINTS))) != 0;
1820 }
1821
util_rast_prim_is_triangles(unsigned prim)1822 static inline bool util_rast_prim_is_triangles(unsigned prim)
1823 {
1824 return ((1 << prim) &
1825 ((1 << PIPE_PRIM_TRIANGLES) | (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1826 (1 << PIPE_PRIM_TRIANGLE_FAN) | (1 << PIPE_PRIM_QUADS) | (1 << PIPE_PRIM_QUAD_STRIP) |
1827 (1 << PIPE_PRIM_POLYGON) | (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1828 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1829 }
1830
1831 /**
1832 * Return true if there is enough memory in VRAM and GTT for the buffers
1833 * added so far.
1834 *
1835 * \param vram VRAM memory size not added to the buffer list yet
1836 * \param gtt GTT memory size not added to the buffer list yet
1837 */
radeon_cs_memory_below_limit(struct si_screen * screen,struct radeon_cmdbuf * cs,uint64_t vram,uint64_t gtt)1838 static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, struct radeon_cmdbuf *cs,
1839 uint64_t vram, uint64_t gtt)
1840 {
1841 vram += cs->used_vram;
1842 gtt += cs->used_gart;
1843
1844 /* Anything that goes above the VRAM size should go to GTT. */
1845 if (vram > screen->info.vram_size)
1846 gtt += vram - screen->info.vram_size;
1847
1848 /* Now we just need to check if we have enough GTT. */
1849 return gtt < screen->info.gart_size * 0.7;
1850 }
1851
1852 /**
1853 * Add a buffer to the buffer list for the given command stream (CS).
1854 *
1855 * All buffers used by a CS must be added to the list. This tells the kernel
1856 * driver which buffers are used by GPU commands. Other buffers can
1857 * be swapped out (not accessible) during execution.
1858 *
1859 * The buffer list becomes empty after every context flush and must be
1860 * rebuilt.
1861 */
radeon_add_to_buffer_list(struct si_context * sctx,struct radeon_cmdbuf * cs,struct si_resource * bo,enum radeon_bo_usage usage,enum radeon_bo_priority priority)1862 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
1863 struct si_resource *bo, enum radeon_bo_usage usage,
1864 enum radeon_bo_priority priority)
1865 {
1866 assert(usage);
1867 sctx->ws->cs_add_buffer(cs, bo->buf, (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1868 bo->domains, priority);
1869 }
1870
1871 /**
1872 * Same as above, but also checks memory usage and flushes the context
1873 * accordingly.
1874 *
1875 * When this SHOULD NOT be used:
1876 *
1877 * - if si_context_add_resource_size has been called for the buffer
1878 * followed by *_need_cs_space for checking the memory usage
1879 *
1880 * - if si_need_dma_space has been called for the buffer
1881 *
1882 * - when emitting state packets and draw packets (because preceding packets
1883 * can't be re-emitted at that point)
1884 *
1885 * - if shader resource "enabled_mask" is not up-to-date or there is
1886 * a different constraint disallowing a context flush
1887 */
radeon_add_to_gfx_buffer_list_check_mem(struct si_context * sctx,struct si_resource * bo,enum radeon_bo_usage usage,enum radeon_bo_priority priority,bool check_mem)1888 static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1889 struct si_resource *bo,
1890 enum radeon_bo_usage usage,
1891 enum radeon_bo_priority priority,
1892 bool check_mem)
1893 {
1894 if (check_mem &&
1895 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs, sctx->vram + bo->vram_usage,
1896 sctx->gtt + bo->gart_usage))
1897 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1898
1899 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1900 }
1901
si_compute_prim_discard_enabled(struct si_context * sctx)1902 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1903 {
1904 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1905 }
1906
si_get_wave_size(struct si_screen * sscreen,gl_shader_stage stage,bool ngg,bool es,bool gs_fast_launch,bool prim_discard_cs)1907 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1908 gl_shader_stage stage, bool ngg, bool es,
1909 bool gs_fast_launch, bool prim_discard_cs)
1910 {
1911 if (stage == MESA_SHADER_COMPUTE)
1912 return sscreen->compute_wave_size;
1913 else if (stage == MESA_SHADER_FRAGMENT)
1914 return sscreen->ps_wave_size;
1915 else if (gs_fast_launch)
1916 return 32; /* GS fast launch hangs with Wave64, so always use Wave32. */
1917 else if ((stage == MESA_SHADER_VERTEX && prim_discard_cs) || /* only Wave64 implemented */
1918 (stage == MESA_SHADER_VERTEX && es && !ngg) ||
1919 (stage == MESA_SHADER_TESS_EVAL && es && !ngg) ||
1920 (stage == MESA_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1921 return 64;
1922 else
1923 return sscreen->ge_wave_size;
1924 }
1925
si_get_shader_wave_size(struct si_shader * shader)1926 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1927 {
1928 return si_get_wave_size(shader->selector->screen, shader->selector->info.stage,
1929 shader->key.as_ngg,
1930 shader->key.as_es,
1931 shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL,
1932 shader->key.opt.vs_as_prim_discard_cs);
1933 }
1934
1935 /* Return the number of samples that the rasterizer uses. */
si_get_num_coverage_samples(struct si_context * sctx)1936 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx)
1937 {
1938 if (sctx->framebuffer.nr_samples > 1 &&
1939 sctx->queued.named.rasterizer->multisample_enable)
1940 return sctx->framebuffer.nr_samples;
1941
1942 /* Note that smoothing_enabled is set by si_update_shaders. */
1943 if (sctx->smoothing_enabled)
1944 return SI_NUM_SMOOTH_AA_SAMPLES;
1945
1946 return 1;
1947 }
1948
1949 #define PRINT_ERR(fmt, args...) \
1950 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1951
1952 struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
1953 const struct pipe_resource *templ,
1954 struct pb_buffer *imported_buf,
1955 bool dedicated);
1956
1957 #endif
1958