1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/format/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nv50/nv50_context.h"
30 #include "nv50/nv50_query_hw.h"
31 #include "nv50/nv50_resource.h"
32
33 #include "nv50/nv50_3d.xml.h"
34
35 void
nv50_vertex_state_delete(struct pipe_context * pipe,void * hwcso)36 nv50_vertex_state_delete(struct pipe_context *pipe,
37 void *hwcso)
38 {
39 struct nv50_vertex_stateobj *so = hwcso;
40
41 if (so->translate)
42 so->translate->release(so->translate);
43 FREE(hwcso);
44 }
45
46 void *
nv50_vertex_state_create(struct pipe_context * pipe,unsigned num_elements,const struct pipe_vertex_element * elements)47 nv50_vertex_state_create(struct pipe_context *pipe,
48 unsigned num_elements,
49 const struct pipe_vertex_element *elements)
50 {
51 struct nv50_vertex_stateobj *so;
52 struct translate_key transkey;
53 unsigned i;
54
55 so = MALLOC(sizeof(*so) +
56 num_elements * sizeof(struct nv50_vertex_element));
57 if (!so)
58 return NULL;
59 so->num_elements = num_elements;
60 so->instance_elts = 0;
61 so->instance_bufs = 0;
62 so->need_conversion = false;
63
64 memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
65
66 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
67 so->min_instance_div[i] = 0xffffffff;
68
69 transkey.nr_elements = 0;
70 transkey.output_stride = 0;
71
72 for (i = 0; i < num_elements; ++i) {
73 const struct pipe_vertex_element *ve = &elements[i];
74 const unsigned vbi = ve->vertex_buffer_index;
75 unsigned size;
76 enum pipe_format fmt = ve->src_format;
77
78 so->element[i].pipe = elements[i];
79 so->element[i].state = nv50_vertex_format[fmt].vtx;
80
81 if (!so->element[i].state) {
82 switch (util_format_get_nr_components(fmt)) {
83 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
84 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
85 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
86 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
87 default:
88 assert(0);
89 FREE(so);
90 return NULL;
91 }
92 so->element[i].state = nv50_vertex_format[fmt].vtx;
93 so->need_conversion = true;
94 pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
95 "Converting vertex element %d, no hw format %s",
96 i, util_format_name(ve->src_format));
97 }
98 so->element[i].state |= i;
99
100 size = util_format_get_blocksize(fmt);
101 if (so->vb_access_size[vbi] < (ve->src_offset + size))
102 so->vb_access_size[vbi] = ve->src_offset + size;
103
104 if (1) {
105 unsigned j = transkey.nr_elements++;
106
107 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
108 transkey.element[j].input_format = ve->src_format;
109 transkey.element[j].input_buffer = vbi;
110 transkey.element[j].input_offset = ve->src_offset;
111 transkey.element[j].instance_divisor = ve->instance_divisor;
112
113 transkey.element[j].output_format = fmt;
114 transkey.element[j].output_offset = transkey.output_stride;
115 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
116
117 if (unlikely(ve->instance_divisor)) {
118 so->instance_elts |= 1 << i;
119 so->instance_bufs |= 1 << vbi;
120 if (ve->instance_divisor < so->min_instance_div[vbi])
121 so->min_instance_div[vbi] = ve->instance_divisor;
122 }
123 }
124 }
125
126 so->translate = translate_create(&transkey);
127 so->vertex_size = transkey.output_stride / 4;
128 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
129 MAX2(so->vertex_size, 1);
130
131 return so;
132 }
133
134 #define NV50_3D_VERTEX_ATTRIB_INACTIVE \
135 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \
136 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
137 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
138
139 static void
nv50_emit_vtxattr(struct nv50_context * nv50,struct pipe_vertex_buffer * vb,struct pipe_vertex_element * ve,unsigned attr)140 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
141 struct pipe_vertex_element *ve, unsigned attr)
142 {
143 struct nouveau_pushbuf *push = nv50->base.pushbuf;
144 const void *data = (const uint8_t *)vb->buffer.user + ve->src_offset;
145 float v[4];
146 const unsigned nc = util_format_get_nr_components(ve->src_format);
147
148 assert(vb->is_user_buffer);
149
150 util_format_unpack_rgba(ve->src_format, v, data, 1);
151
152 switch (nc) {
153 case 4:
154 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
155 PUSH_DATAf(push, v[0]);
156 PUSH_DATAf(push, v[1]);
157 PUSH_DATAf(push, v[2]);
158 PUSH_DATAf(push, v[3]);
159 break;
160 case 3:
161 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
162 PUSH_DATAf(push, v[0]);
163 PUSH_DATAf(push, v[1]);
164 PUSH_DATAf(push, v[2]);
165 break;
166 case 2:
167 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
168 PUSH_DATAf(push, v[0]);
169 PUSH_DATAf(push, v[1]);
170 break;
171 case 1:
172 if (attr == nv50->vertprog->vp.edgeflag) {
173 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
174 PUSH_DATA (push, v[0] ? 1 : 0);
175 }
176 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
177 PUSH_DATAf(push, v[0]);
178 break;
179 default:
180 assert(0);
181 break;
182 }
183 }
184
185 static inline void
nv50_user_vbuf_range(struct nv50_context * nv50,unsigned vbi,uint32_t * base,uint32_t * size)186 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
187 uint32_t *base, uint32_t *size)
188 {
189 assert(vbi < PIPE_MAX_ATTRIBS);
190 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
191 /* TODO: use min and max instance divisor to get a proper range */
192 *base = 0;
193 *size = nv50->vtxbuf[vbi].buffer.resource->width0;
194 } else {
195 /* NOTE: if there are user buffers, we *must* have index bounds */
196 assert(nv50->vb_elt_limit != ~0);
197 *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
198 *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
199 nv50->vertex->vb_access_size[vbi];
200 }
201 }
202
203 static void
nv50_upload_user_buffers(struct nv50_context * nv50,uint64_t addrs[],uint32_t limits[])204 nv50_upload_user_buffers(struct nv50_context *nv50,
205 uint64_t addrs[], uint32_t limits[])
206 {
207 unsigned b;
208
209 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
210 for (b = 0; b < nv50->num_vtxbufs; ++b) {
211 struct nouveau_bo *bo;
212 const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
213 uint32_t base, size;
214
215 if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
216 continue;
217 nv50_user_vbuf_range(nv50, b, &base, &size);
218
219 limits[b] = base + size - 1;
220 addrs[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user, base, size,
221 &bo);
222 if (addrs[b])
223 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, NOUVEAU_BO_GART |
224 NOUVEAU_BO_RD, bo);
225 }
226 nv50->base.vbo_dirty = true;
227 }
228
229 static void
nv50_update_user_vbufs(struct nv50_context * nv50)230 nv50_update_user_vbufs(struct nv50_context *nv50)
231 {
232 uint64_t address[PIPE_MAX_ATTRIBS];
233 struct nouveau_pushbuf *push = nv50->base.pushbuf;
234 unsigned i;
235 uint32_t written = 0;
236
237 for (i = 0; i < nv50->vertex->num_elements; ++i) {
238 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
239 const unsigned b = ve->vertex_buffer_index;
240 struct pipe_vertex_buffer *vb;
241 uint32_t base, size;
242
243 assert(b < PIPE_MAX_ATTRIBS);
244 vb = &nv50->vtxbuf[b];
245
246 if (!(nv50->vbo_user & (1 << b)))
247 continue;
248
249 if (!vb->stride) {
250 nv50_emit_vtxattr(nv50, vb, ve, i);
251 continue;
252 }
253 nv50_user_vbuf_range(nv50, b, &base, &size);
254
255 if (!(written & (1 << b))) {
256 struct nouveau_bo *bo;
257 const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
258 written |= 1 << b;
259 address[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user,
260 base, size, &bo);
261 if (address[b])
262 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, bo_flags, bo);
263 }
264
265 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
266 PUSH_DATAh(push, address[b] + base + size - 1);
267 PUSH_DATA (push, address[b] + base + size - 1);
268 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
269 PUSH_DATAh(push, address[b] + ve->src_offset);
270 PUSH_DATA (push, address[b] + ve->src_offset);
271 }
272 nv50->base.vbo_dirty = true;
273 }
274
275 static inline void
nv50_release_user_vbufs(struct nv50_context * nv50)276 nv50_release_user_vbufs(struct nv50_context *nv50)
277 {
278 if (nv50->vbo_user) {
279 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX_TMP);
280 nouveau_scratch_done(&nv50->base);
281 }
282 }
283
284 void
nv50_vertex_arrays_validate(struct nv50_context * nv50)285 nv50_vertex_arrays_validate(struct nv50_context *nv50)
286 {
287 uint64_t addrs[PIPE_MAX_ATTRIBS];
288 uint32_t limits[PIPE_MAX_ATTRIBS];
289 struct nouveau_pushbuf *push = nv50->base.pushbuf;
290 struct nv50_vertex_stateobj *vertex = nv50->vertex;
291 struct pipe_vertex_buffer *vb;
292 struct nv50_vertex_element *ve;
293 uint32_t mask;
294 uint32_t refd = 0;
295 unsigned i;
296 const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
297
298 if (unlikely(vertex->need_conversion))
299 nv50->vbo_fifo = ~0;
300 else
301 if (nv50->vbo_user & ~nv50->vbo_constant)
302 nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
303 else
304 nv50->vbo_fifo = 0;
305
306 if (!nv50->vbo_fifo) {
307 /* if vertex buffer was written by GPU - flush VBO cache */
308 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
309 for (i = 0; i < nv50->num_vtxbufs; ++i) {
310 struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer.resource);
311 if (!nv50->vtxbuf[i].is_user_buffer &&
312 buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
313 buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
314 nv50->base.vbo_dirty = true;
315 }
316 }
317 }
318
319 /* update vertex format state */
320 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
321 if (nv50->vbo_fifo) {
322 nv50->state.num_vtxelts = vertex->num_elements;
323 for (i = 0; i < vertex->num_elements; ++i)
324 PUSH_DATA (push, vertex->element[i].state);
325 for (; i < n; ++i)
326 PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
327 for (i = 0; i < n; ++i) {
328 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
329 PUSH_DATA (push, 0);
330 }
331 return;
332 }
333 for (i = 0; i < vertex->num_elements; ++i) {
334 const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
335
336 assert(b < PIPE_MAX_ATTRIBS);
337 ve = &vertex->element[i];
338 vb = &nv50->vtxbuf[b];
339
340 if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
341 PUSH_DATA(push, ve->state);
342 else
343 PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
344 }
345 for (; i < n; ++i)
346 PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
347
348 /* update per-instance enables */
349 mask = vertex->instance_elts ^ nv50->state.instance_elts;
350 while (mask) {
351 const int i = ffs(mask) - 1;
352 mask &= ~(1 << i);
353 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
354 PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
355 }
356 nv50->state.instance_elts = vertex->instance_elts;
357
358 if (nv50->vbo_user & ~nv50->vbo_constant)
359 nv50_upload_user_buffers(nv50, addrs, limits);
360
361 /* update buffers and set constant attributes */
362 for (i = 0; i < vertex->num_elements; ++i) {
363 uint64_t address, limit;
364 const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
365
366 assert(b < PIPE_MAX_ATTRIBS);
367 ve = &vertex->element[i];
368 vb = &nv50->vtxbuf[b];
369
370 if (unlikely(nv50->vbo_constant & (1 << b))) {
371 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
372 PUSH_DATA (push, 0);
373 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
374 continue;
375 } else
376 if (nv50->vbo_user & (1 << b)) {
377 address = addrs[b] + ve->pipe.src_offset;
378 limit = addrs[b] + limits[b];
379 } else
380 if (!vb->buffer.resource) {
381 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
382 PUSH_DATA (push, 0);
383 continue;
384 } else {
385 struct nv04_resource *buf = nv04_resource(vb->buffer.resource);
386 if (!(refd & (1 << b))) {
387 refd |= 1 << b;
388 BCTX_REFN(nv50->bufctx_3d, 3D_VERTEX, buf, RD);
389 }
390 address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
391 limit = buf->address + buf->base.width0 - 1;
392 }
393
394 if (unlikely(ve->pipe.instance_divisor)) {
395 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
396 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
397 PUSH_DATAh(push, address);
398 PUSH_DATA (push, address);
399 PUSH_DATA (push, ve->pipe.instance_divisor);
400 } else {
401 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
402 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
403 PUSH_DATAh(push, address);
404 PUSH_DATA (push, address);
405 }
406 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
407 PUSH_DATAh(push, limit);
408 PUSH_DATA (push, limit);
409 }
410 for (; i < nv50->state.num_vtxelts; ++i) {
411 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
412 PUSH_DATA (push, 0);
413 }
414 nv50->state.num_vtxelts = vertex->num_elements;
415 }
416
417 #define NV50_PRIM_GL_CASE(n) \
418 case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
419
420 static inline unsigned
nv50_prim_gl(unsigned prim)421 nv50_prim_gl(unsigned prim)
422 {
423 switch (prim) {
424 NV50_PRIM_GL_CASE(POINTS);
425 NV50_PRIM_GL_CASE(LINES);
426 NV50_PRIM_GL_CASE(LINE_LOOP);
427 NV50_PRIM_GL_CASE(LINE_STRIP);
428 NV50_PRIM_GL_CASE(TRIANGLES);
429 NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
430 NV50_PRIM_GL_CASE(TRIANGLE_FAN);
431 NV50_PRIM_GL_CASE(QUADS);
432 NV50_PRIM_GL_CASE(QUAD_STRIP);
433 NV50_PRIM_GL_CASE(POLYGON);
434 NV50_PRIM_GL_CASE(LINES_ADJACENCY);
435 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
436 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
437 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
438 default:
439 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
440 break;
441 }
442 }
443
444 /* For pre-nva0 transform feedback. */
445 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
446 {
447 [PIPE_PRIM_POINTS] = 1,
448 [PIPE_PRIM_LINES] = 2,
449 [PIPE_PRIM_LINE_LOOP] = 2,
450 [PIPE_PRIM_LINE_STRIP] = 2,
451 [PIPE_PRIM_TRIANGLES] = 3,
452 [PIPE_PRIM_TRIANGLE_STRIP] = 3,
453 [PIPE_PRIM_TRIANGLE_FAN] = 3,
454 [PIPE_PRIM_QUADS] = 3,
455 [PIPE_PRIM_QUAD_STRIP] = 3,
456 [PIPE_PRIM_POLYGON] = 3,
457 [PIPE_PRIM_LINES_ADJACENCY] = 2,
458 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
459 [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
460 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
461 };
462
463 static void
nv50_draw_arrays(struct nv50_context * nv50,unsigned mode,unsigned start,unsigned count,unsigned instance_count)464 nv50_draw_arrays(struct nv50_context *nv50,
465 unsigned mode, unsigned start, unsigned count,
466 unsigned instance_count)
467 {
468 struct nouveau_pushbuf *push = nv50->base.pushbuf;
469 unsigned prim;
470
471 if (nv50->state.index_bias) {
472 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
473 PUSH_DATA (push, 0);
474 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
475 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
476 PUSH_DATA (push, 0);
477 }
478 nv50->state.index_bias = 0;
479 }
480
481 prim = nv50_prim_gl(mode);
482
483 while (instance_count--) {
484 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
485 PUSH_DATA (push, prim);
486 BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
487 PUSH_DATA (push, start);
488 PUSH_DATA (push, count);
489 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
490 PUSH_DATA (push, 0);
491
492 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
493 }
494 }
495
496 static void
nv50_draw_elements_inline_u08(struct nouveau_pushbuf * push,const uint8_t * map,unsigned start,unsigned count)497 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
498 unsigned start, unsigned count)
499 {
500 map += start;
501
502 if (count & 3) {
503 unsigned i;
504 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
505 for (i = 0; i < (count & 3); ++i)
506 PUSH_DATA(push, *map++);
507 count &= ~3;
508 }
509 while (count) {
510 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
511
512 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
513 for (i = 0; i < nr; ++i) {
514 PUSH_DATA(push,
515 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
516 map += 4;
517 }
518 count -= nr * 4;
519 }
520 }
521
522 static void
nv50_draw_elements_inline_u16(struct nouveau_pushbuf * push,const uint16_t * map,unsigned start,unsigned count)523 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
524 unsigned start, unsigned count)
525 {
526 map += start;
527
528 if (count & 1) {
529 count &= ~1;
530 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
531 PUSH_DATA (push, *map++);
532 }
533 while (count) {
534 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
535
536 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
537 for (i = 0; i < nr; ++i) {
538 PUSH_DATA(push, (map[1] << 16) | map[0]);
539 map += 2;
540 }
541 count -= nr * 2;
542 }
543 }
544
545 static void
nv50_draw_elements_inline_u32(struct nouveau_pushbuf * push,const uint32_t * map,unsigned start,unsigned count)546 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
547 unsigned start, unsigned count)
548 {
549 map += start;
550
551 while (count) {
552 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
553
554 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
555 PUSH_DATAp(push, map, nr);
556
557 map += nr;
558 count -= nr;
559 }
560 }
561
562 static void
nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf * push,const uint32_t * map,unsigned start,unsigned count)563 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
564 const uint32_t *map,
565 unsigned start, unsigned count)
566 {
567 map += start;
568
569 if (count & 1) {
570 count--;
571 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
572 PUSH_DATA (push, *map++);
573 }
574 while (count) {
575 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
576
577 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
578 for (i = 0; i < nr; ++i) {
579 PUSH_DATA(push, (map[1] << 16) | map[0]);
580 map += 2;
581 }
582 count -= nr * 2;
583 }
584 }
585
586 static void
nv50_draw_elements(struct nv50_context * nv50,bool shorten,const struct pipe_draw_info * info,unsigned mode,unsigned start,unsigned count,unsigned instance_count,int32_t index_bias,unsigned index_size)587 nv50_draw_elements(struct nv50_context *nv50, bool shorten,
588 const struct pipe_draw_info *info,
589 unsigned mode, unsigned start, unsigned count,
590 unsigned instance_count, int32_t index_bias,
591 unsigned index_size)
592 {
593 struct nouveau_pushbuf *push = nv50->base.pushbuf;
594 unsigned prim;
595
596 prim = nv50_prim_gl(mode);
597
598 if (index_bias != nv50->state.index_bias) {
599 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
600 PUSH_DATA (push, index_bias);
601 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
602 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
603 PUSH_DATA (push, index_bias);
604 }
605 nv50->state.index_bias = index_bias;
606 }
607
608 if (!info->has_user_indices) {
609 struct nv04_resource *buf = nv04_resource(info->index.resource);
610 unsigned pb_start;
611 unsigned pb_bytes;
612 const unsigned base = buf->offset & ~3;
613
614 start += (buf->offset & 3) >> (index_size >> 1);
615
616 assert(nouveau_resource_mapped_by_gpu(info->index.resource));
617
618 /* This shouldn't have to be here. The going theory is that the buffer
619 * is being filled in by PGRAPH, and it's not done yet by the time it
620 * gets submitted to PFIFO, which in turn starts immediately prefetching
621 * the not-yet-written data. Ideally this wait would only happen on
622 * pushbuf submit, but it's probably not a big performance difference.
623 */
624 if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
625 nouveau_fence_wait(buf->fence_wr, &nv50->base.debug);
626
627 while (instance_count--) {
628 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
629 PUSH_DATA (push, prim);
630
631 nouveau_pushbuf_space(push, 16, 0, 1);
632 PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
633
634 switch (index_size) {
635 case 4:
636 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
637 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
638 break;
639 case 2:
640 pb_start = (start & ~1) * 2;
641 pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
642
643 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
644 PUSH_DATA (push, (start << 31) | count);
645 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
646 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
647 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
648 PUSH_DATA (push, 0);
649 break;
650 default:
651 assert(index_size == 1);
652 pb_start = start & ~3;
653 pb_bytes = ((start + count + 3) & ~3) - pb_start;
654
655 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
656 PUSH_DATA (push, (start << 30) | count);
657 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
658 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
659 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
660 PUSH_DATA (push, 0);
661 break;
662 }
663 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
664 PUSH_DATA (push, 0);
665
666 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
667 }
668 } else {
669 const void *data = info->index.user;
670
671 while (instance_count--) {
672 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
673 PUSH_DATA (push, prim);
674 switch (index_size) {
675 case 1:
676 nv50_draw_elements_inline_u08(push, data, start, count);
677 break;
678 case 2:
679 nv50_draw_elements_inline_u16(push, data, start, count);
680 break;
681 case 4:
682 if (shorten)
683 nv50_draw_elements_inline_u32_short(push, data, start, count);
684 else
685 nv50_draw_elements_inline_u32(push, data, start, count);
686 break;
687 default:
688 assert(0);
689 return;
690 }
691 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
692 PUSH_DATA (push, 0);
693
694 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
695 }
696 }
697 NOUVEAU_DRV_STAT(&nv50->screen->base, draw_calls_indexed, 1);
698 }
699
700 static void
nva0_draw_stream_output(struct nv50_context * nv50,const struct pipe_draw_info * info)701 nva0_draw_stream_output(struct nv50_context *nv50,
702 const struct pipe_draw_info *info)
703 {
704 struct nouveau_pushbuf *push = nv50->base.pushbuf;
705 struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
706 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
707 unsigned num_instances = info->instance_count;
708 unsigned mode = nv50_prim_gl(info->mode);
709
710 if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
711 /* A proper implementation without waiting doesn't seem possible,
712 * so don't bother.
713 */
714 NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
715 return;
716 }
717
718 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
719 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
720 PUSH_SPACE(push, 4);
721 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
722 PUSH_DATA (push, 0);
723 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
724 PUSH_DATA (push, 0);
725 }
726
727 assert(num_instances);
728 do {
729 PUSH_SPACE(push, 8);
730 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
731 PUSH_DATA (push, mode);
732 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
733 PUSH_DATA (push, 0);
734 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
735 PUSH_DATA (push, so->stride);
736 nv50_hw_query_pushbuf_submit(push, NVA0_3D_DRAW_TFB_BYTES,
737 nv50_query(so->pq), 0x4);
738 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
739 PUSH_DATA (push, 0);
740
741 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
742 } while (--num_instances);
743 }
744
745 static void
nv50_draw_vbo_kick_notify(struct nouveau_pushbuf * chan)746 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
747 {
748 struct nv50_screen *screen = chan->user_priv;
749
750 nouveau_fence_update(&screen->base, true);
751
752 nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true);
753 }
754
755 void
nv50_draw_vbo(struct pipe_context * pipe,const struct pipe_draw_info * info)756 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
757 {
758 struct nv50_context *nv50 = nv50_context(pipe);
759 struct nouveau_pushbuf *push = nv50->base.pushbuf;
760 bool tex_dirty = false;
761 int s;
762
763 if (info->index_size && !info->has_user_indices)
764 BCTX_REFN(nv50->bufctx_3d, 3D_INDEX, nv04_resource(info->index.resource), RD);
765
766 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
767 nv50->vb_elt_first = info->min_index + info->index_bias;
768 nv50->vb_elt_limit = info->max_index - info->min_index;
769 nv50->instance_off = info->start_instance;
770 nv50->instance_max = info->instance_count - 1;
771
772 /* For picking only a few vertices from a large user buffer, push is better,
773 * if index count is larger and we expect repeated vertices, suggest upload.
774 */
775 nv50->vbo_push_hint = /* the 64 is heuristic */
776 !(info->index_size && ((nv50->vb_elt_limit + 64) < info->count));
777
778 if (nv50->vbo_user && !(nv50->dirty_3d & (NV50_NEW_3D_ARRAYS | NV50_NEW_3D_VERTEX))) {
779 if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
780 nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
781 else
782 if (!nv50->vbo_fifo)
783 nv50_update_user_vbufs(nv50);
784 }
785
786 if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
787 nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
788
789 nv50_state_validate_3d(nv50, ~0);
790
791 push->kick_notify = nv50_draw_vbo_kick_notify;
792
793 for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
794 if (nv50->constbuf_coherent[s])
795 nv50->cb_dirty = true;
796 }
797
798 /* If there are any coherent constbufs, flush the cache */
799 if (nv50->cb_dirty) {
800 BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
801 PUSH_DATA (push, 0);
802 nv50->cb_dirty = false;
803 }
804
805 for (s = 0; s < 3 && !tex_dirty; ++s) {
806 if (nv50->textures_coherent[s])
807 tex_dirty = true;
808 }
809
810 if (tex_dirty) {
811 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
812 PUSH_DATA (push, 0x20);
813 }
814
815 if (nv50->screen->base.class_3d >= NVA0_3D_CLASS &&
816 nv50->seamless_cube_map != nv50->state.seamless_cube_map) {
817 nv50->state.seamless_cube_map = nv50->seamless_cube_map;
818 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
819 PUSH_DATA (push, nv50->seamless_cube_map ? NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
820 }
821
822 if (nv50->vertprog->mul_zero_wins != nv50->state.mul_zero_wins) {
823 nv50->state.mul_zero_wins = nv50->vertprog->mul_zero_wins;
824 BEGIN_NV04(push, NV50_3D(UNK1690), 1);
825 PUSH_DATA (push, 0x00010000 * !!nv50->state.mul_zero_wins);
826 }
827
828 if (nv50->vbo_fifo) {
829 nv50_push_vbo(nv50, info);
830 goto cleanup;
831 }
832
833 if (nv50->state.instance_base != info->start_instance) {
834 nv50->state.instance_base = info->start_instance;
835 /* NOTE: this does not affect the shader input, should it ? */
836 BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
837 PUSH_DATA (push, info->start_instance);
838 }
839
840 nv50->base.vbo_dirty |= !!nv50->vtxbufs_coherent;
841
842 if (nv50->base.vbo_dirty) {
843 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
844 PUSH_DATA (push, 0);
845 nv50->base.vbo_dirty = false;
846 }
847
848 if (info->index_size) {
849 bool shorten = info->max_index <= 65535;
850
851 if (info->primitive_restart != nv50->state.prim_restart) {
852 if (info->primitive_restart) {
853 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
854 PUSH_DATA (push, 1);
855 PUSH_DATA (push, info->restart_index);
856
857 if (info->restart_index > 65535)
858 shorten = false;
859 } else {
860 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
861 PUSH_DATA (push, 0);
862 }
863 nv50->state.prim_restart = info->primitive_restart;
864 } else
865 if (info->primitive_restart) {
866 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
867 PUSH_DATA (push, info->restart_index);
868
869 if (info->restart_index > 65535)
870 shorten = false;
871 }
872
873 nv50_draw_elements(nv50, shorten, info,
874 info->mode, info->start, info->count,
875 info->instance_count, info->index_bias, info->index_size);
876 } else
877 if (unlikely(info->count_from_stream_output)) {
878 nva0_draw_stream_output(nv50, info);
879 } else {
880 nv50_draw_arrays(nv50,
881 info->mode, info->start, info->count,
882 info->instance_count);
883 }
884
885 cleanup:
886 push->kick_notify = nv50_default_kick_notify;
887
888 nv50_release_user_vbufs(nv50);
889
890 nouveau_pushbuf_bufctx(push, NULL);
891
892 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_INDEX);
893 }
894