1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/format/u_format.h"
27 #include "util/format/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
30
31 #include "nouveau_vp3_video.h"
32
33 #include "codegen/nv50_ir_driver.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40 #include "nvc0/mme/comc597.mme.h"
41
42 #include "nv50/g80_texture.xml.h"
43
44 static bool
nvc0_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)45 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
46 enum pipe_format format,
47 enum pipe_texture_target target,
48 unsigned sample_count,
49 unsigned storage_sample_count,
50 unsigned bindings)
51 {
52 const struct util_format_description *desc = util_format_description(format);
53
54 if (sample_count > 8)
55 return false;
56 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
57 return false;
58
59 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
60 return false;
61
62 /* Short-circuit the rest of the logic -- this is used by the gallium frontend
63 * to determine valid MS levels in a no-attachments scenario.
64 */
65 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
66 return true;
67
68 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
69 if (util_format_get_blocksizebits(format) == 3 * 32)
70 return false;
71
72 if (bindings & PIPE_BIND_LINEAR)
73 if (util_format_is_depth_or_stencil(format) ||
74 (target != PIPE_TEXTURE_1D &&
75 target != PIPE_TEXTURE_2D &&
76 target != PIPE_TEXTURE_RECT) ||
77 sample_count > 1)
78 return false;
79
80 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A
81 * and GM20B.
82 */
83 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
84 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
85 nouveau_screen(pscreen)->device->chipset != 0x12b &&
86 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
87 return false;
88
89 /* shared is always supported */
90 bindings &= ~(PIPE_BIND_LINEAR |
91 PIPE_BIND_SHARED);
92
93 if (bindings & PIPE_BIND_SHADER_IMAGE) {
94 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
95 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
96 /* This should work on Fermi, but for currently unknown reasons it
97 * does not and results in breaking reads from pbos. */
98 return false;
99 }
100 }
101
102 return (( nvc0_format_table[format].usage |
103 nvc0_vertex_format[format].usage) & bindings) == bindings;
104 }
105
106 static int
nvc0_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)107 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
108 {
109 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
110 const struct nouveau_screen *screen = nouveau_screen(pscreen);
111 struct nouveau_device *dev = screen->device;
112
113 switch (param) {
114 /* non-boolean caps */
115 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
116 return 16384;
117 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
118 return 15;
119 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
120 return 12;
121 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
122 return 2048;
123 case PIPE_CAP_MIN_TEXEL_OFFSET:
124 return -8;
125 case PIPE_CAP_MAX_TEXEL_OFFSET:
126 return 7;
127 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
128 return -32;
129 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
130 return 31;
131 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
132 return 128 * 1024 * 1024;
133 case PIPE_CAP_GLSL_FEATURE_LEVEL:
134 return 430;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
136 return 430;
137 case PIPE_CAP_MAX_RENDER_TARGETS:
138 return 8;
139 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
140 return 1;
141 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
142 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
143 return 8;
144 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
145 return 4;
146 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
147 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
148 return 128;
149 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
150 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
151 return 1024;
152 case PIPE_CAP_MAX_VERTEX_STREAMS:
153 return 4;
154 case PIPE_CAP_MAX_GS_INVOCATIONS:
155 return 32;
156 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
157 return 1 << 27;
158 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
159 return 2048;
160 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
161 return 2047;
162 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
163 return 256;
164 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
165 if (class_3d < GM107_3D_CLASS)
166 return 256; /* IMAGE bindings require alignment to 256 */
167 return 16;
168 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
169 return 16;
170 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
171 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
172 case PIPE_CAP_MAX_VIEWPORTS:
173 return NVC0_MAX_VIEWPORTS;
174 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
175 return 4;
176 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
177 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
178 case PIPE_CAP_ENDIANNESS:
179 return PIPE_ENDIAN_LITTLE;
180 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
181 return 30;
182 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
183 return NVC0_MAX_WINDOW_RECTANGLES;
184 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
185 return class_3d >= GM200_3D_CLASS ? 8 : 0;
186 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
187 return 64 * 1024 * 1024;
188 case PIPE_CAP_MAX_VARYINGS:
189 /* NOTE: These only count our slots for GENERIC varyings.
190 * The address space may be larger, but the actual hard limit seems to be
191 * less than what the address space layout permits, so don't add TEXCOORD,
192 * COLOR, etc. here.
193 */
194 return 0x1f0 / 16;
195 case PIPE_CAP_MAX_VERTEX_BUFFERS:
196 return 16;
197 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
198 return 512 * 1024; /* TODO: Investigate tuning this */
199
200 /* supported caps */
201 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
202 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
203 case PIPE_CAP_TEXTURE_SWIZZLE:
204 case PIPE_CAP_TEXTURE_SHADOW_MAP:
205 case PIPE_CAP_NPOT_TEXTURES:
206 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
207 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
208 case PIPE_CAP_ANISOTROPIC_FILTER:
209 case PIPE_CAP_SEAMLESS_CUBE_MAP:
210 case PIPE_CAP_CUBE_MAP_ARRAY:
211 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
212 case PIPE_CAP_TEXTURE_MULTISAMPLE:
213 case PIPE_CAP_DEPTH_CLIP_DISABLE:
214 case PIPE_CAP_POINT_SPRITE:
215 case PIPE_CAP_TGSI_TEXCOORD:
216 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
217 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
218 case PIPE_CAP_VERTEX_SHADER_SATURATE:
219 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
220 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
221 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
222 case PIPE_CAP_QUERY_TIMESTAMP:
223 case PIPE_CAP_QUERY_TIME_ELAPSED:
224 case PIPE_CAP_OCCLUSION_QUERY:
225 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
226 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
227 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
228 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
229 case PIPE_CAP_INDEP_BLEND_ENABLE:
230 case PIPE_CAP_INDEP_BLEND_FUNC:
231 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
232 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
233 case PIPE_CAP_PRIMITIVE_RESTART:
234 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
235 case PIPE_CAP_TGSI_INSTANCEID:
236 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
237 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
238 case PIPE_CAP_CONDITIONAL_RENDER:
239 case PIPE_CAP_TEXTURE_BARRIER:
240 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
241 case PIPE_CAP_START_INSTANCE:
242 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
243 case PIPE_CAP_DRAW_INDIRECT:
244 case PIPE_CAP_USER_VERTEX_BUFFERS:
245 case PIPE_CAP_TEXTURE_QUERY_LOD:
246 case PIPE_CAP_SAMPLE_SHADING:
247 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
248 case PIPE_CAP_TEXTURE_GATHER_SM5:
249 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
250 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
251 case PIPE_CAP_SAMPLER_VIEW_TARGET:
252 case PIPE_CAP_CLIP_HALFZ:
253 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
254 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
255 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
256 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
257 case PIPE_CAP_DEPTH_BOUNDS_TEST:
258 case PIPE_CAP_TGSI_TXQS:
259 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
260 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
261 case PIPE_CAP_SHAREABLE_SHADERS:
262 case PIPE_CAP_CLEAR_TEXTURE:
263 case PIPE_CAP_DRAW_PARAMETERS:
264 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
265 case PIPE_CAP_MULTI_DRAW_INDIRECT:
266 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
267 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
268 case PIPE_CAP_QUERY_BUFFER_OBJECT:
269 case PIPE_CAP_INVALIDATE_BUFFER:
270 case PIPE_CAP_STRING_MARKER:
271 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
272 case PIPE_CAP_CULL_DISTANCE:
273 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
274 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
275 case PIPE_CAP_TGSI_VOTE:
276 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
277 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
278 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
279 case PIPE_CAP_DOUBLES:
280 case PIPE_CAP_INT64:
281 case PIPE_CAP_TGSI_TEX_TXF_LZ:
282 case PIPE_CAP_TGSI_CLOCK:
283 case PIPE_CAP_COMPUTE:
284 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
285 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
286 case PIPE_CAP_QUERY_SO_OVERFLOW:
287 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
288 case PIPE_CAP_TGSI_DIV:
289 case PIPE_CAP_TGSI_ATOMINC_WRAP:
290 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
291 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
292 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
293 case PIPE_CAP_FLATSHADE:
294 case PIPE_CAP_ALPHA_TEST:
295 case PIPE_CAP_POINT_SIZE_FIXED:
296 case PIPE_CAP_TWO_SIDED_COLOR:
297 case PIPE_CAP_CLIP_PLANES:
298 case PIPE_CAP_TEXTURE_SHADOW_LOD:
299 case PIPE_CAP_PACKED_STREAM_OUTPUT:
300 case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
301 return 1;
302 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
303 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
304 case PIPE_CAP_FBFETCH:
305 return class_3d >= NVE4_3D_CLASS ? 1 : 0; /* needs testing on fermi */
306 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
307 case PIPE_CAP_TGSI_BALLOT:
308 return class_3d >= NVE4_3D_CLASS;
309 case PIPE_CAP_BINDLESS_TEXTURE:
310 return class_3d >= NVE4_3D_CLASS;
311 case PIPE_CAP_TGSI_ATOMFADD:
312 return class_3d < GM107_3D_CLASS; /* needs additional lowering */
313 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
314 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
315 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
316 case PIPE_CAP_POST_DEPTH_COVERAGE:
317 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
318 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
319 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
320 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
321 case PIPE_CAP_VIEWPORT_SWIZZLE:
322 case PIPE_CAP_VIEWPORT_MASK:
323 return class_3d >= GM200_3D_CLASS;
324 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
325 return class_3d >= GP100_3D_CLASS;
326 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY_COMPUTE_ONLY:
327 case PIPE_CAP_SYSTEM_SVM:
328 return screen->has_svm ? 1 : 0;
329
330 /* caps has to be turned on with nir */
331 case PIPE_CAP_GL_SPIRV:
332 case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
333 case PIPE_CAP_INT64_DIVMOD:
334 return screen->prefer_nir ? 1 : 0;
335
336 /* nir related caps */
337 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
338 return 0;
339
340 /* unsupported caps */
341 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
342 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
343 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
344 case PIPE_CAP_SHADER_STENCIL_EXPORT:
345 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
346 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
347 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
348 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
349 case PIPE_CAP_FAKE_SW_MSAA:
350 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
351 case PIPE_CAP_VERTEXID_NOBASE:
352 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
353 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
354 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
355 case PIPE_CAP_GENERATE_MIPMAP:
356 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
357 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
358 case PIPE_CAP_QUERY_MEMORY_INFO:
359 case PIPE_CAP_PCI_GROUP:
360 case PIPE_CAP_PCI_BUS:
361 case PIPE_CAP_PCI_DEVICE:
362 case PIPE_CAP_PCI_FUNCTION:
363 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
364 case PIPE_CAP_NATIVE_FENCE_FD:
365 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
366 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
367 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
368 case PIPE_CAP_MEMOBJ:
369 case PIPE_CAP_LOAD_CONSTBUF:
370 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
371 case PIPE_CAP_TILE_RASTER_ORDER:
372 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
373 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
374 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
375 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
376 case PIPE_CAP_FENCE_SIGNAL:
377 case PIPE_CAP_CONSTBUF0_FLAGS:
378 case PIPE_CAP_PACKED_UNIFORMS:
379 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
380 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
381 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
382 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
383 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
384 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
385 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
386 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
387 case PIPE_CAP_NIR_COMPACT_ARRAYS:
388 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
389 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
390 case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
391 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
392 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
393 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
394 case PIPE_CAP_FBFETCH_COHERENT:
395 case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
396 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
397 case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: /* could be done */
398 case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
399 case PIPE_CAP_FRONTEND_NOOP:
400 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
401 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
402 case PIPE_CAP_PSIZ_CLAMPED:
403 return 0;
404
405 case PIPE_CAP_VENDOR_ID:
406 return 0x10de;
407 case PIPE_CAP_DEVICE_ID: {
408 uint64_t device_id;
409 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
410 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
411 return -1;
412 }
413 return device_id;
414 }
415 case PIPE_CAP_ACCELERATED:
416 return 1;
417 case PIPE_CAP_VIDEO_MEMORY:
418 return dev->vram_size >> 20;
419 case PIPE_CAP_UMA:
420 return 0;
421
422 default:
423 debug_printf("%s: unhandled cap %d\n", __func__, param);
424 /* fallthrough */
425 /* caps where we want the default value */
426 case PIPE_CAP_DMABUF:
427 case PIPE_CAP_ESSL_FEATURE_LEVEL:
428 case PIPE_CAP_THROTTLE:
429 return u_pipe_screen_get_param_defaults(pscreen, param);
430 }
431 }
432
433 static int
nvc0_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)434 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
435 enum pipe_shader_type shader,
436 enum pipe_shader_cap param)
437 {
438 const struct nouveau_screen *screen = nouveau_screen(pscreen);
439 const uint16_t class_3d = screen->class_3d;
440
441 switch (shader) {
442 case PIPE_SHADER_VERTEX:
443 case PIPE_SHADER_GEOMETRY:
444 case PIPE_SHADER_FRAGMENT:
445 case PIPE_SHADER_COMPUTE:
446 case PIPE_SHADER_TESS_CTRL:
447 case PIPE_SHADER_TESS_EVAL:
448 break;
449 default:
450 return 0;
451 }
452
453 switch (param) {
454 case PIPE_SHADER_CAP_PREFERRED_IR:
455 return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
456 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
457 uint32_t irs = 1 << PIPE_SHADER_IR_NIR |
458 ((class_3d >= GV100_3D_CLASS) ? 0 : 1 << PIPE_SHADER_IR_TGSI);
459 if (screen->force_enable_cl)
460 irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
461 return irs;
462 }
463 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
464 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
465 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
466 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
467 return 16384;
468 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
469 return 16;
470 case PIPE_SHADER_CAP_MAX_INPUTS:
471 return 0x200 / 16;
472 case PIPE_SHADER_CAP_MAX_OUTPUTS:
473 return 32;
474 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
475 return NVC0_MAX_CONSTBUF_SIZE;
476 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
477 return NVC0_MAX_PIPE_CONSTBUFS;
478 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
479 return shader != PIPE_SHADER_FRAGMENT;
480 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
481 /* HW doesn't support indirect addressing of fragment program inputs
482 * on Volta. The binary driver generates a function to handle every
483 * possible indirection, and indirectly calls the function to handle
484 * this instead.
485 */
486 if (class_3d >= GV100_3D_CLASS)
487 return shader != PIPE_SHADER_FRAGMENT;
488 return 1;
489 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
490 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
491 return 1;
492 case PIPE_SHADER_CAP_MAX_TEMPS:
493 return NVC0_CAP_MAX_PROGRAM_TEMPS;
494 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
495 return 1;
496 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
497 return 1;
498 case PIPE_SHADER_CAP_SUBROUTINES:
499 return 1;
500 case PIPE_SHADER_CAP_INTEGERS:
501 return 1;
502 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
503 return 1;
504 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
505 return 1;
506 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
507 return 1;
508 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
509 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
510 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
511 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
512 case PIPE_SHADER_CAP_INT64_ATOMICS:
513 case PIPE_SHADER_CAP_FP16:
514 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
515 case PIPE_SHADER_CAP_INT16:
516 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
517 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
518 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
519 return 0;
520 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
521 return NVC0_MAX_BUFFERS;
522 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
523 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
524 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
525 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
526 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
527 return 32;
528 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
529 if (class_3d >= NVE4_3D_CLASS)
530 return NVC0_MAX_IMAGES;
531 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
532 return NVC0_MAX_IMAGES;
533 return 0;
534 default:
535 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
536 return 0;
537 }
538 }
539
540 static float
nvc0_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)541 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
542 {
543 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
544
545 switch (param) {
546 case PIPE_CAPF_MAX_LINE_WIDTH:
547 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
548 return 10.0f;
549 case PIPE_CAPF_MAX_POINT_WIDTH:
550 return 63.0f;
551 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
552 return 63.375f;
553 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
554 return 16.0f;
555 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
556 return 15.0f;
557 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
558 return 0.0f;
559 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
560 return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
561 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
562 return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
563 }
564
565 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
566 return 0.0f;
567 }
568
569 static int
nvc0_screen_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * data)570 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
571 enum pipe_shader_ir ir_type,
572 enum pipe_compute_cap param, void *data)
573 {
574 struct nvc0_screen *screen = nvc0_screen(pscreen);
575 const uint16_t obj_class = screen->compute->oclass;
576
577 #define RET(x) do { \
578 if (data) \
579 memcpy(data, x, sizeof(x)); \
580 return sizeof(x); \
581 } while (0)
582
583 switch (param) {
584 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
585 RET((uint64_t []) { 3 });
586 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
587 if (obj_class >= NVE4_COMPUTE_CLASS) {
588 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
589 } else {
590 RET(((uint64_t []) { 65535, 65535, 65535 }));
591 }
592 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
593 RET(((uint64_t []) { 1024, 1024, 64 }));
594 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
595 RET((uint64_t []) { 1024 });
596 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
597 if (obj_class >= NVE4_COMPUTE_CLASS) {
598 RET((uint64_t []) { 1024 });
599 } else {
600 RET((uint64_t []) { 512 });
601 }
602 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
603 RET((uint64_t []) { 1ULL << 40 });
604 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
605 switch (obj_class) {
606 case GM200_COMPUTE_CLASS:
607 RET((uint64_t []) { 96 << 10 });
608 break;
609 case GM107_COMPUTE_CLASS:
610 RET((uint64_t []) { 64 << 10 });
611 break;
612 default:
613 RET((uint64_t []) { 48 << 10 });
614 break;
615 }
616 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
617 RET((uint64_t []) { 512 << 10 });
618 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
619 RET((uint64_t []) { 4096 });
620 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
621 RET((uint32_t []) { 32 });
622 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
623 RET((uint64_t []) { 1ULL << 40 });
624 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
625 RET((uint32_t []) { NVC0_MAX_IMAGES });
626 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
627 RET((uint32_t []) { screen->mp_count_compute });
628 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
629 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
630 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
631 RET((uint32_t []) { 64 });
632 default:
633 return 0;
634 }
635
636 #undef RET
637 }
638
639 static void
nvc0_screen_get_sample_pixel_grid(struct pipe_screen * pscreen,unsigned sample_count,unsigned * width,unsigned * height)640 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
641 unsigned sample_count,
642 unsigned *width, unsigned *height)
643 {
644 switch (sample_count) {
645 case 0:
646 case 1:
647 /* this could be 4x4, but the GL state tracker makes it difficult to
648 * create a 1x MSAA texture and smaller grids save CB space */
649 *width = 2;
650 *height = 4;
651 break;
652 case 2:
653 *width = 2;
654 *height = 4;
655 break;
656 case 4:
657 *width = 2;
658 *height = 2;
659 break;
660 case 8:
661 *width = 1;
662 *height = 2;
663 break;
664 default:
665 assert(0);
666 }
667 }
668
669 static void
nvc0_screen_destroy(struct pipe_screen * pscreen)670 nvc0_screen_destroy(struct pipe_screen *pscreen)
671 {
672 struct nvc0_screen *screen = nvc0_screen(pscreen);
673
674 if (!nouveau_drm_screen_unref(&screen->base))
675 return;
676
677 if (screen->base.fence.current) {
678 struct nouveau_fence *current = NULL;
679
680 /* nouveau_fence_wait will create a new current fence, so wait on the
681 * _current_ one, and remove both.
682 */
683 nouveau_fence_ref(screen->base.fence.current, ¤t);
684 nouveau_fence_wait(current, NULL);
685 nouveau_fence_ref(NULL, ¤t);
686 nouveau_fence_ref(NULL, &screen->base.fence.current);
687 }
688 if (screen->base.pushbuf)
689 screen->base.pushbuf->user_priv = NULL;
690
691 if (screen->blitter)
692 nvc0_blitter_destroy(screen);
693 if (screen->pm.prog) {
694 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
695 nvc0_program_destroy(NULL, screen->pm.prog);
696 FREE(screen->pm.prog);
697 }
698
699 nouveau_bo_ref(NULL, &screen->text);
700 nouveau_bo_ref(NULL, &screen->uniform_bo);
701 nouveau_bo_ref(NULL, &screen->tls);
702 nouveau_bo_ref(NULL, &screen->txc);
703 nouveau_bo_ref(NULL, &screen->fence.bo);
704 nouveau_bo_ref(NULL, &screen->poly_cache);
705
706 nouveau_heap_destroy(&screen->lib_code);
707 nouveau_heap_destroy(&screen->text_heap);
708
709 FREE(screen->tic.entries);
710
711 nouveau_object_del(&screen->eng3d);
712 nouveau_object_del(&screen->eng2d);
713 nouveau_object_del(&screen->m2mf);
714 nouveau_object_del(&screen->compute);
715 nouveau_object_del(&screen->nvsw);
716
717 nouveau_screen_fini(&screen->base);
718
719 FREE(screen);
720 }
721
722 static int
nvc0_graph_set_macro(struct nvc0_screen * screen,uint32_t m,unsigned pos,unsigned size,const uint32_t * data)723 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
724 unsigned size, const uint32_t *data)
725 {
726 struct nouveau_pushbuf *push = screen->base.pushbuf;
727
728 size /= 4;
729
730 assert((pos + size) <= 0x800);
731
732 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
733 PUSH_DATA (push, (m - 0x3800) / 8);
734 PUSH_DATA (push, pos);
735 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
736 PUSH_DATA (push, pos);
737 PUSH_DATAp(push, data, size);
738
739 return pos + size;
740 }
741
742 static int
tu102_graph_set_macro(struct nvc0_screen * screen,uint32_t m,unsigned pos,unsigned size,const uint32_t * data)743 tu102_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
744 unsigned size, const uint32_t *data)
745 {
746 struct nouveau_pushbuf *push = screen->base.pushbuf;
747
748 size /= 4;
749
750 assert((pos + size) <= 0x800);
751
752 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
753 PUSH_DATA (push, (m - 0x3800) / 8);
754 PUSH_DATA (push, pos);
755 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
756 PUSH_DATA (push, pos);
757 PUSH_DATAp(push, data, size);
758
759 return pos + (size / 3);
760 }
761
762 static void
nvc0_magic_3d_init(struct nouveau_pushbuf * push,uint16_t obj_class)763 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
764 {
765 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
766 PUSH_DATA (push, 0xff);
767 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
768 PUSH_DATA (push, 0xff);
769 PUSH_DATA (push, 0xff);
770 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
771 PUSH_DATA (push, 0xff);
772 PUSH_DATA (push, 0xff);
773 if (obj_class < GV100_3D_CLASS) {
774 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
775 PUSH_DATA (push, 0x3f);
776 }
777
778 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
779 PUSH_DATA (push, (3 << 16) | 3);
780 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
781 PUSH_DATA (push, (2 << 16) | 2);
782
783 if (obj_class < GM107_3D_CLASS) {
784 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
785 PUSH_DATA (push, 0);
786 }
787 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
788 PUSH_DATA (push, 0x10);
789 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
790 PUSH_DATA (push, 0x10);
791 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
792 PUSH_DATA (push, 0x10);
793 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
794 PUSH_DATA (push, 0x10);
795 PUSH_DATA (push, 0x10);
796 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
797 PUSH_DATA (push, 0x10);
798 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
799 PUSH_DATA (push, 0xe);
800
801 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
802 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
803 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
804 PUSH_DATA (push, 0);
805 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
806 PUSH_DATA (push, 3);
807
808 if (obj_class < GV100_3D_CLASS) {
809 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
810 PUSH_DATA (push, 0x3fffff);
811 }
812 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
813 PUSH_DATA (push, 1);
814 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
815 PUSH_DATA (push, 1);
816
817 if (obj_class < GM107_3D_CLASS) {
818 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
819 PUSH_DATA (push, 3);
820
821 if (obj_class >= NVE4_3D_CLASS) {
822 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
823 PUSH_DATA (push, 1);
824 }
825 }
826
827 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
828 * are supposed to do */
829 }
830
831 static void
nvc0_screen_fence_emit(struct pipe_screen * pscreen,u32 * sequence)832 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
833 {
834 struct nvc0_screen *screen = nvc0_screen(pscreen);
835 struct nouveau_pushbuf *push = screen->base.pushbuf;
836
837 /* we need to do it after possible flush in MARK_RING */
838 *sequence = ++screen->base.fence.sequence;
839
840 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
841 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
842 PUSH_DATAh(push, screen->fence.bo->offset);
843 PUSH_DATA (push, screen->fence.bo->offset);
844 PUSH_DATA (push, *sequence);
845 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
846 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
847 }
848
849 static u32
nvc0_screen_fence_update(struct pipe_screen * pscreen)850 nvc0_screen_fence_update(struct pipe_screen *pscreen)
851 {
852 struct nvc0_screen *screen = nvc0_screen(pscreen);
853 return screen->fence.map[0];
854 }
855
856 static int
nvc0_screen_init_compute(struct nvc0_screen * screen)857 nvc0_screen_init_compute(struct nvc0_screen *screen)
858 {
859 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
860
861 switch (screen->base.device->chipset & ~0xf) {
862 case 0xc0:
863 case 0xd0:
864 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
865 case 0xe0:
866 case 0xf0:
867 case 0x100:
868 case 0x110:
869 case 0x120:
870 case 0x130:
871 case 0x140:
872 case 0x160:
873 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
874 default:
875 return -1;
876 }
877 }
878
879 static int
nvc0_screen_resize_tls_area(struct nvc0_screen * screen,uint32_t lpos,uint32_t lneg,uint32_t cstack)880 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
881 uint32_t lpos, uint32_t lneg, uint32_t cstack)
882 {
883 struct nouveau_bo *bo = NULL;
884 int ret;
885 uint64_t size = (lpos + lneg) * 32 + cstack;
886
887 if (size >= (1 << 20)) {
888 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
889 return -1;
890 }
891
892 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
893 size = align(size, 0x8000);
894 size *= screen->mp_count;
895
896 size = align(size, 1 << 17);
897
898 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
899 NULL, &bo);
900 if (ret)
901 return ret;
902
903 /* Make sure that the pushbuf has acquired a reference to the old tls
904 * segment, as it may have commands that will reference it.
905 */
906 if (screen->tls)
907 PUSH_REFN(screen->base.pushbuf, screen->tls,
908 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
909 nouveau_bo_ref(NULL, &screen->tls);
910 screen->tls = bo;
911 return 0;
912 }
913
914 int
nvc0_screen_resize_text_area(struct nvc0_screen * screen,uint64_t size)915 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
916 {
917 struct nouveau_pushbuf *push = screen->base.pushbuf;
918 struct nouveau_bo *bo;
919 int ret;
920
921 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
922 1 << 17, size, NULL, &bo);
923 if (ret)
924 return ret;
925
926 /* Make sure that the pushbuf has acquired a reference to the old text
927 * segment, as it may have commands that will reference it.
928 */
929 if (screen->text)
930 PUSH_REFN(push, screen->text,
931 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
932 nouveau_bo_ref(NULL, &screen->text);
933 screen->text = bo;
934
935 nouveau_heap_destroy(&screen->lib_code);
936 nouveau_heap_destroy(&screen->text_heap);
937
938 /* XXX: getting a page fault at the end of the code buffer every few
939 * launches, don't use the last 256 bytes to work around them - prefetch ?
940 */
941 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
942
943 /* update the code segment setup */
944 if (screen->eng3d->oclass < GV100_3D_CLASS) {
945 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
946 PUSH_DATAh(push, screen->text->offset);
947 PUSH_DATA (push, screen->text->offset);
948 if (screen->compute) {
949 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
950 PUSH_DATAh(push, screen->text->offset);
951 PUSH_DATA (push, screen->text->offset);
952 }
953 }
954
955 return 0;
956 }
957
958 void
nvc0_screen_bind_cb_3d(struct nvc0_screen * screen,bool * can_serialize,int stage,int index,int size,uint64_t addr)959 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
960 int stage, int index, int size, uint64_t addr)
961 {
962 assert(stage != 5);
963
964 struct nouveau_pushbuf *push = screen->base.pushbuf;
965
966 if (screen->base.class_3d >= GM107_3D_CLASS) {
967 struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
968
969 // TODO: Better figure out the conditions in which this is needed
970 bool serialize = binding->addr == addr && binding->size != size;
971 if (can_serialize)
972 serialize = serialize && *can_serialize;
973 if (serialize) {
974 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
975 if (can_serialize)
976 *can_serialize = false;
977 }
978
979 binding->addr = addr;
980 binding->size = size;
981 }
982
983 if (size >= 0) {
984 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
985 PUSH_DATA (push, size);
986 PUSH_DATAh(push, addr);
987 PUSH_DATA (push, addr);
988 }
989 IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
990 }
991
992 static const void *
nvc0_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)993 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
994 enum pipe_shader_ir ir,
995 enum pipe_shader_type shader)
996 {
997 struct nvc0_screen *screen = nvc0_screen(pscreen);
998 if (ir == PIPE_SHADER_IR_NIR)
999 return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset);
1000 return NULL;
1001 }
1002
1003 #define FAIL_SCREEN_INIT(str, err) \
1004 do { \
1005 NOUVEAU_ERR(str, err); \
1006 goto fail; \
1007 } while(0)
1008
1009 struct nouveau_screen *
nvc0_screen_create(struct nouveau_device * dev)1010 nvc0_screen_create(struct nouveau_device *dev)
1011 {
1012 struct nvc0_screen *screen;
1013 struct pipe_screen *pscreen;
1014 struct nouveau_object *chan;
1015 struct nouveau_pushbuf *push;
1016 uint64_t value;
1017 uint32_t obj_class;
1018 uint32_t flags;
1019 int ret;
1020 unsigned i;
1021
1022 switch (dev->chipset & ~0xf) {
1023 case 0xc0:
1024 case 0xd0:
1025 case 0xe0:
1026 case 0xf0:
1027 case 0x100:
1028 case 0x110:
1029 case 0x120:
1030 case 0x130:
1031 case 0x140:
1032 case 0x160:
1033 break;
1034 default:
1035 return NULL;
1036 }
1037
1038 screen = CALLOC_STRUCT(nvc0_screen);
1039 if (!screen)
1040 return NULL;
1041 pscreen = &screen->base.base;
1042 pscreen->destroy = nvc0_screen_destroy;
1043
1044 ret = nouveau_screen_init(&screen->base, dev);
1045 if (ret)
1046 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1047 chan = screen->base.channel;
1048 push = screen->base.pushbuf;
1049 push->user_priv = screen;
1050 push->rsvd_kick = 5;
1051
1052 /* TODO: could this be higher on Kepler+? how does reclocking vs no
1053 * reclocking affect performance?
1054 * TODO: could this be higher on Fermi?
1055 */
1056 if (dev->chipset >= 0xe0)
1057 screen->base.transfer_pushbuf_threshold = 1024;
1058
1059 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1060 PIPE_BIND_SHADER_BUFFER |
1061 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1062 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1063 screen->base.sysmem_bindings |=
1064 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1065
1066 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1067 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1068 screen->base.vidmem_bindings = 0;
1069 }
1070
1071 pscreen->context_create = nvc0_create;
1072 pscreen->is_format_supported = nvc0_screen_is_format_supported;
1073 pscreen->get_param = nvc0_screen_get_param;
1074 pscreen->get_shader_param = nvc0_screen_get_shader_param;
1075 pscreen->get_paramf = nvc0_screen_get_paramf;
1076 pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1077 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1078 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1079 /* nir stuff */
1080 pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1081
1082 nvc0_screen_init_resource_functions(pscreen);
1083
1084 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1085 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1086
1087 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1088 if (screen->base.drm->version >= 0x01000202)
1089 flags |= NOUVEAU_BO_COHERENT;
1090
1091 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1092 if (ret)
1093 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1094 nouveau_bo_map(screen->fence.bo, 0, NULL);
1095 screen->fence.map = screen->fence.bo->map;
1096 screen->base.fence.emit = nvc0_screen_fence_emit;
1097 screen->base.fence.update = nvc0_screen_fence_update;
1098
1099 if (dev->chipset < 0x140) {
1100 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1101 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1102 if (ret)
1103 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1104
1105 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1106 PUSH_DATA (push, screen->nvsw->handle);
1107 }
1108
1109 switch (dev->chipset & ~0xf) {
1110 case 0x160:
1111 case 0x140:
1112 case 0x130:
1113 case 0x120:
1114 case 0x110:
1115 case 0x100:
1116 case 0xf0:
1117 obj_class = NVF0_P2MF_CLASS;
1118 break;
1119 case 0xe0:
1120 obj_class = NVE4_P2MF_CLASS;
1121 break;
1122 default:
1123 obj_class = NVC0_M2MF_CLASS;
1124 break;
1125 }
1126 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1127 &screen->m2mf);
1128 if (ret)
1129 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1130
1131 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1132 PUSH_DATA (push, screen->m2mf->oclass);
1133 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1134 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1135 PUSH_DATA (push, NVE4_COPY_CLASS);
1136 }
1137
1138 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1139 &screen->eng2d);
1140 if (ret)
1141 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1142
1143 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1144 PUSH_DATA (push, screen->eng2d->oclass);
1145 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1146 PUSH_DATA (push, 0);
1147 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1148 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1149 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1150 PUSH_DATA (push, 0);
1151 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1152 PUSH_DATA (push, 0);
1153 BEGIN_NVC0(push, NVC0_2D(SET_PIXELS_FROM_MEMORY_CORRAL_SIZE), 1);
1154 PUSH_DATA (push, 0x3f);
1155 BEGIN_NVC0(push, NVC0_2D(SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP), 1);
1156 PUSH_DATA (push, 1);
1157 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1158 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1159
1160 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1161 PUSH_DATAh(push, screen->fence.bo->offset + 16);
1162 PUSH_DATA (push, screen->fence.bo->offset + 16);
1163
1164 switch (dev->chipset & ~0xf) {
1165 case 0x160:
1166 obj_class = TU102_3D_CLASS;
1167 break;
1168 case 0x140:
1169 obj_class = GV100_3D_CLASS;
1170 break;
1171 case 0x130:
1172 switch (dev->chipset) {
1173 case 0x130:
1174 case 0x13b:
1175 obj_class = GP100_3D_CLASS;
1176 break;
1177 default:
1178 obj_class = GP102_3D_CLASS;
1179 break;
1180 }
1181 break;
1182 case 0x120:
1183 obj_class = GM200_3D_CLASS;
1184 break;
1185 case 0x110:
1186 obj_class = GM107_3D_CLASS;
1187 break;
1188 case 0x100:
1189 case 0xf0:
1190 obj_class = NVF0_3D_CLASS;
1191 break;
1192 case 0xe0:
1193 switch (dev->chipset) {
1194 case 0xea:
1195 obj_class = NVEA_3D_CLASS;
1196 break;
1197 default:
1198 obj_class = NVE4_3D_CLASS;
1199 break;
1200 }
1201 break;
1202 case 0xd0:
1203 obj_class = NVC8_3D_CLASS;
1204 break;
1205 case 0xc0:
1206 default:
1207 switch (dev->chipset) {
1208 case 0xc8:
1209 obj_class = NVC8_3D_CLASS;
1210 break;
1211 case 0xc1:
1212 obj_class = NVC1_3D_CLASS;
1213 break;
1214 default:
1215 obj_class = NVC0_3D_CLASS;
1216 break;
1217 }
1218 break;
1219 }
1220 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1221 &screen->eng3d);
1222 if (ret)
1223 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1224 screen->base.class_3d = obj_class;
1225
1226 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1227 PUSH_DATA (push, screen->eng3d->oclass);
1228
1229 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1230 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1231
1232 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1233 /* kill shaders after about 1 second (at 100 MHz) */
1234 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1235 PUSH_DATA (push, 0x17);
1236 }
1237
1238 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1239 screen->base.drm->version >= 0x01000101);
1240 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1241 for (i = 0; i < 8; ++i)
1242 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1243
1244 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1245 PUSH_DATA (push, 1);
1246
1247 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1248 PUSH_DATA (push, 0);
1249 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1250 PUSH_DATA (push, 0);
1251 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1252 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1253 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1254 PUSH_DATA (push, 0);
1255 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1256 PUSH_DATA (push, 1);
1257 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1258 PUSH_DATA (push, 1);
1259 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1260 PUSH_DATA (push, 1);
1261 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1262 PUSH_DATA (push, 0);
1263 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1264 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1265 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1266 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1267 } else {
1268 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1269 PUSH_DATA (push, 15);
1270 }
1271 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1272 PUSH_DATA (push, 8); /* 128 */
1273 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1274 PUSH_DATA (push, 1);
1275 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1276 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1277 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1278 }
1279
1280 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1281
1282 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1283 if (ret)
1284 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1285
1286 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1287 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1288 &screen->uniform_bo);
1289 if (ret)
1290 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1291
1292 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1293
1294 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1295 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1296 PUSH_DATA (push, 256);
1297 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1298 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1299 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1300 PUSH_DATA (push, 0);
1301 PUSH_DATAf(push, 0.0f);
1302 PUSH_DATAf(push, 0.0f);
1303 PUSH_DATAf(push, 0.0f);
1304 PUSH_DATAf(push, 0.0f);
1305 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1306 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1307 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1308
1309 if (screen->base.drm->version >= 0x01000101) {
1310 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1311 if (ret)
1312 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1313 } else {
1314 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1315 value = (8 << 8) | 4;
1316 else
1317 value = (16 << 8) | 4;
1318 }
1319 screen->gpc_count = value & 0x000000ff;
1320 screen->mp_count = value >> 8;
1321 screen->mp_count_compute = screen->mp_count;
1322
1323 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1324 if (ret)
1325 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1326
1327 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1328 PUSH_DATAh(push, screen->tls->offset);
1329 PUSH_DATA (push, screen->tls->offset);
1330 PUSH_DATA (push, screen->tls->size >> 32);
1331 PUSH_DATA (push, screen->tls->size);
1332 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1333 PUSH_DATA (push, 0);
1334 /* Reduce likelihood of collision with real buffers by placing the hole at
1335 * the top of the 4G area. This will have to be dealt with for real
1336 * eventually by blocking off that area from the VM.
1337 */
1338 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1339 PUSH_DATA (push, 0xff << 24);
1340
1341 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1342 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1343 &screen->poly_cache);
1344 if (ret)
1345 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1346
1347 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1348 PUSH_DATAh(push, screen->poly_cache->offset);
1349 PUSH_DATA (push, screen->poly_cache->offset);
1350 PUSH_DATA (push, 3);
1351 }
1352
1353 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1354 &screen->txc);
1355 if (ret)
1356 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1357
1358 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1359 PUSH_DATAh(push, screen->txc->offset);
1360 PUSH_DATA (push, screen->txc->offset);
1361 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1362 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1363 screen->tic.maxwell = true;
1364 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1365 screen->tic.maxwell =
1366 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1367 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1368 }
1369 }
1370
1371 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1372 PUSH_DATAh(push, screen->txc->offset + 65536);
1373 PUSH_DATA (push, screen->txc->offset + 65536);
1374 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1375
1376 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1377 PUSH_DATA (push, 0);
1378 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1379 PUSH_DATA (push, 0);
1380 PUSH_DATA (push, 0);
1381 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1382 PUSH_DATA (push, 0x3f);
1383
1384 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1385 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1386 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1387 for (i = 0; i < 8 * 2; ++i)
1388 PUSH_DATA(push, 0);
1389 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1390 PUSH_DATA (push, 0);
1391 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1392 PUSH_DATA (push, 0);
1393
1394 /* neither scissors, viewport nor stencil mask should affect clears */
1395 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1396 PUSH_DATA (push, 0);
1397
1398 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1399 PUSH_DATA (push, 1);
1400 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1401 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1402 PUSH_DATAf(push, 0.0f);
1403 PUSH_DATAf(push, 1.0f);
1404 }
1405 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1406 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1407
1408 /* We use scissors instead of exact view volume clipping,
1409 * so they're always enabled.
1410 */
1411 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1412 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1413 PUSH_DATA (push, 1);
1414 PUSH_DATA (push, 16384 << 16);
1415 PUSH_DATA (push, 16384 << 16);
1416 }
1417
1418 if (screen->eng3d->oclass < TU102_3D_CLASS) {
1419 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1420
1421 i = 0;
1422 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1423 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1424 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1425 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1426 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1427 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1428 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1429 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1430 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1431 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1432 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1433 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1434 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1435 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1436 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1437 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1438 } else {
1439 #undef MK_MACRO
1440 #define MK_MACRO(m, n) i = tu102_graph_set_macro(screen, m, i, sizeof(n), n);
1441
1442 i = 0;
1443 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mmec597_per_instance_bf);
1444 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mmec597_blend_enables);
1445 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mmec597_vertex_array_select);
1446 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mmec597_tep_select);
1447 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mmec597_gp_select);
1448 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mmec597_poly_mode_front);
1449 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mmec597_poly_mode_back);
1450 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mmec597_draw_arrays_indirect);
1451 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mmec597_draw_elts_indirect);
1452 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mmec597_draw_arrays_indirect_count);
1453 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mmec597_draw_elts_indirect_count);
1454 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mmec597_query_buffer_write);
1455 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mmec597_conservative_raster_state);
1456 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mmec597_compute_counter);
1457 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mmec597_compute_counter_to_query);
1458 }
1459
1460 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1461 PUSH_DATA (push, 1);
1462 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1463 PUSH_DATA (push, 1);
1464 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1465 PUSH_DATA (push, 0x40);
1466 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1467 PUSH_DATA (push, 0);
1468 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1469 PUSH_DATA (push, 0x30);
1470 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1471 PUSH_DATA (push, 3);
1472 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1473 PUSH_DATA (push, 0x20);
1474 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1475 PUSH_DATA (push, 0x00);
1476 screen->save_state.patch_vertices = 3;
1477
1478 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1479 PUSH_DATA (push, 0);
1480 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1481 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1482
1483 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1484
1485 if (nvc0_screen_init_compute(screen))
1486 goto fail;
1487
1488 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1489 for (i = 0; i < 5; ++i) {
1490 unsigned j = 0;
1491 for (j = 0; j < 16; j++)
1492 screen->cb_bindings[i][j].size = -1;
1493
1494 /* TIC and TSC entries for each unit (nve4+ only) */
1495 /* auxiliary constants (6 user clip planes, base instance id) */
1496 nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1497 screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1498 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1499 unsigned j;
1500 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1501 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1502 for (j = 0; j < 8; ++j)
1503 PUSH_DATA(push, j);
1504 } else {
1505 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1506 PUSH_DATA (push, 0x54);
1507 }
1508
1509 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1510 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1511 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1512 PUSH_DATA (push, 0); /* 0 */
1513 PUSH_DATA (push, 0);
1514 PUSH_DATA (push, 1); /* 1 */
1515 PUSH_DATA (push, 0);
1516 PUSH_DATA (push, 0); /* 2 */
1517 PUSH_DATA (push, 1);
1518 PUSH_DATA (push, 1); /* 3 */
1519 PUSH_DATA (push, 1);
1520 PUSH_DATA (push, 2); /* 4 */
1521 PUSH_DATA (push, 0);
1522 PUSH_DATA (push, 3); /* 5 */
1523 PUSH_DATA (push, 0);
1524 PUSH_DATA (push, 2); /* 6 */
1525 PUSH_DATA (push, 1);
1526 PUSH_DATA (push, 3); /* 7 */
1527 PUSH_DATA (push, 1);
1528 }
1529 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1530 PUSH_DATA (push, 0);
1531
1532 PUSH_KICK (push);
1533
1534 screen->tic.entries = CALLOC(
1535 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1536 sizeof(void *));
1537 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1538 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1539
1540 if (!nvc0_blitter_create(screen))
1541 goto fail;
1542
1543 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1544
1545 return &screen->base;
1546
1547 fail:
1548 screen->base.base.context_create = NULL;
1549 return &screen->base;
1550 }
1551
1552 int
nvc0_screen_tic_alloc(struct nvc0_screen * screen,void * entry)1553 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1554 {
1555 int i = screen->tic.next;
1556
1557 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1558 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1559
1560 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1561
1562 if (screen->tic.entries[i])
1563 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1564
1565 screen->tic.entries[i] = entry;
1566 return i;
1567 }
1568
1569 int
nvc0_screen_tsc_alloc(struct nvc0_screen * screen,void * entry)1570 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1571 {
1572 int i = screen->tsc.next;
1573
1574 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1575 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1576
1577 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1578
1579 if (screen->tsc.entries[i])
1580 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1581
1582 screen->tsc.entries[i] = entry;
1583 return i;
1584 }
1585