| /external/wpa_supplicant_8/src/crypto/ |
| D | milenage.c | 36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1()
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345()
173 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k, in milenage_generate()
208 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts, in milenage_auts()
235 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres, u8 *kc) in gsm_milenage()
270 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand, in milenage_check()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_isa.c | 561 int opc; in r600_isa_init() local
574 int opc = op->opcode[isa->hw_class]; in r600_isa_init() local
582 int opc = op->opcode[isa->hw_class]; in r600_isa_init() local
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| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_disasm.c | 41 uint32_t opc : 6; member
458 #define OPC(opc) [INST_OPCODE_##opc] = {#opc, print_opc_default} argument
459 #define OPC_MOV(opc) [INST_OPCODE_##opc] = {#opc, print_opc_mov} argument
460 #define OPC_TEX(opc) [INST_OPCODE_##opc] = {#opc, print_opc_tex} argument
461 #define OPC_IMM(opc) [INST_OPCODE_##opc] = {#opc, print_opc_imm} argument
530 const unsigned opc = instr->opc | (instr->opcode_bit6 << 6); in print_instr() local
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 43 #define OPCODE_GAP(opc) { .opcode = opc }, argument
77 #define OPCODE_GAP(opc) "UNK" #opc, argument
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| /external/mesa3d/src/freedreno/afuc/ |
| D | disasm.c | 119 static void print_alu_name(afuc_opc opc, uint32_t instr) in print_alu_name()
307 afuc_opc opc; in disasm() local
355 afuc_opc opc; in disasm() local
472 unsigned opc, p; in disasm() local
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| D | afuc.h | 173 afuc_get_opc(afuc_instr *ai, afuc_opc *opc, bool *rep) in afuc_get_opc()
185 afuc_set_opc(afuc_instr *ai, afuc_opc opc, bool rep) in afuc_set_opc()
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| D | asm.c | 131 afuc_opc opc; in emit_instructions() local
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| /external/mesa3d/src/freedreno/ir3/ |
| D | disasm-a3xx.c | 508 int opc = _OPC(2, cat2->opc); in print_instr_cat2() local
1187 uint32_t opc = _OPC(6, cat6->opc); in print_instr_cat6_a6xx() local
1302 uint16_t opc; member
1306 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat } argument
1488 const char *disasm_a3xx_instr_name(opc_t opc) in disasm_a3xx_instr_name()
1497 uint32_t opc = instr_opc(instr, ctx->gpu_id); in print_single_instr() local
1521 opc_t opc = _OPC(instr->opc_cat, instr_opc(instr, ctx->gpu_id)); in print_instr() local
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| D | ir3.h | 173 opc_t opc; member
849 cat3_half_opc(opc_t opc) in cat3_half_opc()
862 cat3_full_opc(opc_t opc) in cat3_full_opc()
875 cat4_half_opc(opc_t opc) in cat4_half_opc()
886 cat4_full_opc(opc_t opc) in cat4_full_opc()
1010 static inline bool ir3_cat2_int(opc_t opc) in ir3_cat2_int()
1051 static inline unsigned ir3_cat2_absneg(opc_t opc) in ir3_cat2_absneg()
1111 static inline unsigned ir3_cat3_absneg(opc_t opc) in ir3_cat3_absneg()
1476 #define __INSTR0(flag, name, opc) \ argument
1488 #define __INSTR1(flag, name, opc) \ argument
[all …]
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| D | instr-a3xx.h | 53 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc) argument
265 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS)) argument
266 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1))) argument
399 uint32_t opc : 4; member
506 uint32_t opc : 6; member
567 uint32_t opc : 4; member
625 uint32_t opc : 6; member
727 uint32_t opc : 5; member
855 uint32_t opc : 5; member
920 uint32_t opc : 5; member
[all …]
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| D | ir3_parser.y | 79 static struct ir3_instruction * new_instr(opc_t opc) in new_instr()
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| D | ir3.c | 1059 opc_t opc, int nreg) in ir3_instr_create2()
1068 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc) in ir3_instr_create()
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| /external/mesa3d/src/freedreno/ir2/ |
| D | disasm-a2xx.c | 129 #define INSTR(opc, num_srcs) [opc] = { num_srcs, #opc } argument
442 #define INSTR(opc, name, fxn) [opc] = { name, fxn } argument
558 #define INSTR(opc, fxn) [opc] = { #opc, fxn } argument
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| D | instr-a2xx.h | 224 instr_cf_opc_t opc : 4; member
233 instr_cf_opc_t opc : 4; member
246 instr_cf_opc_t opc : 4; member
255 instr_cf_opc_t opc : 4; member
265 instr_cf_opc_t opc : 4; member
324 instr_fetch_opc_t opc : 5; member
358 instr_fetch_opc_t opc : 5; member
391 instr_fetch_opc_t opc : 5; member
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_emit_nvc0.cpp | 396 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc) in emitForm_A()
441 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc) in emitForm_B()
470 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred) in emitForm_S()
1867 uint32_t opc; in emitSTORE() local
1914 uint32_t opc; in emitLOAD() local
2050 uint64_t opc; in emitMOV() local
2258 uint64_t opc; in emitSUCalc() local
2513 uint64_t opc = 0x4; in emitVSHL() local
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| /external/autotest/client/cros/cellular/ |
| D | prologix_scpi_driver_test_noautorun.py | 184 def _get_idns_and_verify(self, instruments, opc=False): argument
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| /external/vixl/src/aarch64/ |
| D | instructions-aarch64.cc | 253 unsigned opc = ExtractBits(23, 22); in CanTakeSVEMovprfx() local
394 unsigned opc = ExtractBits(23, 22); in CanTakeSVEMovprfx() local
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| /external/f2fs-tools/tools/sg_write_buffer/include/ |
| D | freebsd_nvme_ioctl.h | 39 uint16_t opc : 8; /* opcode */ member
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | ConstantsContext.h | 271 CompareConstantExpr(Type *ty, Instruction::OtherOps opc, in CompareConstantExpr()
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| /external/llvm/lib/IR/ |
| D | ConstantsContext.h | 265 CompareConstantExpr(Type *ty, Instruction::OtherOps opc, in CompareConstantExpr()
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| /external/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| D | EmulateInstructionARM64.cpp | 704 uint32_t opc = Bits32(opcode, 31, 30); in EmulateLDPSTP() local
928 uint32_t opc = Bits32(opcode, 23, 22); in EmulateLDRSTRImm() local
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackend.cpp | 431 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 in adjustFixupValue() local
446 unsigned opc = 0; in adjustFixupValue() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackend.cpp | 506 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 in adjustFixupValue() local
521 unsigned opc = 0; in adjustFixupValue() local
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| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackend.cpp | 513 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 in adjustFixupValue() local
528 unsigned opc = 0; in adjustFixupValue() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonNewValueJump.cpp | 637 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, in runOnMachineFunction() local
|