1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_fs.h"
29 #include "brw_fs_live_variables.h"
30 #include "brw_vec4.h"
31 #include "brw_cfg.h"
32 #include "brw_shader.h"
33
34 using namespace brw;
35
36 /** @file brw_fs_schedule_instructions.cpp
37 *
38 * List scheduling of FS instructions.
39 *
40 * The basic model of the list scheduler is to take a basic block,
41 * compute a DAG of the dependencies (RAW ordering with latency, WAW
42 * ordering with latency, WAR ordering), and make a list of the DAG heads.
43 * Heuristically pick a DAG head, then put all the children that are
44 * now DAG heads into the list of things to schedule.
45 *
46 * The heuristic is the important part. We're trying to be cheap,
47 * since actually computing the optimal scheduling is NP complete.
48 * What we do is track a "current clock". When we schedule a node, we
49 * update the earliest-unblocked clock time of its children, and
50 * increment the clock. Then, when trying to schedule, we just pick
51 * the earliest-unblocked instruction to schedule.
52 *
53 * Note that often there will be many things which could execute
54 * immediately, and there are a range of heuristic options to choose
55 * from in picking among those.
56 */
57
58 static bool debug = false;
59
60 class instruction_scheduler;
61
62 class schedule_node : public exec_node
63 {
64 public:
65 schedule_node(backend_instruction *inst, instruction_scheduler *sched);
66 void set_latency_gen4();
67 void set_latency_gen7(bool is_haswell);
68
69 backend_instruction *inst;
70 schedule_node **children;
71 int *child_latency;
72 int child_count;
73 int parent_count;
74 int child_array_size;
75 int unblocked_time;
76 int latency;
77
78 /**
79 * Which iteration of pushing groups of children onto the candidates list
80 * this node was a part of.
81 */
82 unsigned cand_generation;
83
84 /**
85 * This is the sum of the instruction's latency plus the maximum delay of
86 * its children, or just the issue_time if it's a leaf node.
87 */
88 int delay;
89
90 /**
91 * Preferred exit node among the (direct or indirect) successors of this
92 * node. Among the scheduler nodes blocked by this node, this will be the
93 * one that may cause earliest program termination, or NULL if none of the
94 * successors is an exit node.
95 */
96 schedule_node *exit;
97 };
98
99 /**
100 * Lower bound of the scheduling time after which one of the instructions
101 * blocked by this node may lead to program termination.
102 *
103 * exit_unblocked_time() determines a strict partial ordering relation '«' on
104 * the set of scheduler nodes as follows:
105 *
106 * n « m <-> exit_unblocked_time(n) < exit_unblocked_time(m)
107 *
108 * which can be used to heuristically order nodes according to how early they
109 * can unblock an exit node and lead to program termination.
110 */
111 static inline int
exit_unblocked_time(const schedule_node * n)112 exit_unblocked_time(const schedule_node *n)
113 {
114 return n->exit ? n->exit->unblocked_time : INT_MAX;
115 }
116
117 void
set_latency_gen4()118 schedule_node::set_latency_gen4()
119 {
120 int chans = 8;
121 int math_latency = 22;
122
123 switch (inst->opcode) {
124 case SHADER_OPCODE_RCP:
125 this->latency = 1 * chans * math_latency;
126 break;
127 case SHADER_OPCODE_RSQ:
128 this->latency = 2 * chans * math_latency;
129 break;
130 case SHADER_OPCODE_INT_QUOTIENT:
131 case SHADER_OPCODE_SQRT:
132 case SHADER_OPCODE_LOG2:
133 /* full precision log. partial is 2. */
134 this->latency = 3 * chans * math_latency;
135 break;
136 case SHADER_OPCODE_INT_REMAINDER:
137 case SHADER_OPCODE_EXP2:
138 /* full precision. partial is 3, same throughput. */
139 this->latency = 4 * chans * math_latency;
140 break;
141 case SHADER_OPCODE_POW:
142 this->latency = 8 * chans * math_latency;
143 break;
144 case SHADER_OPCODE_SIN:
145 case SHADER_OPCODE_COS:
146 /* minimum latency, max is 12 rounds. */
147 this->latency = 5 * chans * math_latency;
148 break;
149 default:
150 this->latency = 2;
151 break;
152 }
153 }
154
155 void
set_latency_gen7(bool is_haswell)156 schedule_node::set_latency_gen7(bool is_haswell)
157 {
158 switch (inst->opcode) {
159 case BRW_OPCODE_MAD:
160 /* 2 cycles
161 * (since the last two src operands are in different register banks):
162 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
163 *
164 * 3 cycles on IVB, 4 on HSW
165 * (since the last two src operands are in the same register bank):
166 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
167 *
168 * 18 cycles on IVB, 16 on HSW
169 * (since the last two src operands are in different register banks):
170 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
171 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
172 *
173 * 20 cycles on IVB, 18 on HSW
174 * (since the last two src operands are in the same register bank):
175 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
176 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
177 */
178
179 /* Our register allocator doesn't know about register banks, so use the
180 * higher latency.
181 */
182 latency = is_haswell ? 16 : 18;
183 break;
184
185 case BRW_OPCODE_LRP:
186 /* 2 cycles
187 * (since the last two src operands are in different register banks):
188 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
189 *
190 * 3 cycles on IVB, 4 on HSW
191 * (since the last two src operands are in the same register bank):
192 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
193 *
194 * 16 cycles on IVB, 14 on HSW
195 * (since the last two src operands are in different register banks):
196 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
197 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
198 *
199 * 16 cycles
200 * (since the last two src operands are in the same register bank):
201 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
202 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
203 */
204
205 /* Our register allocator doesn't know about register banks, so use the
206 * higher latency.
207 */
208 latency = 14;
209 break;
210
211 case SHADER_OPCODE_RCP:
212 case SHADER_OPCODE_RSQ:
213 case SHADER_OPCODE_SQRT:
214 case SHADER_OPCODE_LOG2:
215 case SHADER_OPCODE_EXP2:
216 case SHADER_OPCODE_SIN:
217 case SHADER_OPCODE_COS:
218 /* 2 cycles:
219 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
220 *
221 * 18 cycles:
222 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
223 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
224 *
225 * Same for exp2, log2, rsq, sqrt, sin, cos.
226 */
227 latency = is_haswell ? 14 : 16;
228 break;
229
230 case SHADER_OPCODE_POW:
231 /* 2 cycles:
232 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
233 *
234 * 26 cycles:
235 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
236 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
237 */
238 latency = is_haswell ? 22 : 24;
239 break;
240
241 case SHADER_OPCODE_TEX:
242 case SHADER_OPCODE_TXD:
243 case SHADER_OPCODE_TXF:
244 case SHADER_OPCODE_TXF_LZ:
245 case SHADER_OPCODE_TXL:
246 case SHADER_OPCODE_TXL_LZ:
247 /* 18 cycles:
248 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
249 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
250 * send(8) g4<1>UW g114<8,8,1>F
251 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
252 *
253 * 697 +/-49 cycles (min 610, n=26):
254 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
255 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
256 * send(8) g4<1>UW g114<8,8,1>F
257 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
258 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
259 *
260 * So the latency on our first texture load of the batchbuffer takes
261 * ~700 cycles, since the caches are cold at that point.
262 *
263 * 840 +/- 92 cycles (min 720, n=25):
264 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
265 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
266 * send(8) g4<1>UW g114<8,8,1>F
267 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
268 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
269 * send(8) g4<1>UW g114<8,8,1>F
270 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
271 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
272 *
273 * On the second load, it takes just an extra ~140 cycles, and after
274 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
275 *
276 * 683 +/- 49 cycles (min = 602, n=47):
277 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
278 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
279 * send(8) g4<1>UW g114<8,8,1>F
280 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
281 * send(8) g50<1>UW g114<8,8,1>F
282 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
283 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
284 *
285 * The unit appears to be pipelined, since this matches up with the
286 * cache-cold case, despite there being two loads here. If you replace
287 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
288 *
289 * So, take some number between the cache-hot 140 cycles and the
290 * cache-cold 700 cycles. No particular tuning was done on this.
291 *
292 * I haven't done significant testing of the non-TEX opcodes. TXL at
293 * least looked about the same as TEX.
294 */
295 latency = 200;
296 break;
297
298 case SHADER_OPCODE_TXS:
299 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
300 * cycles (n=15):
301 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
302 * send(8) g6<1>UW g114<8,8,1>F
303 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
304 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
305 *
306 *
307 * Two loads was 535 +/- 30 cycles (n=19):
308 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
309 * send(16) g6<1>UW g114<8,8,1>F
310 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
311 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
312 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
313 * send(16) g8<1>UW g114<8,8,1>F
314 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
315 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
316 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
317 *
318 * Since the only caches that should matter are just the
319 * instruction/state cache containing the surface state, assume that we
320 * always have hot caches.
321 */
322 latency = 100;
323 break;
324
325 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
326 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
327 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
328 case VS_OPCODE_PULL_CONSTANT_LOAD:
329 /* testing using varying-index pull constants:
330 *
331 * 16 cycles:
332 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
333 * send(8) g4<1>F g4<8,8,1>D
334 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
335 *
336 * ~480 cycles:
337 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
338 * send(8) g4<1>F g4<8,8,1>D
339 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
340 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
341 *
342 * ~620 cycles:
343 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
344 * send(8) g4<1>F g4<8,8,1>D
345 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
346 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
347 * send(8) g4<1>F g4<8,8,1>D
348 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
349 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
350 *
351 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
352 * about 460. We expect to mostly be cache hot, so pick something more
353 * in that direction.
354 */
355 latency = 200;
356 break;
357
358 case SHADER_OPCODE_GEN7_SCRATCH_READ:
359 /* Testing a load from offset 0, that had been previously written:
360 *
361 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
362 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
363 *
364 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
365 * then around 140. Presumably this is cache hit vs miss.
366 */
367 latency = 50;
368 break;
369
370 case VEC4_OPCODE_UNTYPED_ATOMIC:
371 /* See GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
372 latency = 14000;
373 break;
374
375 case VEC4_OPCODE_UNTYPED_SURFACE_READ:
376 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
377 /* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */
378 latency = is_haswell ? 300 : 600;
379 break;
380
381 case SHADER_OPCODE_SEND:
382 switch (inst->sfid) {
383 case BRW_SFID_SAMPLER: {
384 unsigned msg_type = (inst->desc >> 12) & 0x1f;
385 switch (msg_type) {
386 case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO:
387 case GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO:
388 /* See also SHADER_OPCODE_TXS */
389 latency = 100;
390 break;
391
392 default:
393 /* See also SHADER_OPCODE_TEX */
394 latency = 200;
395 break;
396 }
397 break;
398 }
399
400 case GEN6_SFID_DATAPORT_RENDER_CACHE:
401 switch ((inst->desc >> 14) & 0x1f) {
402 case GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE:
403 case GEN7_DATAPORT_RC_TYPED_SURFACE_READ:
404 /* See also SHADER_OPCODE_TYPED_SURFACE_READ */
405 assert(!is_haswell);
406 latency = 600;
407 break;
408
409 case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP:
410 /* See also SHADER_OPCODE_TYPED_ATOMIC */
411 assert(!is_haswell);
412 latency = 14000;
413 break;
414
415 case GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE:
416 /* completely fabricated number */
417 latency = 600;
418 break;
419
420 default:
421 unreachable("Unknown render cache message");
422 }
423 break;
424
425 case GEN7_SFID_DATAPORT_DATA_CACHE:
426 switch ((inst->desc >> 14) & 0x1f) {
427 case BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ:
428 case GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ:
429 case GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE:
430 /* We have no data for this but assume it's a little faster than
431 * untyped surface read/write.
432 */
433 latency = 200;
434 break;
435
436 case GEN7_DATAPORT_DC_DWORD_SCATTERED_READ:
437 case GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE:
438 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ:
439 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE:
440 /* We have no data for this but assume it's roughly the same as
441 * untyped surface read/write.
442 */
443 latency = 300;
444 break;
445
446 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ:
447 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE:
448 /* Test code:
449 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
450 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
451 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
452 * send(8) g4<1>UD g112<8,8,1>UD
453 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
454 * .
455 * . [repeats 8 times]
456 * .
457 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
458 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
459 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
460 * send(8) g4<1>UD g112<8,8,1>UD
461 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
462 *
463 * Running it 100 times as fragment shader on a 128x128 quad
464 * gives an average latency of 583 cycles per surface read,
465 * standard deviation 0.9%.
466 */
467 assert(!is_haswell);
468 latency = 600;
469 break;
470
471 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
472 /* Test code:
473 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
474 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
475 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
476 * send(8) g4<1>ud g112<8,8,1>ud
477 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
478 *
479 * Running it 100 times as fragment shader on a 128x128 quad
480 * gives an average latency of 13867 cycles per atomic op,
481 * standard deviation 3%. Note that this is a rather
482 * pessimistic estimate, the actual latency in cases with few
483 * collisions between threads and favorable pipelining has been
484 * seen to be reduced by a factor of 100.
485 */
486 assert(!is_haswell);
487 latency = 14000;
488 break;
489
490 default:
491 unreachable("Unknown data cache message");
492 }
493 break;
494
495 case HSW_SFID_DATAPORT_DATA_CACHE_1:
496 switch ((inst->desc >> 14) & 0x1f) {
497 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ:
498 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
499 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
500 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE:
501 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE:
502 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ:
503 case GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE:
504 case GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ:
505 case GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ:
506 case GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE:
507 /* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */
508 latency = 300;
509 break;
510
511 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
512 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
513 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
514 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
515 case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP:
516 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP:
517 case GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP:
518 /* See also GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
519 latency = 14000;
520 break;
521
522 default:
523 unreachable("Unknown data cache message");
524 }
525 break;
526
527 default:
528 unreachable("Unknown SFID");
529 }
530 break;
531
532 default:
533 /* 2 cycles:
534 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
535 *
536 * 16 cycles:
537 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
538 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
539 */
540 latency = 14;
541 break;
542 }
543 }
544
545 class instruction_scheduler {
546 public:
instruction_scheduler(const backend_shader * s,int grf_count,unsigned hw_reg_count,int block_count,instruction_scheduler_mode mode)547 instruction_scheduler(const backend_shader *s, int grf_count,
548 unsigned hw_reg_count, int block_count,
549 instruction_scheduler_mode mode):
550 bs(s)
551 {
552 this->mem_ctx = ralloc_context(NULL);
553 this->grf_count = grf_count;
554 this->hw_reg_count = hw_reg_count;
555 this->instructions.make_empty();
556 this->post_reg_alloc = (mode == SCHEDULE_POST);
557 this->mode = mode;
558 this->reg_pressure = 0;
559 this->block_idx = 0;
560 if (!post_reg_alloc) {
561 this->reg_pressure_in = rzalloc_array(mem_ctx, int, block_count);
562
563 this->livein = ralloc_array(mem_ctx, BITSET_WORD *, block_count);
564 for (int i = 0; i < block_count; i++)
565 this->livein[i] = rzalloc_array(mem_ctx, BITSET_WORD,
566 BITSET_WORDS(grf_count));
567
568 this->liveout = ralloc_array(mem_ctx, BITSET_WORD *, block_count);
569 for (int i = 0; i < block_count; i++)
570 this->liveout[i] = rzalloc_array(mem_ctx, BITSET_WORD,
571 BITSET_WORDS(grf_count));
572
573 this->hw_liveout = ralloc_array(mem_ctx, BITSET_WORD *, block_count);
574 for (int i = 0; i < block_count; i++)
575 this->hw_liveout[i] = rzalloc_array(mem_ctx, BITSET_WORD,
576 BITSET_WORDS(hw_reg_count));
577
578 this->written = rzalloc_array(mem_ctx, bool, grf_count);
579
580 this->reads_remaining = rzalloc_array(mem_ctx, int, grf_count);
581
582 this->hw_reads_remaining = rzalloc_array(mem_ctx, int, hw_reg_count);
583 } else {
584 this->reg_pressure_in = NULL;
585 this->livein = NULL;
586 this->liveout = NULL;
587 this->hw_liveout = NULL;
588 this->written = NULL;
589 this->reads_remaining = NULL;
590 this->hw_reads_remaining = NULL;
591 }
592 }
593
~instruction_scheduler()594 ~instruction_scheduler()
595 {
596 ralloc_free(this->mem_ctx);
597 }
598 void add_barrier_deps(schedule_node *n);
599 void add_dep(schedule_node *before, schedule_node *after, int latency);
600 void add_dep(schedule_node *before, schedule_node *after);
601
602 void run(cfg_t *cfg);
603 void add_insts_from_block(bblock_t *block);
604 void compute_delays();
605 void compute_exits();
606 virtual void calculate_deps() = 0;
607 virtual schedule_node *choose_instruction_to_schedule() = 0;
608
609 /**
610 * Returns how many cycles it takes the instruction to issue.
611 *
612 * Instructions in gen hardware are handled one simd4 vector at a time,
613 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
614 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
615 */
616 virtual int issue_time(backend_instruction *inst) = 0;
617
618 virtual void count_reads_remaining(backend_instruction *inst) = 0;
619 virtual void setup_liveness(cfg_t *cfg) = 0;
620 virtual void update_register_pressure(backend_instruction *inst) = 0;
621 virtual int get_register_pressure_benefit(backend_instruction *inst) = 0;
622
623 void schedule_instructions(bblock_t *block);
624
625 void *mem_ctx;
626
627 bool post_reg_alloc;
628 int grf_count;
629 unsigned hw_reg_count;
630 int reg_pressure;
631 int block_idx;
632 exec_list instructions;
633 const backend_shader *bs;
634
635 instruction_scheduler_mode mode;
636
637 /*
638 * The register pressure at the beginning of each basic block.
639 */
640
641 int *reg_pressure_in;
642
643 /*
644 * The virtual GRF's whose range overlaps the beginning of each basic block.
645 */
646
647 BITSET_WORD **livein;
648
649 /*
650 * The virtual GRF's whose range overlaps the end of each basic block.
651 */
652
653 BITSET_WORD **liveout;
654
655 /*
656 * The hardware GRF's whose range overlaps the end of each basic block.
657 */
658
659 BITSET_WORD **hw_liveout;
660
661 /*
662 * Whether we've scheduled a write for this virtual GRF yet.
663 */
664
665 bool *written;
666
667 /*
668 * How many reads we haven't scheduled for this virtual GRF yet.
669 */
670
671 int *reads_remaining;
672
673 /*
674 * How many reads we haven't scheduled for this hardware GRF yet.
675 */
676
677 int *hw_reads_remaining;
678 };
679
680 class fs_instruction_scheduler : public instruction_scheduler
681 {
682 public:
683 fs_instruction_scheduler(const fs_visitor *v, int grf_count, int hw_reg_count,
684 int block_count,
685 instruction_scheduler_mode mode);
686 void calculate_deps();
687 bool is_compressed(const fs_inst *inst);
688 schedule_node *choose_instruction_to_schedule();
689 int issue_time(backend_instruction *inst);
690 const fs_visitor *v;
691
692 void count_reads_remaining(backend_instruction *inst);
693 void setup_liveness(cfg_t *cfg);
694 void update_register_pressure(backend_instruction *inst);
695 int get_register_pressure_benefit(backend_instruction *inst);
696 };
697
fs_instruction_scheduler(const fs_visitor * v,int grf_count,int hw_reg_count,int block_count,instruction_scheduler_mode mode)698 fs_instruction_scheduler::fs_instruction_scheduler(const fs_visitor *v,
699 int grf_count, int hw_reg_count,
700 int block_count,
701 instruction_scheduler_mode mode)
702 : instruction_scheduler(v, grf_count, hw_reg_count, block_count, mode),
703 v(v)
704 {
705 }
706
707 static bool
is_src_duplicate(fs_inst * inst,int src)708 is_src_duplicate(fs_inst *inst, int src)
709 {
710 for (int i = 0; i < src; i++)
711 if (inst->src[i].equals(inst->src[src]))
712 return true;
713
714 return false;
715 }
716
717 void
count_reads_remaining(backend_instruction * be)718 fs_instruction_scheduler::count_reads_remaining(backend_instruction *be)
719 {
720 fs_inst *inst = (fs_inst *)be;
721
722 if (!reads_remaining)
723 return;
724
725 for (int i = 0; i < inst->sources; i++) {
726 if (is_src_duplicate(inst, i))
727 continue;
728
729 if (inst->src[i].file == VGRF) {
730 reads_remaining[inst->src[i].nr]++;
731 } else if (inst->src[i].file == FIXED_GRF) {
732 if (inst->src[i].nr >= hw_reg_count)
733 continue;
734
735 for (unsigned j = 0; j < regs_read(inst, i); j++)
736 hw_reads_remaining[inst->src[i].nr + j]++;
737 }
738 }
739 }
740
741 void
setup_liveness(cfg_t * cfg)742 fs_instruction_scheduler::setup_liveness(cfg_t *cfg)
743 {
744 const fs_live_variables &live = v->live_analysis.require();
745
746 /* First, compute liveness on a per-GRF level using the in/out sets from
747 * liveness calculation.
748 */
749 for (int block = 0; block < cfg->num_blocks; block++) {
750 for (int i = 0; i < live.num_vars; i++) {
751 if (BITSET_TEST(live.block_data[block].livein, i)) {
752 int vgrf = live.vgrf_from_var[i];
753 if (!BITSET_TEST(livein[block], vgrf)) {
754 reg_pressure_in[block] += v->alloc.sizes[vgrf];
755 BITSET_SET(livein[block], vgrf);
756 }
757 }
758
759 if (BITSET_TEST(live.block_data[block].liveout, i))
760 BITSET_SET(liveout[block], live.vgrf_from_var[i]);
761 }
762 }
763
764 /* Now, extend the live in/live out sets for when a range crosses a block
765 * boundary, which matches what our register allocator/interference code
766 * does to account for force_writemask_all and incompatible exec_mask's.
767 */
768 for (int block = 0; block < cfg->num_blocks - 1; block++) {
769 for (int i = 0; i < grf_count; i++) {
770 if (live.vgrf_start[i] <= cfg->blocks[block]->end_ip &&
771 live.vgrf_end[i] >= cfg->blocks[block + 1]->start_ip) {
772 if (!BITSET_TEST(livein[block + 1], i)) {
773 reg_pressure_in[block + 1] += v->alloc.sizes[i];
774 BITSET_SET(livein[block + 1], i);
775 }
776
777 BITSET_SET(liveout[block], i);
778 }
779 }
780 }
781
782 int payload_last_use_ip[hw_reg_count];
783 v->calculate_payload_ranges(hw_reg_count, payload_last_use_ip);
784
785 for (unsigned i = 0; i < hw_reg_count; i++) {
786 if (payload_last_use_ip[i] == -1)
787 continue;
788
789 for (int block = 0; block < cfg->num_blocks; block++) {
790 if (cfg->blocks[block]->start_ip <= payload_last_use_ip[i])
791 reg_pressure_in[block]++;
792
793 if (cfg->blocks[block]->end_ip <= payload_last_use_ip[i])
794 BITSET_SET(hw_liveout[block], i);
795 }
796 }
797 }
798
799 void
update_register_pressure(backend_instruction * be)800 fs_instruction_scheduler::update_register_pressure(backend_instruction *be)
801 {
802 fs_inst *inst = (fs_inst *)be;
803
804 if (!reads_remaining)
805 return;
806
807 if (inst->dst.file == VGRF) {
808 written[inst->dst.nr] = true;
809 }
810
811 for (int i = 0; i < inst->sources; i++) {
812 if (is_src_duplicate(inst, i))
813 continue;
814
815 if (inst->src[i].file == VGRF) {
816 reads_remaining[inst->src[i].nr]--;
817 } else if (inst->src[i].file == FIXED_GRF &&
818 inst->src[i].nr < hw_reg_count) {
819 for (unsigned off = 0; off < regs_read(inst, i); off++)
820 hw_reads_remaining[inst->src[i].nr + off]--;
821 }
822 }
823 }
824
825 int
get_register_pressure_benefit(backend_instruction * be)826 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be)
827 {
828 fs_inst *inst = (fs_inst *)be;
829 int benefit = 0;
830
831 if (inst->dst.file == VGRF) {
832 if (!BITSET_TEST(livein[block_idx], inst->dst.nr) &&
833 !written[inst->dst.nr])
834 benefit -= v->alloc.sizes[inst->dst.nr];
835 }
836
837 for (int i = 0; i < inst->sources; i++) {
838 if (is_src_duplicate(inst, i))
839 continue;
840
841 if (inst->src[i].file == VGRF &&
842 !BITSET_TEST(liveout[block_idx], inst->src[i].nr) &&
843 reads_remaining[inst->src[i].nr] == 1)
844 benefit += v->alloc.sizes[inst->src[i].nr];
845
846 if (inst->src[i].file == FIXED_GRF &&
847 inst->src[i].nr < hw_reg_count) {
848 for (unsigned off = 0; off < regs_read(inst, i); off++) {
849 int reg = inst->src[i].nr + off;
850 if (!BITSET_TEST(hw_liveout[block_idx], reg) &&
851 hw_reads_remaining[reg] == 1) {
852 benefit++;
853 }
854 }
855 }
856 }
857
858 return benefit;
859 }
860
861 class vec4_instruction_scheduler : public instruction_scheduler
862 {
863 public:
864 vec4_instruction_scheduler(const vec4_visitor *v, int grf_count);
865 void calculate_deps();
866 schedule_node *choose_instruction_to_schedule();
867 int issue_time(backend_instruction *inst);
868 const vec4_visitor *v;
869
870 void count_reads_remaining(backend_instruction *inst);
871 void setup_liveness(cfg_t *cfg);
872 void update_register_pressure(backend_instruction *inst);
873 int get_register_pressure_benefit(backend_instruction *inst);
874 };
875
vec4_instruction_scheduler(const vec4_visitor * v,int grf_count)876 vec4_instruction_scheduler::vec4_instruction_scheduler(const vec4_visitor *v,
877 int grf_count)
878 : instruction_scheduler(v, grf_count, 0, 0, SCHEDULE_POST),
879 v(v)
880 {
881 }
882
883 void
count_reads_remaining(backend_instruction *)884 vec4_instruction_scheduler::count_reads_remaining(backend_instruction *)
885 {
886 }
887
888 void
setup_liveness(cfg_t *)889 vec4_instruction_scheduler::setup_liveness(cfg_t *)
890 {
891 }
892
893 void
update_register_pressure(backend_instruction *)894 vec4_instruction_scheduler::update_register_pressure(backend_instruction *)
895 {
896 }
897
898 int
get_register_pressure_benefit(backend_instruction *)899 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction *)
900 {
901 return 0;
902 }
903
schedule_node(backend_instruction * inst,instruction_scheduler * sched)904 schedule_node::schedule_node(backend_instruction *inst,
905 instruction_scheduler *sched)
906 {
907 const struct gen_device_info *devinfo = sched->bs->devinfo;
908
909 this->inst = inst;
910 this->child_array_size = 0;
911 this->children = NULL;
912 this->child_latency = NULL;
913 this->child_count = 0;
914 this->parent_count = 0;
915 this->unblocked_time = 0;
916 this->cand_generation = 0;
917 this->delay = 0;
918 this->exit = NULL;
919
920 /* We can't measure Gen6 timings directly but expect them to be much
921 * closer to Gen7 than Gen4.
922 */
923 if (!sched->post_reg_alloc)
924 this->latency = 1;
925 else if (devinfo->gen >= 6)
926 set_latency_gen7(devinfo->is_haswell);
927 else
928 set_latency_gen4();
929 }
930
931 void
add_insts_from_block(bblock_t * block)932 instruction_scheduler::add_insts_from_block(bblock_t *block)
933 {
934 foreach_inst_in_block(backend_instruction, inst, block) {
935 schedule_node *n = new(mem_ctx) schedule_node(inst, this);
936
937 instructions.push_tail(n);
938 }
939 }
940
941 /** Computation of the delay member of each node. */
942 void
compute_delays()943 instruction_scheduler::compute_delays()
944 {
945 foreach_in_list_reverse(schedule_node, n, &instructions) {
946 if (!n->child_count) {
947 n->delay = issue_time(n->inst);
948 } else {
949 for (int i = 0; i < n->child_count; i++) {
950 assert(n->children[i]->delay);
951 n->delay = MAX2(n->delay, n->latency + n->children[i]->delay);
952 }
953 }
954 }
955 }
956
957 void
compute_exits()958 instruction_scheduler::compute_exits()
959 {
960 /* Calculate a lower bound of the scheduling time of each node in the
961 * graph. This is analogous to the node's critical path but calculated
962 * from the top instead of from the bottom of the block.
963 */
964 foreach_in_list(schedule_node, n, &instructions) {
965 for (int i = 0; i < n->child_count; i++) {
966 n->children[i]->unblocked_time =
967 MAX2(n->children[i]->unblocked_time,
968 n->unblocked_time + issue_time(n->inst) + n->child_latency[i]);
969 }
970 }
971
972 /* Calculate the exit of each node by induction based on the exit nodes of
973 * its children. The preferred exit of a node is the one among the exit
974 * nodes of its children which can be unblocked first according to the
975 * optimistic unblocked time estimate calculated above.
976 */
977 foreach_in_list_reverse(schedule_node, n, &instructions) {
978 n->exit = (n->inst->opcode == FS_OPCODE_DISCARD_JUMP ? n : NULL);
979
980 for (int i = 0; i < n->child_count; i++) {
981 if (exit_unblocked_time(n->children[i]) < exit_unblocked_time(n))
982 n->exit = n->children[i]->exit;
983 }
984 }
985 }
986
987 /**
988 * Add a dependency between two instruction nodes.
989 *
990 * The @after node will be scheduled after @before. We will try to
991 * schedule it @latency cycles after @before, but no guarantees there.
992 */
993 void
add_dep(schedule_node * before,schedule_node * after,int latency)994 instruction_scheduler::add_dep(schedule_node *before, schedule_node *after,
995 int latency)
996 {
997 if (!before || !after)
998 return;
999
1000 assert(before != after);
1001
1002 for (int i = 0; i < before->child_count; i++) {
1003 if (before->children[i] == after) {
1004 before->child_latency[i] = MAX2(before->child_latency[i], latency);
1005 return;
1006 }
1007 }
1008
1009 if (before->child_array_size <= before->child_count) {
1010 if (before->child_array_size < 16)
1011 before->child_array_size = 16;
1012 else
1013 before->child_array_size *= 2;
1014
1015 before->children = reralloc(mem_ctx, before->children,
1016 schedule_node *,
1017 before->child_array_size);
1018 before->child_latency = reralloc(mem_ctx, before->child_latency,
1019 int, before->child_array_size);
1020 }
1021
1022 before->children[before->child_count] = after;
1023 before->child_latency[before->child_count] = latency;
1024 before->child_count++;
1025 after->parent_count++;
1026 }
1027
1028 void
add_dep(schedule_node * before,schedule_node * after)1029 instruction_scheduler::add_dep(schedule_node *before, schedule_node *after)
1030 {
1031 if (!before)
1032 return;
1033
1034 add_dep(before, after, before->latency);
1035 }
1036
1037 static bool
is_scheduling_barrier(const backend_instruction * inst)1038 is_scheduling_barrier(const backend_instruction *inst)
1039 {
1040 return inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
1041 inst->is_control_flow() ||
1042 inst->has_side_effects();
1043 }
1044
1045 /**
1046 * Sometimes we really want this node to execute after everything that
1047 * was before it and before everything that followed it. This adds
1048 * the deps to do so.
1049 */
1050 void
add_barrier_deps(schedule_node * n)1051 instruction_scheduler::add_barrier_deps(schedule_node *n)
1052 {
1053 schedule_node *prev = (schedule_node *)n->prev;
1054 schedule_node *next = (schedule_node *)n->next;
1055
1056 if (prev) {
1057 while (!prev->is_head_sentinel()) {
1058 add_dep(prev, n, 0);
1059 if (is_scheduling_barrier(prev->inst))
1060 break;
1061 prev = (schedule_node *)prev->prev;
1062 }
1063 }
1064
1065 if (next) {
1066 while (!next->is_tail_sentinel()) {
1067 add_dep(n, next, 0);
1068 if (is_scheduling_barrier(next->inst))
1069 break;
1070 next = (schedule_node *)next->next;
1071 }
1072 }
1073 }
1074
1075 /* instruction scheduling needs to be aware of when an MRF write
1076 * actually writes 2 MRFs.
1077 */
1078 bool
is_compressed(const fs_inst * inst)1079 fs_instruction_scheduler::is_compressed(const fs_inst *inst)
1080 {
1081 return inst->exec_size == 16;
1082 }
1083
1084 void
calculate_deps()1085 fs_instruction_scheduler::calculate_deps()
1086 {
1087 /* Pre-register-allocation, this tracks the last write per VGRF offset.
1088 * After register allocation, reg_offsets are gone and we track individual
1089 * GRF registers.
1090 */
1091 schedule_node **last_grf_write;
1092 schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->gen)];
1093 schedule_node *last_conditional_mod[8] = {};
1094 schedule_node *last_accumulator_write = NULL;
1095 /* Fixed HW registers are assumed to be separate from the virtual
1096 * GRFs, so they can be tracked separately. We don't really write
1097 * to fixed GRFs much, so don't bother tracking them on a more
1098 * granular level.
1099 */
1100 schedule_node *last_fixed_grf_write = NULL;
1101
1102 last_grf_write = (schedule_node **)calloc(sizeof(schedule_node *), grf_count * 16);
1103 memset(last_mrf_write, 0, sizeof(last_mrf_write));
1104
1105 /* top-to-bottom dependencies: RAW and WAW. */
1106 foreach_in_list(schedule_node, n, &instructions) {
1107 fs_inst *inst = (fs_inst *)n->inst;
1108
1109 if (is_scheduling_barrier(inst))
1110 add_barrier_deps(n);
1111
1112 /* read-after-write deps. */
1113 for (int i = 0; i < inst->sources; i++) {
1114 if (inst->src[i].file == VGRF) {
1115 if (post_reg_alloc) {
1116 for (unsigned r = 0; r < regs_read(inst, i); r++)
1117 add_dep(last_grf_write[inst->src[i].nr + r], n);
1118 } else {
1119 for (unsigned r = 0; r < regs_read(inst, i); r++) {
1120 add_dep(last_grf_write[inst->src[i].nr * 16 +
1121 inst->src[i].offset / REG_SIZE + r], n);
1122 }
1123 }
1124 } else if (inst->src[i].file == FIXED_GRF) {
1125 if (post_reg_alloc) {
1126 for (unsigned r = 0; r < regs_read(inst, i); r++)
1127 add_dep(last_grf_write[inst->src[i].nr + r], n);
1128 } else {
1129 add_dep(last_fixed_grf_write, n);
1130 }
1131 } else if (inst->src[i].is_accumulator()) {
1132 add_dep(last_accumulator_write, n);
1133 } else if (inst->src[i].file == ARF) {
1134 add_barrier_deps(n);
1135 }
1136 }
1137
1138 if (inst->base_mrf != -1) {
1139 for (int i = 0; i < inst->mlen; i++) {
1140 /* It looks like the MRF regs are released in the send
1141 * instruction once it's sent, not when the result comes
1142 * back.
1143 */
1144 add_dep(last_mrf_write[inst->base_mrf + i], n);
1145 }
1146 }
1147
1148 if (const unsigned mask = inst->flags_read(v->devinfo)) {
1149 assert(mask < (1 << ARRAY_SIZE(last_conditional_mod)));
1150
1151 for (unsigned i = 0; i < ARRAY_SIZE(last_conditional_mod); i++) {
1152 if (mask & (1 << i))
1153 add_dep(last_conditional_mod[i], n);
1154 }
1155 }
1156
1157 if (inst->reads_accumulator_implicitly()) {
1158 add_dep(last_accumulator_write, n);
1159 }
1160
1161 /* write-after-write deps. */
1162 if (inst->dst.file == VGRF) {
1163 if (post_reg_alloc) {
1164 for (unsigned r = 0; r < regs_written(inst); r++) {
1165 add_dep(last_grf_write[inst->dst.nr + r], n);
1166 last_grf_write[inst->dst.nr + r] = n;
1167 }
1168 } else {
1169 for (unsigned r = 0; r < regs_written(inst); r++) {
1170 add_dep(last_grf_write[inst->dst.nr * 16 +
1171 inst->dst.offset / REG_SIZE + r], n);
1172 last_grf_write[inst->dst.nr * 16 +
1173 inst->dst.offset / REG_SIZE + r] = n;
1174 }
1175 }
1176 } else if (inst->dst.file == MRF) {
1177 int reg = inst->dst.nr & ~BRW_MRF_COMPR4;
1178
1179 add_dep(last_mrf_write[reg], n);
1180 last_mrf_write[reg] = n;
1181 if (is_compressed(inst)) {
1182 if (inst->dst.nr & BRW_MRF_COMPR4)
1183 reg += 4;
1184 else
1185 reg++;
1186 add_dep(last_mrf_write[reg], n);
1187 last_mrf_write[reg] = n;
1188 }
1189 } else if (inst->dst.file == FIXED_GRF) {
1190 if (post_reg_alloc) {
1191 for (unsigned r = 0; r < regs_written(inst); r++)
1192 last_grf_write[inst->dst.nr + r] = n;
1193 } else {
1194 last_fixed_grf_write = n;
1195 }
1196 } else if (inst->dst.is_accumulator()) {
1197 add_dep(last_accumulator_write, n);
1198 last_accumulator_write = n;
1199 } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
1200 add_barrier_deps(n);
1201 }
1202
1203 if (inst->mlen > 0 && inst->base_mrf != -1) {
1204 for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
1205 add_dep(last_mrf_write[inst->base_mrf + i], n);
1206 last_mrf_write[inst->base_mrf + i] = n;
1207 }
1208 }
1209
1210 if (const unsigned mask = inst->flags_written()) {
1211 assert(mask < (1 << ARRAY_SIZE(last_conditional_mod)));
1212
1213 for (unsigned i = 0; i < ARRAY_SIZE(last_conditional_mod); i++) {
1214 if (mask & (1 << i)) {
1215 add_dep(last_conditional_mod[i], n, 0);
1216 last_conditional_mod[i] = n;
1217 }
1218 }
1219 }
1220
1221 if (inst->writes_accumulator_implicitly(v->devinfo) &&
1222 !inst->dst.is_accumulator()) {
1223 add_dep(last_accumulator_write, n);
1224 last_accumulator_write = n;
1225 }
1226 }
1227
1228 /* bottom-to-top dependencies: WAR */
1229 memset(last_grf_write, 0, sizeof(schedule_node *) * grf_count * 16);
1230 memset(last_mrf_write, 0, sizeof(last_mrf_write));
1231 memset(last_conditional_mod, 0, sizeof(last_conditional_mod));
1232 last_accumulator_write = NULL;
1233 last_fixed_grf_write = NULL;
1234
1235 foreach_in_list_reverse_safe(schedule_node, n, &instructions) {
1236 fs_inst *inst = (fs_inst *)n->inst;
1237
1238 /* write-after-read deps. */
1239 for (int i = 0; i < inst->sources; i++) {
1240 if (inst->src[i].file == VGRF) {
1241 if (post_reg_alloc) {
1242 for (unsigned r = 0; r < regs_read(inst, i); r++)
1243 add_dep(n, last_grf_write[inst->src[i].nr + r], 0);
1244 } else {
1245 for (unsigned r = 0; r < regs_read(inst, i); r++) {
1246 add_dep(n, last_grf_write[inst->src[i].nr * 16 +
1247 inst->src[i].offset / REG_SIZE + r], 0);
1248 }
1249 }
1250 } else if (inst->src[i].file == FIXED_GRF) {
1251 if (post_reg_alloc) {
1252 for (unsigned r = 0; r < regs_read(inst, i); r++)
1253 add_dep(n, last_grf_write[inst->src[i].nr + r], 0);
1254 } else {
1255 add_dep(n, last_fixed_grf_write, 0);
1256 }
1257 } else if (inst->src[i].is_accumulator()) {
1258 add_dep(n, last_accumulator_write, 0);
1259 } else if (inst->src[i].file == ARF) {
1260 add_barrier_deps(n);
1261 }
1262 }
1263
1264 if (inst->base_mrf != -1) {
1265 for (int i = 0; i < inst->mlen; i++) {
1266 /* It looks like the MRF regs are released in the send
1267 * instruction once it's sent, not when the result comes
1268 * back.
1269 */
1270 add_dep(n, last_mrf_write[inst->base_mrf + i], 2);
1271 }
1272 }
1273
1274 if (const unsigned mask = inst->flags_read(v->devinfo)) {
1275 assert(mask < (1 << ARRAY_SIZE(last_conditional_mod)));
1276
1277 for (unsigned i = 0; i < ARRAY_SIZE(last_conditional_mod); i++) {
1278 if (mask & (1 << i))
1279 add_dep(n, last_conditional_mod[i]);
1280 }
1281 }
1282
1283 if (inst->reads_accumulator_implicitly()) {
1284 add_dep(n, last_accumulator_write);
1285 }
1286
1287 /* Update the things this instruction wrote, so earlier reads
1288 * can mark this as WAR dependency.
1289 */
1290 if (inst->dst.file == VGRF) {
1291 if (post_reg_alloc) {
1292 for (unsigned r = 0; r < regs_written(inst); r++)
1293 last_grf_write[inst->dst.nr + r] = n;
1294 } else {
1295 for (unsigned r = 0; r < regs_written(inst); r++) {
1296 last_grf_write[inst->dst.nr * 16 +
1297 inst->dst.offset / REG_SIZE + r] = n;
1298 }
1299 }
1300 } else if (inst->dst.file == MRF) {
1301 int reg = inst->dst.nr & ~BRW_MRF_COMPR4;
1302
1303 last_mrf_write[reg] = n;
1304
1305 if (is_compressed(inst)) {
1306 if (inst->dst.nr & BRW_MRF_COMPR4)
1307 reg += 4;
1308 else
1309 reg++;
1310
1311 last_mrf_write[reg] = n;
1312 }
1313 } else if (inst->dst.file == FIXED_GRF) {
1314 if (post_reg_alloc) {
1315 for (unsigned r = 0; r < regs_written(inst); r++)
1316 last_grf_write[inst->dst.nr + r] = n;
1317 } else {
1318 last_fixed_grf_write = n;
1319 }
1320 } else if (inst->dst.is_accumulator()) {
1321 last_accumulator_write = n;
1322 } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
1323 add_barrier_deps(n);
1324 }
1325
1326 if (inst->mlen > 0 && inst->base_mrf != -1) {
1327 for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
1328 last_mrf_write[inst->base_mrf + i] = n;
1329 }
1330 }
1331
1332 if (const unsigned mask = inst->flags_written()) {
1333 assert(mask < (1 << ARRAY_SIZE(last_conditional_mod)));
1334
1335 for (unsigned i = 0; i < ARRAY_SIZE(last_conditional_mod); i++) {
1336 if (mask & (1 << i))
1337 last_conditional_mod[i] = n;
1338 }
1339 }
1340
1341 if (inst->writes_accumulator_implicitly(v->devinfo)) {
1342 last_accumulator_write = n;
1343 }
1344 }
1345
1346 free(last_grf_write);
1347 }
1348
1349 void
calculate_deps()1350 vec4_instruction_scheduler::calculate_deps()
1351 {
1352 schedule_node *last_grf_write[grf_count];
1353 schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->gen)];
1354 schedule_node *last_conditional_mod = NULL;
1355 schedule_node *last_accumulator_write = NULL;
1356 /* Fixed HW registers are assumed to be separate from the virtual
1357 * GRFs, so they can be tracked separately. We don't really write
1358 * to fixed GRFs much, so don't bother tracking them on a more
1359 * granular level.
1360 */
1361 schedule_node *last_fixed_grf_write = NULL;
1362
1363 memset(last_grf_write, 0, sizeof(last_grf_write));
1364 memset(last_mrf_write, 0, sizeof(last_mrf_write));
1365
1366 /* top-to-bottom dependencies: RAW and WAW. */
1367 foreach_in_list(schedule_node, n, &instructions) {
1368 vec4_instruction *inst = (vec4_instruction *)n->inst;
1369
1370 if (is_scheduling_barrier(inst))
1371 add_barrier_deps(n);
1372
1373 /* read-after-write deps. */
1374 for (int i = 0; i < 3; i++) {
1375 if (inst->src[i].file == VGRF) {
1376 for (unsigned j = 0; j < regs_read(inst, i); ++j)
1377 add_dep(last_grf_write[inst->src[i].nr + j], n);
1378 } else if (inst->src[i].file == FIXED_GRF) {
1379 add_dep(last_fixed_grf_write, n);
1380 } else if (inst->src[i].is_accumulator()) {
1381 assert(last_accumulator_write);
1382 add_dep(last_accumulator_write, n);
1383 } else if (inst->src[i].file == ARF) {
1384 add_barrier_deps(n);
1385 }
1386 }
1387
1388 if (inst->reads_g0_implicitly())
1389 add_dep(last_fixed_grf_write, n);
1390
1391 if (!inst->is_send_from_grf()) {
1392 for (int i = 0; i < inst->mlen; i++) {
1393 /* It looks like the MRF regs are released in the send
1394 * instruction once it's sent, not when the result comes
1395 * back.
1396 */
1397 add_dep(last_mrf_write[inst->base_mrf + i], n);
1398 }
1399 }
1400
1401 if (inst->reads_flag()) {
1402 assert(last_conditional_mod);
1403 add_dep(last_conditional_mod, n);
1404 }
1405
1406 if (inst->reads_accumulator_implicitly()) {
1407 assert(last_accumulator_write);
1408 add_dep(last_accumulator_write, n);
1409 }
1410
1411 /* write-after-write deps. */
1412 if (inst->dst.file == VGRF) {
1413 for (unsigned j = 0; j < regs_written(inst); ++j) {
1414 add_dep(last_grf_write[inst->dst.nr + j], n);
1415 last_grf_write[inst->dst.nr + j] = n;
1416 }
1417 } else if (inst->dst.file == MRF) {
1418 add_dep(last_mrf_write[inst->dst.nr], n);
1419 last_mrf_write[inst->dst.nr] = n;
1420 } else if (inst->dst.file == FIXED_GRF) {
1421 last_fixed_grf_write = n;
1422 } else if (inst->dst.is_accumulator()) {
1423 add_dep(last_accumulator_write, n);
1424 last_accumulator_write = n;
1425 } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
1426 add_barrier_deps(n);
1427 }
1428
1429 if (inst->mlen > 0 && !inst->is_send_from_grf()) {
1430 for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
1431 add_dep(last_mrf_write[inst->base_mrf + i], n);
1432 last_mrf_write[inst->base_mrf + i] = n;
1433 }
1434 }
1435
1436 if (inst->writes_flag()) {
1437 add_dep(last_conditional_mod, n, 0);
1438 last_conditional_mod = n;
1439 }
1440
1441 if (inst->writes_accumulator_implicitly(v->devinfo) &&
1442 !inst->dst.is_accumulator()) {
1443 add_dep(last_accumulator_write, n);
1444 last_accumulator_write = n;
1445 }
1446 }
1447
1448 /* bottom-to-top dependencies: WAR */
1449 memset(last_grf_write, 0, sizeof(last_grf_write));
1450 memset(last_mrf_write, 0, sizeof(last_mrf_write));
1451 last_conditional_mod = NULL;
1452 last_accumulator_write = NULL;
1453 last_fixed_grf_write = NULL;
1454
1455 foreach_in_list_reverse_safe(schedule_node, n, &instructions) {
1456 vec4_instruction *inst = (vec4_instruction *)n->inst;
1457
1458 /* write-after-read deps. */
1459 for (int i = 0; i < 3; i++) {
1460 if (inst->src[i].file == VGRF) {
1461 for (unsigned j = 0; j < regs_read(inst, i); ++j)
1462 add_dep(n, last_grf_write[inst->src[i].nr + j]);
1463 } else if (inst->src[i].file == FIXED_GRF) {
1464 add_dep(n, last_fixed_grf_write);
1465 } else if (inst->src[i].is_accumulator()) {
1466 add_dep(n, last_accumulator_write);
1467 } else if (inst->src[i].file == ARF) {
1468 add_barrier_deps(n);
1469 }
1470 }
1471
1472 if (!inst->is_send_from_grf()) {
1473 for (int i = 0; i < inst->mlen; i++) {
1474 /* It looks like the MRF regs are released in the send
1475 * instruction once it's sent, not when the result comes
1476 * back.
1477 */
1478 add_dep(n, last_mrf_write[inst->base_mrf + i], 2);
1479 }
1480 }
1481
1482 if (inst->reads_flag()) {
1483 add_dep(n, last_conditional_mod);
1484 }
1485
1486 if (inst->reads_accumulator_implicitly()) {
1487 add_dep(n, last_accumulator_write);
1488 }
1489
1490 /* Update the things this instruction wrote, so earlier reads
1491 * can mark this as WAR dependency.
1492 */
1493 if (inst->dst.file == VGRF) {
1494 for (unsigned j = 0; j < regs_written(inst); ++j)
1495 last_grf_write[inst->dst.nr + j] = n;
1496 } else if (inst->dst.file == MRF) {
1497 last_mrf_write[inst->dst.nr] = n;
1498 } else if (inst->dst.file == FIXED_GRF) {
1499 last_fixed_grf_write = n;
1500 } else if (inst->dst.is_accumulator()) {
1501 last_accumulator_write = n;
1502 } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
1503 add_barrier_deps(n);
1504 }
1505
1506 if (inst->mlen > 0 && !inst->is_send_from_grf()) {
1507 for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
1508 last_mrf_write[inst->base_mrf + i] = n;
1509 }
1510 }
1511
1512 if (inst->writes_flag()) {
1513 last_conditional_mod = n;
1514 }
1515
1516 if (inst->writes_accumulator_implicitly(v->devinfo)) {
1517 last_accumulator_write = n;
1518 }
1519 }
1520 }
1521
1522 schedule_node *
choose_instruction_to_schedule()1523 fs_instruction_scheduler::choose_instruction_to_schedule()
1524 {
1525 schedule_node *chosen = NULL;
1526
1527 if (mode == SCHEDULE_PRE || mode == SCHEDULE_POST) {
1528 int chosen_time = 0;
1529
1530 /* Of the instructions ready to execute or the closest to being ready,
1531 * choose the one most likely to unblock an early program exit, or
1532 * otherwise the oldest one.
1533 */
1534 foreach_in_list(schedule_node, n, &instructions) {
1535 if (!chosen ||
1536 exit_unblocked_time(n) < exit_unblocked_time(chosen) ||
1537 (exit_unblocked_time(n) == exit_unblocked_time(chosen) &&
1538 n->unblocked_time < chosen_time)) {
1539 chosen = n;
1540 chosen_time = n->unblocked_time;
1541 }
1542 }
1543 } else {
1544 /* Before register allocation, we don't care about the latencies of
1545 * instructions. All we care about is reducing live intervals of
1546 * variables so that we can avoid register spilling, or get SIMD16
1547 * shaders which naturally do a better job of hiding instruction
1548 * latency.
1549 */
1550 foreach_in_list(schedule_node, n, &instructions) {
1551 fs_inst *inst = (fs_inst *)n->inst;
1552
1553 if (!chosen) {
1554 chosen = n;
1555 continue;
1556 }
1557
1558 /* Most important: If we can definitely reduce register pressure, do
1559 * so immediately.
1560 */
1561 int register_pressure_benefit = get_register_pressure_benefit(n->inst);
1562 int chosen_register_pressure_benefit =
1563 get_register_pressure_benefit(chosen->inst);
1564
1565 if (register_pressure_benefit > 0 &&
1566 register_pressure_benefit > chosen_register_pressure_benefit) {
1567 chosen = n;
1568 continue;
1569 } else if (chosen_register_pressure_benefit > 0 &&
1570 (register_pressure_benefit <
1571 chosen_register_pressure_benefit)) {
1572 continue;
1573 }
1574
1575 if (mode == SCHEDULE_PRE_LIFO) {
1576 /* Prefer instructions that recently became available for
1577 * scheduling. These are the things that are most likely to
1578 * (eventually) make a variable dead and reduce register pressure.
1579 * Typical register pressure estimates don't work for us because
1580 * most of our pressure comes from texturing, where no single
1581 * instruction to schedule will make a vec4 value dead.
1582 */
1583 if (n->cand_generation > chosen->cand_generation) {
1584 chosen = n;
1585 continue;
1586 } else if (n->cand_generation < chosen->cand_generation) {
1587 continue;
1588 }
1589
1590 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1591 * do this, then because we prefer instructions that just became
1592 * candidates, we'll end up in a pattern of scheduling a SEND,
1593 * then the MRFs for the next SEND, then the next SEND, then the
1594 * MRFs, etc., without ever consuming the results of a send.
1595 */
1596 if (v->devinfo->gen < 7) {
1597 fs_inst *chosen_inst = (fs_inst *)chosen->inst;
1598
1599 /* We use size_written > 4 * exec_size as our test for the kind
1600 * of send instruction to avoid -- only sends generate many
1601 * regs, and a single-result send is probably actually reducing
1602 * register pressure.
1603 */
1604 if (inst->size_written <= 4 * inst->exec_size &&
1605 chosen_inst->size_written > 4 * chosen_inst->exec_size) {
1606 chosen = n;
1607 continue;
1608 } else if (inst->size_written > chosen_inst->size_written) {
1609 continue;
1610 }
1611 }
1612 }
1613
1614 /* For instructions pushed on the cands list at the same time, prefer
1615 * the one with the highest delay to the end of the program. This is
1616 * most likely to have its values able to be consumed first (such as
1617 * for a large tree of lowered ubo loads, which appear reversed in
1618 * the instruction stream with respect to when they can be consumed).
1619 */
1620 if (n->delay > chosen->delay) {
1621 chosen = n;
1622 continue;
1623 } else if (n->delay < chosen->delay) {
1624 continue;
1625 }
1626
1627 /* Prefer the node most likely to unblock an early program exit.
1628 */
1629 if (exit_unblocked_time(n) < exit_unblocked_time(chosen)) {
1630 chosen = n;
1631 continue;
1632 } else if (exit_unblocked_time(n) > exit_unblocked_time(chosen)) {
1633 continue;
1634 }
1635
1636 /* If all other metrics are equal, we prefer the first instruction in
1637 * the list (program execution).
1638 */
1639 }
1640 }
1641
1642 return chosen;
1643 }
1644
1645 schedule_node *
choose_instruction_to_schedule()1646 vec4_instruction_scheduler::choose_instruction_to_schedule()
1647 {
1648 schedule_node *chosen = NULL;
1649 int chosen_time = 0;
1650
1651 /* Of the instructions ready to execute or the closest to being ready,
1652 * choose the oldest one.
1653 */
1654 foreach_in_list(schedule_node, n, &instructions) {
1655 if (!chosen || n->unblocked_time < chosen_time) {
1656 chosen = n;
1657 chosen_time = n->unblocked_time;
1658 }
1659 }
1660
1661 return chosen;
1662 }
1663
1664 int
issue_time(backend_instruction * inst0)1665 fs_instruction_scheduler::issue_time(backend_instruction *inst0)
1666 {
1667 const fs_inst *inst = static_cast<fs_inst *>(inst0);
1668 const unsigned overhead = v->grf_used && has_bank_conflict(v->devinfo, inst) ?
1669 DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE) : 0;
1670 if (is_compressed(inst))
1671 return 4 + overhead;
1672 else
1673 return 2 + overhead;
1674 }
1675
1676 int
issue_time(backend_instruction *)1677 vec4_instruction_scheduler::issue_time(backend_instruction *)
1678 {
1679 /* We always execute as two vec4s in parallel. */
1680 return 2;
1681 }
1682
1683 void
schedule_instructions(bblock_t * block)1684 instruction_scheduler::schedule_instructions(bblock_t *block)
1685 {
1686 const struct gen_device_info *devinfo = bs->devinfo;
1687 int time = 0;
1688 int instructions_to_schedule = block->end_ip - block->start_ip + 1;
1689
1690 if (!post_reg_alloc)
1691 reg_pressure = reg_pressure_in[block->num];
1692 block_idx = block->num;
1693
1694 /* Remove non-DAG heads from the list. */
1695 foreach_in_list_safe(schedule_node, n, &instructions) {
1696 if (n->parent_count != 0)
1697 n->remove();
1698 }
1699
1700 unsigned cand_generation = 1;
1701 while (!instructions.is_empty()) {
1702 schedule_node *chosen = choose_instruction_to_schedule();
1703
1704 /* Schedule this instruction. */
1705 assert(chosen);
1706 chosen->remove();
1707 chosen->inst->exec_node::remove();
1708 block->instructions.push_tail(chosen->inst);
1709 instructions_to_schedule--;
1710
1711 if (!post_reg_alloc) {
1712 reg_pressure -= get_register_pressure_benefit(chosen->inst);
1713 update_register_pressure(chosen->inst);
1714 }
1715
1716 /* If we expected a delay for scheduling, then bump the clock to reflect
1717 * that. In reality, the hardware will switch to another hyperthread
1718 * and may not return to dispatching our thread for a while even after
1719 * we're unblocked. After this, we have the time when the chosen
1720 * instruction will start executing.
1721 */
1722 time = MAX2(time, chosen->unblocked_time);
1723
1724 /* Update the clock for how soon an instruction could start after the
1725 * chosen one.
1726 */
1727 time += issue_time(chosen->inst);
1728
1729 if (debug) {
1730 fprintf(stderr, "clock %4d, scheduled: ", time);
1731 bs->dump_instruction(chosen->inst);
1732 if (!post_reg_alloc)
1733 fprintf(stderr, "(register pressure %d)\n", reg_pressure);
1734 }
1735
1736 /* Now that we've scheduled a new instruction, some of its
1737 * children can be promoted to the list of instructions ready to
1738 * be scheduled. Update the children's unblocked time for this
1739 * DAG edge as we do so.
1740 */
1741 for (int i = chosen->child_count - 1; i >= 0; i--) {
1742 schedule_node *child = chosen->children[i];
1743
1744 child->unblocked_time = MAX2(child->unblocked_time,
1745 time + chosen->child_latency[i]);
1746
1747 if (debug) {
1748 fprintf(stderr, "\tchild %d, %d parents: ", i, child->parent_count);
1749 bs->dump_instruction(child->inst);
1750 }
1751
1752 child->cand_generation = cand_generation;
1753 child->parent_count--;
1754 if (child->parent_count == 0) {
1755 if (debug) {
1756 fprintf(stderr, "\t\tnow available\n");
1757 }
1758 instructions.push_head(child);
1759 }
1760 }
1761 cand_generation++;
1762
1763 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1764 * but it's more limited pre-gen6, so if we send something off to it then
1765 * the next math instruction isn't going to make progress until the first
1766 * is done.
1767 */
1768 if (devinfo->gen < 6 && chosen->inst->is_math()) {
1769 foreach_in_list(schedule_node, n, &instructions) {
1770 if (n->inst->is_math())
1771 n->unblocked_time = MAX2(n->unblocked_time,
1772 time + chosen->latency);
1773 }
1774 }
1775 }
1776
1777 assert(instructions_to_schedule == 0);
1778 }
1779
1780 void
run(cfg_t * cfg)1781 instruction_scheduler::run(cfg_t *cfg)
1782 {
1783 if (debug && !post_reg_alloc) {
1784 fprintf(stderr, "\nInstructions before scheduling (reg_alloc %d)\n",
1785 post_reg_alloc);
1786 bs->dump_instructions();
1787 }
1788
1789 if (!post_reg_alloc)
1790 setup_liveness(cfg);
1791
1792 foreach_block(block, cfg) {
1793 if (reads_remaining) {
1794 memset(reads_remaining, 0,
1795 grf_count * sizeof(*reads_remaining));
1796 memset(hw_reads_remaining, 0,
1797 hw_reg_count * sizeof(*hw_reads_remaining));
1798 memset(written, 0, grf_count * sizeof(*written));
1799
1800 foreach_inst_in_block(fs_inst, inst, block)
1801 count_reads_remaining(inst);
1802 }
1803
1804 add_insts_from_block(block);
1805
1806 calculate_deps();
1807
1808 compute_delays();
1809 compute_exits();
1810
1811 schedule_instructions(block);
1812 }
1813
1814 if (debug && !post_reg_alloc) {
1815 fprintf(stderr, "\nInstructions after scheduling (reg_alloc %d)\n",
1816 post_reg_alloc);
1817 bs->dump_instructions();
1818 }
1819 }
1820
1821 void
schedule_instructions(instruction_scheduler_mode mode)1822 fs_visitor::schedule_instructions(instruction_scheduler_mode mode)
1823 {
1824 int grf_count;
1825 if (mode == SCHEDULE_POST)
1826 grf_count = grf_used;
1827 else
1828 grf_count = alloc.count;
1829
1830 fs_instruction_scheduler sched(this, grf_count, first_non_payload_grf,
1831 cfg->num_blocks, mode);
1832 sched.run(cfg);
1833
1834 invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
1835 }
1836
1837 void
opt_schedule_instructions()1838 vec4_visitor::opt_schedule_instructions()
1839 {
1840 vec4_instruction_scheduler sched(this, prog_data->total_grf);
1841 sched.run(cfg);
1842
1843 invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
1844 }
1845