1 /*
2 * Copyright (C) 2019 Collabora, Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include <xf86drm.h>
28
29 #include "util/u_math.h"
30 #include "util/macros.h"
31 #include "util/hash_table.h"
32 #include "util/u_thread.h"
33 #include "drm-uapi/panfrost_drm.h"
34 #include "pan_encoder.h"
35 #include "pan_device.h"
36 #include "panfrost-quirks.h"
37 #include "pan_bo.h"
38 #include "pan_texture.h"
39
40 /* Abstraction over the raw drm_panfrost_get_param ioctl for fetching
41 * information about devices */
42
43 static __u64
panfrost_query_raw(int fd,enum drm_panfrost_param param,bool required,unsigned default_value)44 panfrost_query_raw(
45 int fd,
46 enum drm_panfrost_param param,
47 bool required,
48 unsigned default_value)
49 {
50 struct drm_panfrost_get_param get_param = {0,};
51 ASSERTED int ret;
52
53 get_param.param = param;
54 ret = drmIoctl(fd, DRM_IOCTL_PANFROST_GET_PARAM, &get_param);
55
56 if (ret) {
57 assert(!required);
58 return default_value;
59 }
60
61 return get_param.value;
62 }
63
64 static unsigned
panfrost_query_gpu_version(int fd)65 panfrost_query_gpu_version(int fd)
66 {
67 return panfrost_query_raw(fd, DRM_PANFROST_PARAM_GPU_PROD_ID, true, 0);
68 }
69
70 static unsigned
panfrost_query_core_count(int fd)71 panfrost_query_core_count(int fd)
72 {
73 /* On older kernels, worst-case to 16 cores */
74
75 unsigned mask = panfrost_query_raw(fd,
76 DRM_PANFROST_PARAM_SHADER_PRESENT, false, 0xffff);
77
78 return util_bitcount(mask);
79 }
80
81 /* Architectural maximums, since this register may be not implemented
82 * by a given chip. G31 is actually 512 instead of 768 but it doesn't
83 * really matter. */
84
85 static unsigned
panfrost_max_thread_count(unsigned arch)86 panfrost_max_thread_count(unsigned arch)
87 {
88 switch (arch) {
89 /* Midgard */
90 case 4:
91 case 5:
92 return 256;
93
94 /* Bifrost, first generation */
95 case 6:
96 return 384;
97
98 /* Bifrost, second generation (G31 is 512 but it doesn't matter) */
99 case 7:
100 return 768;
101
102 /* Valhall (for completeness) */
103 default:
104 return 1024;
105 }
106 }
107
108 static unsigned
panfrost_query_thread_tls_alloc(int fd,unsigned major)109 panfrost_query_thread_tls_alloc(int fd, unsigned major)
110 {
111 unsigned tls = panfrost_query_raw(fd,
112 DRM_PANFROST_PARAM_THREAD_TLS_ALLOC, false, 0);
113
114 return (tls > 0) ? tls : panfrost_max_thread_count(major);
115 }
116
117 static uint32_t
panfrost_query_compressed_formats(int fd)118 panfrost_query_compressed_formats(int fd)
119 {
120 /* If unspecified, assume ASTC/ETC only. Factory default for Juno, and
121 * should exist on any Mali configuration. All hardware should report
122 * these texture formats but the kernel might not be new enough. */
123
124 uint32_t default_set =
125 (1 << MALI_ETC2_RGB8) |
126 (1 << MALI_ETC2_R11_UNORM) |
127 (1 << MALI_ETC2_RGBA8) |
128 (1 << MALI_ETC2_RG11_UNORM) |
129 (1 << MALI_ETC2_R11_SNORM) |
130 (1 << MALI_ETC2_RG11_SNORM) |
131 (1 << MALI_ETC2_RGB8A1) |
132 (1 << MALI_ASTC_3D_LDR) |
133 (1 << MALI_ASTC_3D_HDR) |
134 (1 << MALI_ASTC_2D_LDR) |
135 (1 << MALI_ASTC_2D_HDR);
136
137 return panfrost_query_raw(fd, DRM_PANFROST_PARAM_TEXTURE_FEATURES0,
138 false, default_set);
139 }
140
141 /* DRM_PANFROST_PARAM_TEXTURE_FEATURES0 will return a bitmask of supported
142 * compressed formats, so we offer a helper to test if a format is supported */
143
144 bool
panfrost_supports_compressed_format(struct panfrost_device * dev,unsigned fmt)145 panfrost_supports_compressed_format(struct panfrost_device *dev, unsigned fmt)
146 {
147 if (MALI_EXTRACT_TYPE(fmt) != MALI_FORMAT_COMPRESSED)
148 return true;
149
150 unsigned idx = fmt & ~MALI_FORMAT_COMPRESSED;
151 assert(idx < 32);
152
153 return dev->compressed_formats & (1 << idx);
154 }
155
156 /* Returns the architecture version given a GPU ID, either from a table for
157 * old-style Midgard versions or directly for new-style Bifrost/Valhall
158 * versions */
159
160 static unsigned
panfrost_major_version(unsigned gpu_id)161 panfrost_major_version(unsigned gpu_id)
162 {
163 switch (gpu_id) {
164 case 0x600:
165 case 0x620:
166 case 0x720:
167 return 4;
168 case 0x750:
169 case 0x820:
170 case 0x830:
171 case 0x860:
172 case 0x880:
173 return 5;
174 default:
175 return gpu_id >> 12;
176 }
177 }
178
179 /* Given a GPU ID like 0x860, return a prettified model name */
180
181 const char *
panfrost_model_name(unsigned gpu_id)182 panfrost_model_name(unsigned gpu_id)
183 {
184 switch (gpu_id) {
185 case 0x600: return "Mali T600 (Panfrost)";
186 case 0x620: return "Mali T620 (Panfrost)";
187 case 0x720: return "Mali T720 (Panfrost)";
188 case 0x820: return "Mali T820 (Panfrost)";
189 case 0x830: return "Mali T830 (Panfrost)";
190 case 0x750: return "Mali T760 (Panfrost)";
191 case 0x860: return "Mali T860 (Panfrost)";
192 case 0x880: return "Mali T880 (Panfrost)";
193 case 0x6221: return "Mali G72 (Panfrost)";
194 case 0x7093: return "Mali G31 (Panfrost)";
195 case 0x7212: return "Mali G52 (Panfrost)";
196 default:
197 unreachable("Invalid GPU ID");
198 }
199 }
200
201 void
panfrost_open_device(void * memctx,int fd,struct panfrost_device * dev)202 panfrost_open_device(void *memctx, int fd, struct panfrost_device *dev)
203 {
204 dev->fd = fd;
205 dev->memctx = memctx;
206 dev->gpu_id = panfrost_query_gpu_version(fd);
207 dev->arch = panfrost_major_version(dev->gpu_id);
208 dev->core_count = panfrost_query_core_count(fd);
209 dev->thread_tls_alloc = panfrost_query_thread_tls_alloc(fd, dev->arch);
210 dev->kernel_version = drmGetVersion(fd);
211 dev->quirks = panfrost_get_quirks(dev->gpu_id);
212 dev->compressed_formats = panfrost_query_compressed_formats(fd);
213
214 if (dev->quirks & HAS_SWIZZLES)
215 dev->formats = panfrost_pipe_format_v6;
216 else
217 dev->formats = panfrost_pipe_format_v7;
218
219 util_sparse_array_init(&dev->bo_map, sizeof(struct panfrost_bo), 512);
220
221 pthread_mutex_init(&dev->bo_cache.lock, NULL);
222 list_inithead(&dev->bo_cache.lru);
223
224 for (unsigned i = 0; i < ARRAY_SIZE(dev->bo_cache.buckets); ++i)
225 list_inithead(&dev->bo_cache.buckets[i]);
226
227 /* Tiler heap is internally required by the tiler, which can only be
228 * active for a single job chain at once, so a single heap can be
229 * shared across batches/contextes */
230
231 dev->tiler_heap = panfrost_bo_create(dev, 4096 * 4096,
232 PAN_BO_INVISIBLE | PAN_BO_GROWABLE);
233 }
234
235 void
panfrost_close_device(struct panfrost_device * dev)236 panfrost_close_device(struct panfrost_device *dev)
237 {
238 panfrost_bo_unreference(dev->blit_shaders.bo);
239 panfrost_bo_unreference(dev->tiler_heap);
240 panfrost_bo_cache_evict_all(dev);
241 pthread_mutex_destroy(&dev->bo_cache.lock);
242 drmFreeVersion(dev->kernel_version);
243 util_sparse_array_finish(&dev->bo_map);
244
245 }
246