1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <platform_def.h>
9
10 #include <common/interrupt_props.h>
11 #include <drivers/arm/gicv3.h>
12 #include <lib/utils.h>
13 #include <plat/arm/common/plat_arm.h>
14 #include <plat/common/platform.h>
15
16 /******************************************************************************
17 * The following functions are defined as weak to allow a platform to override
18 * the way the GICv3 driver is initialised and used.
19 *****************************************************************************/
20 #pragma weak plat_arm_gic_driver_init
21 #pragma weak plat_arm_gic_init
22 #pragma weak plat_arm_gic_cpuif_enable
23 #pragma weak plat_arm_gic_cpuif_disable
24 #pragma weak plat_arm_gic_pcpu_init
25 #pragma weak plat_arm_gic_redistif_on
26 #pragma weak plat_arm_gic_redistif_off
27
28 /* The GICv3 driver only needs to be initialized in EL3 */
29 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
30
31 /* Default GICR base address to be used for GICR probe. */
32 static const uintptr_t gicr_base_addrs[2] = {
33 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
34 0U /* Zero Termination */
35 };
36
37 /* List of zero terminated GICR frame addresses which CPUs will probe */
38 static const uintptr_t *gicr_frames = gicr_base_addrs;
39
40 static const interrupt_prop_t arm_interrupt_props[] = {
41 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
42 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
43 };
44
45 /*
46 * We save and restore the GICv3 context on system suspend. Allocate the
47 * data in the designated EL3 Secure carve-out memory. The `used` attribute
48 * is used to prevent the compiler from removing the gicv3 contexts.
49 */
50 static gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram") __used;
51 static gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram") __used;
52
53 /* Define accessor function to get reference to the GICv3 context */
54 DEFINE_LOAD_SYM_ADDR(rdist_ctx)
DEFINE_LOAD_SYM_ADDR(dist_ctx)55 DEFINE_LOAD_SYM_ADDR(dist_ctx)
56
57 /*
58 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
59 * to core position.
60 *
61 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
62 * values read from GICR_TYPER don't have an MT field. To reuse the same
63 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
64 * that read from GICR_TYPER.
65 *
66 * Assumptions:
67 *
68 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
69 * - No CPUs implemented in the system use affinity level 3.
70 */
71 static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
72 {
73 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
74 return plat_arm_calc_core_pos(mpidr);
75 }
76
77 static const gicv3_driver_data_t arm_gic_data __unused = {
78 .gicd_base = PLAT_ARM_GICD_BASE,
79 .gicr_base = 0U,
80 .interrupt_props = arm_interrupt_props,
81 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
82 .rdistif_num = PLATFORM_CORE_COUNT,
83 .rdistif_base_addrs = rdistif_base_addrs,
84 .mpidr_to_core_pos = arm_gicv3_mpidr_hash
85 };
86
87 /*
88 * By default, gicr_frames will be pointing to gicr_base_addrs. If
89 * the platform supports a non-contiguous GICR frames (GICR frames located
90 * at uneven offset), plat_arm_override_gicr_frames function can be used by
91 * such platform to override the gicr_frames.
92 */
plat_arm_override_gicr_frames(const uintptr_t * plat_gicr_frames)93 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames)
94 {
95 assert(plat_gicr_frames != NULL);
96 gicr_frames = plat_gicr_frames;
97 }
98
plat_arm_gic_driver_init(void)99 void __init plat_arm_gic_driver_init(void)
100 {
101 /*
102 * The GICv3 driver is initialized in EL3 and does not need
103 * to be initialized again in SEL1. This is because the S-EL1
104 * can use GIC system registers to manage interrupts and does
105 * not need GIC interface base addresses to be configured.
106 */
107 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
108 (defined(__aarch64__) && defined(IMAGE_BL31))
109 gicv3_driver_init(&arm_gic_data);
110
111 if (gicv3_rdistif_probe(gicr_base_addrs[0]) == -1) {
112 ERROR("No GICR base frame found for Primary CPU\n");
113 panic();
114 }
115 #endif
116 }
117
118 /******************************************************************************
119 * ARM common helper to initialize the GIC. Only invoked by BL31
120 *****************************************************************************/
plat_arm_gic_init(void)121 void __init plat_arm_gic_init(void)
122 {
123 gicv3_distif_init();
124 gicv3_rdistif_init(plat_my_core_pos());
125 gicv3_cpuif_enable(plat_my_core_pos());
126 }
127
128 /******************************************************************************
129 * ARM common helper to enable the GIC CPU interface
130 *****************************************************************************/
plat_arm_gic_cpuif_enable(void)131 void plat_arm_gic_cpuif_enable(void)
132 {
133 gicv3_cpuif_enable(plat_my_core_pos());
134 }
135
136 /******************************************************************************
137 * ARM common helper to disable the GIC CPU interface
138 *****************************************************************************/
plat_arm_gic_cpuif_disable(void)139 void plat_arm_gic_cpuif_disable(void)
140 {
141 gicv3_cpuif_disable(plat_my_core_pos());
142 }
143
144 /******************************************************************************
145 * ARM common helper function to iterate over all GICR frames and discover the
146 * corresponding per-cpu redistributor frame as well as initialize the
147 * corresponding interface in GICv3.
148 *****************************************************************************/
plat_arm_gic_pcpu_init(void)149 void plat_arm_gic_pcpu_init(void)
150 {
151 int result;
152 const uintptr_t *plat_gicr_frames = gicr_frames;
153
154 do {
155 result = gicv3_rdistif_probe(*plat_gicr_frames);
156
157 /* If the probe is successful, no need to proceed further */
158 if (result == 0)
159 break;
160
161 plat_gicr_frames++;
162 } while (*plat_gicr_frames != 0U);
163
164 if (result == -1) {
165 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
166 panic();
167 }
168 gicv3_rdistif_init(plat_my_core_pos());
169 }
170
171 /******************************************************************************
172 * ARM common helpers to power GIC redistributor interface
173 *****************************************************************************/
plat_arm_gic_redistif_on(void)174 void plat_arm_gic_redistif_on(void)
175 {
176 gicv3_rdistif_on(plat_my_core_pos());
177 }
178
plat_arm_gic_redistif_off(void)179 void plat_arm_gic_redistif_off(void)
180 {
181 gicv3_rdistif_off(plat_my_core_pos());
182 }
183
184 /******************************************************************************
185 * ARM common helper to save & restore the GICv3 on resume from system suspend
186 *****************************************************************************/
plat_arm_gic_save(void)187 void plat_arm_gic_save(void)
188 {
189 gicv3_redist_ctx_t * const rdist_context =
190 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
191 gicv3_dist_ctx_t * const dist_context =
192 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
193
194 /*
195 * If an ITS is available, save its context before
196 * the Redistributor using:
197 * gicv3_its_save_disable(gits_base, &its_ctx[i])
198 * Additionally, an implementation-defined sequence may
199 * be required to save the whole ITS state.
200 */
201
202 /*
203 * Save the GIC Redistributors and ITS contexts before the
204 * Distributor context. As we only handle SYSTEM SUSPEND API,
205 * we only need to save the context of the CPU that is issuing
206 * the SYSTEM SUSPEND call, i.e. the current CPU.
207 */
208 gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
209
210 /* Save the GIC Distributor context */
211 gicv3_distif_save(dist_context);
212
213 /*
214 * From here, all the components of the GIC can be safely powered down
215 * as long as there is an alternate way to handle wakeup interrupt
216 * sources.
217 */
218 }
219
plat_arm_gic_resume(void)220 void plat_arm_gic_resume(void)
221 {
222 const gicv3_redist_ctx_t *rdist_context =
223 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
224 const gicv3_dist_ctx_t *dist_context =
225 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
226
227 /* Restore the GIC Distributor context */
228 gicv3_distif_init_restore(dist_context);
229
230 /*
231 * Restore the GIC Redistributor and ITS contexts after the
232 * Distributor context. As we only handle SYSTEM SUSPEND API,
233 * we only need to restore the context of the CPU that issued
234 * the SYSTEM SUSPEND call.
235 */
236 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
237
238 /*
239 * If an ITS is available, restore its context after
240 * the Redistributor using:
241 * gicv3_its_restore(gits_base, &its_ctx[i])
242 * An implementation-defined sequence may be required to
243 * restore the whole ITS state. The ITS must also be
244 * re-enabled after this sequence has been executed.
245 */
246 }
247