1 /*
2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <platform_def.h>
8
9 #include <common/bl_common.h>
10 #include <common/interrupt_props.h>
11 #include <drivers/arm/gicv3.h>
12 #include <drivers/arm/arm_gicv3_common.h>
13 #include <lib/mmio.h>
14 #include <lib/utils.h>
15 #include <plat/common/platform.h>
16
17 #include <plat_imx8.h>
18
19 /* the GICv3 driver only needs to be initialized in EL3 */
20 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
21
22 static const interrupt_prop_t g01s_interrupt_props[] = {
23 INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY,
24 INTR_GROUP0, GIC_INTR_CFG_LEVEL),
25 #if SDEI_SUPPORT
26 INTR_PROP_DESC(PLAT_SDEI_SGI_PRIVATE, PLAT_SDEI_NORMAL_PRI,
27 INTR_GROUP0, GIC_INTR_CFG_LEVEL),
28 #endif
29 };
30
plat_imx_mpidr_to_core_pos(unsigned long mpidr)31 static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr)
32 {
33 return (unsigned int)plat_core_pos_by_mpidr(mpidr);
34 }
35
36 const gicv3_driver_data_t arm_gic_data = {
37 .gicd_base = PLAT_GICD_BASE,
38 .gicr_base = PLAT_GICR_BASE,
39 .interrupt_props = g01s_interrupt_props,
40 .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
41 .rdistif_num = PLATFORM_CORE_COUNT,
42 .rdistif_base_addrs = rdistif_base_addrs,
43 .mpidr_to_core_pos = plat_imx_mpidr_to_core_pos,
44 };
45
plat_gic_driver_init(void)46 void plat_gic_driver_init(void)
47 {
48 /*
49 * the GICv3 driver is initialized in EL3 and does not need
50 * to be initialized again in S-EL1. This is because the S-EL1
51 * can use GIC system registers to manage interrupts and does
52 * not need GIC interface base addresses to be configured.
53 */
54 #if IMAGE_BL31
55 gicv3_driver_init(&arm_gic_data);
56 #endif
57 }
58
plat_gicr_exit_sleep(void)59 static __inline void plat_gicr_exit_sleep(void)
60 {
61 unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER);
62
63 /*
64 * ProcessorSleep bit can ONLY be set to zero when
65 * Quiescent bit and Sleep bit are both zero, so
66 * need to make sure Quiescent bit and Sleep bit
67 * are zero before clearing ProcessorSleep bit.
68 */
69 if (val & WAKER_QSC_BIT) {
70 mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT);
71 /* Wait till the WAKER_QSC_BIT changes to 0 */
72 while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U)
73 ;
74 }
75 }
76
plat_gic_init(void)77 void plat_gic_init(void)
78 {
79 plat_gicr_exit_sleep();
80 gicv3_distif_init();
81 gicv3_rdistif_init(plat_my_core_pos());
82 gicv3_cpuif_enable(plat_my_core_pos());
83 }
84
plat_gic_cpuif_enable(void)85 void plat_gic_cpuif_enable(void)
86 {
87 gicv3_cpuif_enable(plat_my_core_pos());
88 }
89
plat_gic_cpuif_disable(void)90 void plat_gic_cpuif_disable(void)
91 {
92 gicv3_cpuif_disable(plat_my_core_pos());
93 }
94
plat_gic_pcpu_init(void)95 void plat_gic_pcpu_init(void)
96 {
97 gicv3_rdistif_init(plat_my_core_pos());
98 }
99
plat_gic_save(unsigned int proc_num,struct plat_gic_ctx * ctx)100 void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx)
101 {
102 /* save the gic rdist/dist context */
103 for (int i = 0; i < PLATFORM_CORE_COUNT; i++)
104 gicv3_rdistif_save(i, &ctx->rdist_ctx[i]);
105 gicv3_distif_save(&ctx->dist_ctx);
106 }
107
plat_gic_restore(unsigned int proc_num,struct plat_gic_ctx * ctx)108 void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx)
109 {
110 /* restore the gic rdist/dist context */
111 gicv3_distif_init_restore(&ctx->dist_ctx);
112 for (int i = 0; i < PLATFORM_CORE_COUNT; i++)
113 gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]);
114 }
115