1 /*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <platform_def.h>
11
12 #include <common/debug.h>
13 #include <drivers/delay_timer.h>
14 #include <drivers/gpio.h>
15 #include <lib/mmio.h>
16 #include <plat/common/platform.h>
17
18 #include <plat_private.h>
19 #include <soc.h>
20
21 uint32_t gpio_port[] = {
22 GPIO0_BASE,
23 GPIO1_BASE,
24 GPIO2_BASE,
25 GPIO3_BASE,
26 GPIO4_BASE,
27 };
28
29 struct {
30 uint32_t swporta_dr;
31 uint32_t swporta_ddr;
32 uint32_t inten;
33 uint32_t intmask;
34 uint32_t inttype_level;
35 uint32_t int_polarity;
36 uint32_t debounce;
37 uint32_t ls_sync;
38 } store_gpio[3];
39
40 static uint32_t store_grf_gpio[(GRF_GPIO2D_HE - GRF_GPIO2A_IOMUX) / 4 + 1];
41
42 #define SWPORTA_DR 0x00
43 #define SWPORTA_DDR 0x04
44 #define INTEN 0x30
45 #define INTMASK 0x34
46 #define INTTYPE_LEVEL 0x38
47 #define INT_POLARITY 0x3c
48 #define DEBOUNCE 0x48
49 #define LS_SYNC 0x60
50
51 #define EXT_PORTA 0x50
52 #define PMU_GPIO_PORT0 0
53 #define PMU_GPIO_PORT1 1
54 #define GPIO_PORT2 2
55 #define GPIO_PORT3 3
56 #define GPIO_PORT4 4
57
58 #define PMU_GRF_GPIO0A_P 0x40
59 #define GRF_GPIO2A_P 0xe040
60 #define GPIO_P_MASK 0x03
61
62 #define GET_GPIO_PORT(pin) (pin / 32)
63 #define GET_GPIO_NUM(pin) (pin % 32)
64 #define GET_GPIO_BANK(pin) ((pin % 32) / 8)
65 #define GET_GPIO_ID(pin) ((pin % 32) % 8)
66
67 /* returns old clock state, enables clock, in order to do GPIO access */
gpio_get_clock(uint32_t gpio_number)68 static int gpio_get_clock(uint32_t gpio_number)
69 {
70 uint32_t port = GET_GPIO_PORT(gpio_number);
71 uint32_t clock_state = 0;
72
73 assert(port < 5);
74
75 switch (port) {
76 case PMU_GPIO_PORT0:
77 clock_state = (mmio_read_32(PMUCRU_BASE +
78 CRU_PMU_CLKGATE_CON(1)) >>
79 PCLK_GPIO0_GATE_SHIFT) & 0x01;
80 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
81 BITS_WITH_WMASK(0, CLK_GATE_MASK,
82 PCLK_GPIO0_GATE_SHIFT));
83 break;
84 case PMU_GPIO_PORT1:
85 clock_state = (mmio_read_32(PMUCRU_BASE +
86 CRU_PMU_CLKGATE_CON(1)) >>
87 PCLK_GPIO1_GATE_SHIFT) & 0x01;
88 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
89 BITS_WITH_WMASK(0, CLK_GATE_MASK,
90 PCLK_GPIO1_GATE_SHIFT));
91 break;
92 case GPIO_PORT2:
93 clock_state = (mmio_read_32(CRU_BASE +
94 CRU_CLKGATE_CON(31)) >>
95 PCLK_GPIO2_GATE_SHIFT) & 0x01;
96 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
97 BITS_WITH_WMASK(0, CLK_GATE_MASK,
98 PCLK_GPIO2_GATE_SHIFT));
99 break;
100 case GPIO_PORT3:
101 clock_state = (mmio_read_32(CRU_BASE +
102 CRU_CLKGATE_CON(31)) >>
103 PCLK_GPIO3_GATE_SHIFT) & 0x01;
104 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
105 BITS_WITH_WMASK(0, CLK_GATE_MASK,
106 PCLK_GPIO3_GATE_SHIFT));
107 break;
108 case GPIO_PORT4:
109 clock_state = (mmio_read_32(CRU_BASE +
110 CRU_CLKGATE_CON(31)) >>
111 PCLK_GPIO4_GATE_SHIFT) & 0x01;
112 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
113 BITS_WITH_WMASK(0, CLK_GATE_MASK,
114 PCLK_GPIO4_GATE_SHIFT));
115 break;
116 default:
117 break;
118 }
119
120 return clock_state;
121 }
122
123 /* restores old state of gpio clock */
gpio_put_clock(uint32_t gpio_number,uint32_t clock_state)124 void gpio_put_clock(uint32_t gpio_number, uint32_t clock_state)
125 {
126 uint32_t port = GET_GPIO_PORT(gpio_number);
127
128 switch (port) {
129 case PMU_GPIO_PORT0:
130 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
131 BITS_WITH_WMASK(clock_state, CLK_GATE_MASK,
132 PCLK_GPIO0_GATE_SHIFT));
133 break;
134 case PMU_GPIO_PORT1:
135 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
136 BITS_WITH_WMASK(clock_state, CLK_GATE_MASK,
137 PCLK_GPIO1_GATE_SHIFT));
138 break;
139 case GPIO_PORT2:
140 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
141 BITS_WITH_WMASK(clock_state, CLK_GATE_MASK,
142 PCLK_GPIO2_GATE_SHIFT));
143 break;
144 case GPIO_PORT3:
145 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
146 BITS_WITH_WMASK(clock_state, CLK_GATE_MASK,
147 PCLK_GPIO3_GATE_SHIFT));
148
149 break;
150 case GPIO_PORT4:
151 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
152 BITS_WITH_WMASK(clock_state, CLK_GATE_MASK,
153 PCLK_GPIO4_GATE_SHIFT));
154 break;
155 default:
156 break;
157 }
158 }
159
get_pull(int gpio)160 static int get_pull(int gpio)
161 {
162 uint32_t port = GET_GPIO_PORT(gpio);
163 uint32_t bank = GET_GPIO_BANK(gpio);
164 uint32_t id = GET_GPIO_ID(gpio);
165 uint32_t val, clock_state;
166
167 assert((port < 5) && (bank < 4));
168
169 clock_state = gpio_get_clock(gpio);
170
171 if (port == PMU_GPIO_PORT0 || port == PMU_GPIO_PORT1) {
172 val = mmio_read_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P +
173 port * 16 + bank * 4);
174 val = (val >> (id * 2)) & GPIO_P_MASK;
175 } else {
176 val = mmio_read_32(GRF_BASE + GRF_GPIO2A_P +
177 (port - 2) * 16 + bank * 4);
178 val = (val >> (id * 2)) & GPIO_P_MASK;
179 }
180 gpio_put_clock(gpio, clock_state);
181
182 /*
183 * in gpio0a, gpio0b, gpio2c, gpio2d,
184 * 00: Z
185 * 01: pull down
186 * 10: Z
187 * 11: pull up
188 * different with other gpio, so need to correct it
189 */
190 if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) {
191 if (val == 3)
192 val = GPIO_PULL_UP;
193 else if (val == 1)
194 val = GPIO_PULL_DOWN;
195 else
196 val = 0;
197 }
198
199 return val;
200 }
201
set_pull(int gpio,int pull)202 static void set_pull(int gpio, int pull)
203 {
204 uint32_t port = GET_GPIO_PORT(gpio);
205 uint32_t bank = GET_GPIO_BANK(gpio);
206 uint32_t id = GET_GPIO_ID(gpio);
207 uint32_t clock_state;
208
209 assert((port < 5) && (bank < 4));
210
211 clock_state = gpio_get_clock(gpio);
212
213 /*
214 * in gpio0a, gpio0b, gpio2c, gpio2d,
215 * 00: Z
216 * 01: pull down
217 * 10: Z
218 * 11: pull up
219 * different with other gpio, so need to correct it
220 */
221 if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) {
222 if (pull == GPIO_PULL_UP)
223 pull = 3;
224 else if (pull == GPIO_PULL_DOWN)
225 pull = 1;
226 else
227 pull = 0;
228 }
229
230 if (port == PMU_GPIO_PORT0 || port == PMU_GPIO_PORT1) {
231 mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P +
232 port * 16 + bank * 4,
233 BITS_WITH_WMASK(pull, GPIO_P_MASK, id * 2));
234 } else {
235 mmio_write_32(GRF_BASE + GRF_GPIO2A_P +
236 (port - 2) * 16 + bank * 4,
237 BITS_WITH_WMASK(pull, GPIO_P_MASK, id * 2));
238 }
239 gpio_put_clock(gpio, clock_state);
240 }
241
set_direction(int gpio,int direction)242 static void set_direction(int gpio, int direction)
243 {
244 uint32_t port = GET_GPIO_PORT(gpio);
245 uint32_t num = GET_GPIO_NUM(gpio);
246 uint32_t clock_state;
247
248 assert((port < 5) && (num < 32));
249
250 clock_state = gpio_get_clock(gpio);
251
252 /*
253 * in gpio.h
254 * #define GPIO_DIR_OUT 0
255 * #define GPIO_DIR_IN 1
256 * but rk3399 gpio direction 1: output, 0: input
257 * so need to revert direction value
258 */
259 mmio_setbits_32(gpio_port[port] + SWPORTA_DDR, !direction << num);
260 gpio_put_clock(gpio, clock_state);
261 }
262
get_direction(int gpio)263 static int get_direction(int gpio)
264 {
265 uint32_t port = GET_GPIO_PORT(gpio);
266 uint32_t num = GET_GPIO_NUM(gpio);
267 int direction, clock_state;
268
269 assert((port < 5) && (num < 32));
270
271 clock_state = gpio_get_clock(gpio);
272
273 /*
274 * in gpio.h
275 * #define GPIO_DIR_OUT 0
276 * #define GPIO_DIR_IN 1
277 * but rk3399 gpio direction 1: output, 0: input
278 * so need to revert direction value
279 */
280 direction = !((mmio_read_32(gpio_port[port] +
281 SWPORTA_DDR) >> num) & 0x1);
282 gpio_put_clock(gpio, clock_state);
283
284 return direction;
285 }
286
get_value(int gpio)287 static int get_value(int gpio)
288 {
289 uint32_t port = GET_GPIO_PORT(gpio);
290 uint32_t num = GET_GPIO_NUM(gpio);
291 int value, clock_state;
292
293 assert((port < 5) && (num < 32));
294
295 clock_state = gpio_get_clock(gpio);
296 value = (mmio_read_32(gpio_port[port] + EXT_PORTA) >> num) & 0x1;
297 gpio_put_clock(gpio, clock_state);
298
299 return value;
300 }
301
set_value(int gpio,int value)302 static void set_value(int gpio, int value)
303 {
304 uint32_t port = GET_GPIO_PORT(gpio);
305 uint32_t num = GET_GPIO_NUM(gpio);
306 uint32_t clock_state;
307
308 assert((port < 5) && (num < 32));
309
310 clock_state = gpio_get_clock(gpio);
311 mmio_clrsetbits_32(gpio_port[port] + SWPORTA_DR, 1 << num,
312 !!value << num);
313 gpio_put_clock(gpio, clock_state);
314 }
315
plat_rockchip_save_gpio(void)316 void plat_rockchip_save_gpio(void)
317 {
318 int i;
319 uint32_t cru_gate_save;
320
321 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31));
322
323 /*
324 * when shutdown logic, we need to save gpio2 ~ gpio4 register,
325 * we need to enable gpio2 ~ gpio4 clock here, since it may be gating,
326 * and we do not care gpio0 and gpio1 clock gate, since we never
327 * gating them
328 */
329 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
330 BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
331
332 /*
333 * since gpio0, gpio1 are pmugpio, they will keep ther value
334 * when shutdown logic power rail, so only need to save gpio2 ~ gpio4
335 * register value
336 */
337 for (i = 2; i < 5; i++) {
338 store_gpio[i - 2].swporta_dr =
339 mmio_read_32(gpio_port[i] + SWPORTA_DR);
340 store_gpio[i - 2].swporta_ddr =
341 mmio_read_32(gpio_port[i] + SWPORTA_DDR);
342 store_gpio[i - 2].inten =
343 mmio_read_32(gpio_port[i] + INTEN);
344 store_gpio[i - 2].intmask =
345 mmio_read_32(gpio_port[i] + INTMASK);
346 store_gpio[i - 2].inttype_level =
347 mmio_read_32(gpio_port[i] + INTTYPE_LEVEL);
348 store_gpio[i - 2].int_polarity =
349 mmio_read_32(gpio_port[i] + INT_POLARITY);
350 store_gpio[i - 2].debounce =
351 mmio_read_32(gpio_port[i] + DEBOUNCE);
352 store_gpio[i - 2].ls_sync =
353 mmio_read_32(gpio_port[i] + LS_SYNC);
354 }
355 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
356 cru_gate_save | REG_SOC_WMSK);
357
358 /*
359 * gpio0, gpio1 in pmuiomux, they will keep ther value
360 * when shutdown logic power rail, so only need to save gpio2 ~ gpio4
361 * iomux register value
362 */
363 for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++)
364 store_grf_gpio[i] =
365 mmio_read_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4);
366 }
367
plat_rockchip_restore_gpio(void)368 void plat_rockchip_restore_gpio(void)
369 {
370 int i;
371 uint32_t cru_gate_save;
372
373 for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++)
374 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,
375 REG_SOC_WMSK | store_grf_gpio[i]);
376
377 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31));
378
379 /*
380 * when shutdown logic, we need to save gpio2 ~ gpio4 register,
381 * we need to enable gpio2 ~ gpio4 clock here, since it may be gating,
382 * and we do not care gpio0 and gpio1 clock gate, since we never
383 * gating them
384 */
385 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
386 BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
387
388 for (i = 2; i < 5; i++) {
389 mmio_write_32(gpio_port[i] + SWPORTA_DR,
390 store_gpio[i - 2].swporta_dr);
391 mmio_write_32(gpio_port[i] + SWPORTA_DDR,
392 store_gpio[i - 2].swporta_ddr);
393 mmio_write_32(gpio_port[i] + INTEN, store_gpio[i - 2].inten);
394 mmio_write_32(gpio_port[i] + INTMASK,
395 store_gpio[i - 2].intmask);
396 mmio_write_32(gpio_port[i] + INTTYPE_LEVEL,
397 store_gpio[i - 2].inttype_level);
398 mmio_write_32(gpio_port[i] + INT_POLARITY,
399 store_gpio[i - 2].int_polarity);
400 mmio_write_32(gpio_port[i] + DEBOUNCE,
401 store_gpio[i - 2].debounce);
402 mmio_write_32(gpio_port[i] + LS_SYNC,
403 store_gpio[i - 2].ls_sync);
404 }
405 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
406 cru_gate_save | REG_SOC_WMSK);
407 }
408
409 const gpio_ops_t rk3399_gpio_ops = {
410 .get_direction = get_direction,
411 .set_direction = set_direction,
412 .get_value = get_value,
413 .set_value = set_value,
414 .set_pull = set_pull,
415 .get_pull = get_pull,
416 };
417
plat_rockchip_gpio_init(void)418 void plat_rockchip_gpio_init(void)
419 {
420 gpio_init(&rk3399_gpio_ops);
421 }
422