1 /*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 #include <lib/mmio.h>
9 #include <plat/common/platform.h>
10
11 #include <mss_mem.h>
12 #include <plat_pm_trace.h>
13
14 #ifdef PM_TRACE_ENABLE
15
16 /* core trace APIs */
17 core_trace_func funcTbl[PLATFORM_CORE_COUNT] = {
18 pm_core_0_trace,
19 pm_core_1_trace,
20 pm_core_2_trace,
21 pm_core_3_trace};
22
23 /*****************************************************************************
24 * pm_core0_trace
25 * pm_core1_trace
26 * pm_core2_trace
27 * pm_core_3trace
28 *
29 * This functions set trace info into core cyclic trace queue in MSS SRAM
30 * memory space
31 *****************************************************************************
32 */
pm_core_0_trace(unsigned int trace)33 void pm_core_0_trace(unsigned int trace)
34 {
35 unsigned int current_position_core_0 =
36 mmio_read_32(AP_MSS_ATF_CORE_0_CTRL_BASE);
37 mmio_write_32((AP_MSS_ATF_CORE_0_INFO_BASE +
38 (current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
39 mmio_read_32(AP_MSS_TIMER_BASE));
40 mmio_write_32((AP_MSS_ATF_CORE_0_INFO_TRACE +
41 (current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
42 trace);
43 mmio_write_32(AP_MSS_ATF_CORE_0_CTRL_BASE,
44 ((current_position_core_0 + 1) &
45 AP_MSS_ATF_TRACE_SIZE_MASK));
46 }
47
pm_core_1_trace(unsigned int trace)48 void pm_core_1_trace(unsigned int trace)
49 {
50 unsigned int current_position_core_1 =
51 mmio_read_32(AP_MSS_ATF_CORE_1_CTRL_BASE);
52 mmio_write_32((AP_MSS_ATF_CORE_1_INFO_BASE +
53 (current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
54 mmio_read_32(AP_MSS_TIMER_BASE));
55 mmio_write_32((AP_MSS_ATF_CORE_1_INFO_TRACE +
56 (current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
57 trace);
58 mmio_write_32(AP_MSS_ATF_CORE_1_CTRL_BASE,
59 ((current_position_core_1 + 1) &
60 AP_MSS_ATF_TRACE_SIZE_MASK));
61 }
62
pm_core_2_trace(unsigned int trace)63 void pm_core_2_trace(unsigned int trace)
64 {
65 unsigned int current_position_core_2 =
66 mmio_read_32(AP_MSS_ATF_CORE_2_CTRL_BASE);
67 mmio_write_32((AP_MSS_ATF_CORE_2_INFO_BASE +
68 (current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
69 mmio_read_32(AP_MSS_TIMER_BASE));
70 mmio_write_32((AP_MSS_ATF_CORE_2_INFO_TRACE +
71 (current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
72 trace);
73 mmio_write_32(AP_MSS_ATF_CORE_2_CTRL_BASE,
74 ((current_position_core_2 + 1) &
75 AP_MSS_ATF_TRACE_SIZE_MASK));
76 }
77
pm_core_3_trace(unsigned int trace)78 void pm_core_3_trace(unsigned int trace)
79 {
80 unsigned int current_position_core_3 =
81 mmio_read_32(AP_MSS_ATF_CORE_3_CTRL_BASE);
82 mmio_write_32((AP_MSS_ATF_CORE_3_INFO_BASE +
83 (current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
84 mmio_read_32(AP_MSS_TIMER_BASE));
85 mmio_write_32((AP_MSS_ATF_CORE_3_INFO_TRACE +
86 (current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
87 trace);
88 mmio_write_32(AP_MSS_ATF_CORE_3_CTRL_BASE,
89 ((current_position_core_3 + 1) &
90 AP_MSS_ATF_TRACE_SIZE_MASK));
91 }
92 #endif /* PM_TRACE_ENABLE */
93